Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
  • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
  • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

• the present invention generally relates to the field of semiconductor devices and methods of interconnecting them.
• MOSFETs metal-oxide semiconductor field effect transistors
• CMOS complementary metal-oxide semiconductor
• a conventional process may require 18 masks for a 3 metal layer process. The complexity of such a process increases the fabrication costs, errors, and also problems with latch-up.
• Bipolar devices are also susceptible to the same problems as MOSFETs with high on-state resistance due to the parasitic resistance of the metal interconnects for similar reasons.
• the present invention discloses a system for interconnecting regions on a semiconductor substrate using wide metal runners or a planar interconnection layer, and a plurality of solder bumps on conductive pads arranged in a checkerboard pattern or interleaved, thereby reducing parasitic resistance.
• the interconnections may be used for connecting discrete as well as integrated devices.
• the preferred embodiment of the present invention uses conventional CMOS fabrication processes to fabricate a semiconductor device embodying the present invention to reduce the costs of production. In accordance with one aspect of the present invention, however, only one type of MOSFETs (either an n-channel or p-channel MOSFET) is made on the die. Since the device of the present invention only consists of parallel n-channel or p-channel transistors, the problem of latch-up is avoided. [0012] In another preferred embodiment no field implants are used, although alternate embodiments may use field implants if there is more than one transistor on a die.
• a self- aligned sicilide is formed over the source, drain and gate of the transistor.
• FIG. la shows one embodiment of the present invention in perspective view.
• a portion of a semiconductor device 100 having two sources 110 and a drain 120 In the illustrative example, device 100 is shown with a P substrate 105. In another embodiment, P substrate 105 is deposited on top of a P- substrate (not shown).
• Sources 110 and drain 120 are preferably n-type dopant implants into P substrate 105. It will be appreciated that variations of the design of the sources and drains are known to one skilled in the art and within the scope of the present invention. For example, sources 110 and drain 120 could be p-type dopant implants into an N substrate 105.
• FIG lb shows a preferred embodiment where sources 110B is comprised of a region 112 which is doped as N+, region 114 which is doped as P+ and region 116 which is doped an N.
• source 110B is comprised of region 114 doped as P+, and regions 112 and 116 are N+ implants adjacent to either side of the P+ region 114.
• regions 112 and 114 also have a region 118. Region 118 may be a lightly doped N- implant while the rest of regions 112 and 114 are N+. Region 118's lightly doped N- implant functions as a lightly doped drain.
• drain 120B in this example, is comprised of region 124 doped as N+ and regions 124 and 126 doped as N.
• gate 130 is comprised of a polysilicon gate over a SiO 2 or Si 3 N 4 insulating layer (not shown) and is placed between source 110 and drain 120. Adjacent to gate 130 are spacers 132 and 134, preferably comprised of SiO 2 or Si N 4 , and partially extending over source 110 and drain 120, respectively. (FIG. lb also shows spacers 132 and 134 extending over regions 118 and 122. Spacers also extend over region 126.)
• Source runners 140 and drain runners 150 are formed on a first interconnect layer and is preferably comprised of metal, although other conductive materials may be used.
• multiple sources 110 are interconnected by source runner 140 using vias 142.
• source runner 140 is in a substantially orthogonal orientation to source 110 and drain 120, although other orientations that are not orthogonal (for instance, angled or even parallel) may be used.
• Drains 120 are interconnected by drain runners 150 using vias> 152.
• drain runner 150 is in a substantially orthogonal orientation to drain 120, although other orientations that are not orthogonal (for instance, angled or even parallel) may be used.
• FIG. la also shows source runners 160 and drain runners 170 formed on a second interconnect layer and is preferably comprised of metal, although other conductive materials may be used.
• Source runner 160 interconnects source runners 140 using vias 162.
• Preferably source runners 160 are in a substantially parallel orientation with respect to source 110, although other orientations that are not parallel (for instance, angled) may be used.
• Drain runners 150 are interconnected by drain runners 170 using vias 172.
• drain runner 170 is in a substantially parallel orientation with respect to drain 120, although other orientations that are not parallel (for instance, angled) may be used.
• FIG. la shows source pad 180 formed on a third interconnect layer, which is preferably comprised of metal, although other conductive materials may be used. Source pad 180 is connected to source runners 160 using vias 182. Also shown is solder bump 184 formed on source pad 180. Although not shown in FIG.
• drain pads see FIG. lc, drain pad 190 as an example
• solder bumps connect drain runners 170 via solder bumps and likewise for gate pads and solder bumps. These solder bumps provide connections between the sources 110, drains 120, and gates 130 with external circuits.
• the vias (for instance vias 142, 152, 162, 172 and 182) form conductive interconnects and are comprised preferably out of tungsten, although other conductive material may be used. These are formed in a manner that are well-known to those skilled in the art.
• FIG. lc shows an embodiment similar to FIG. la except there is no second interconnect layer forming source runners 160 and drain runners 170. Instead, drain pad 190 is formed on the second interconnect layer and is connected to drain runners 150 by vias 172. Solder bump 194 is formed on drain pad 190. Although not shown in FIG. lc for the sake of clarity, similar source pads and solder bumps connect source runners 140. [0032] Referring now to FIG. 2 there is shown a top plan view of the embodiment shown in FIG. la and showing additional sources 110, drains 120 and first layer interconnect source runners 140 and drain runners 150.
• Sources 110 and drains 120 are shown having a substantially vertical orientation while source runners 140 and drain runners 150 are shown in a substantially horizontal orientation. Also shown are vias 142 and 152 interconnecting the source runners 140 and drain runners 150 to sources 110 and drains 120, respectively. It should be noted that although FIG. 2, for instance, shows at a point of connection the use of two vias, one via could be used, as shown in FIG. 3a, or more than two, as shown in FIG. la for vias 182. [0033] Referring now to FIG. 3a there is shown a top plan view of the embodiment of FIG.
• Source runners 140 and drain runners 150 are laid out in a substantially horizontal orientation. Source runners 160 overlay source runners 140 and are interconnected using vias 162. Drain runners 170 overlay drain runners 150 and are interconnected using vias 172. Source pad 180 is shown in FIG. 3 A overlaying source runners 160 and drain runners 170, but is only connected to source runners 160 by vias 182. [0035] FIG. 3b shows a top plan view of the embodiment of FIG.
• Source runners 140 and drain runners 150 are laid out in a substantially horizontal orientation.
• Source runners 160 overlay source runners 140 and interconnect source runners 140 using vias 162.
• Drain runners 170 overlay drain runners 150 and interconnect drain runners 170 using vias 172.
• Drain pad 190 is shown overlaying source runners 160 and drain runners 170, but is only connected to drain runners 170 by vias 192.
• FIG. 4a shows the top of device 100 with source pads 180, analogous drain pads 300 and gate pads 400. Also shown are solder bumps 184 for the source pad, solder bumps 304 for the drain pads, and solder bumps 404 for the gate pads.
• the source and drain pads are arranged in a checkerboard layout.
• FIG. 4b shows an alternative layout where each source pad 410 and drain pad 420 are shaped as "stripes" and are interleaved with each other.
• gate pad 430 would be placed with a shortened source pad 410 or shortened drain pad 420 as needed.
• FIG. 5 Another embodiment of the present invention is shown in FIG. 5.
• sources 520 and drains 530 are laid out in a "checkerboard" pattern.
• a first interconnect layer forms a source connection layer 500 which interconnects sources 520 using vias 504.
• a second interconnect layer forms a drain connection layer 510 which connects drains 530 though vias 514, through openings in the first interconnect layer and using a cutout portion of that first layer to form connection 502. Drain connection layer 510 then connects to connection 502 using vias 516.
• a third interconnect layer (not shown) would also connect to source connection layer 500 using vias 506, connection 512 and a via connected to connection 512 (not shown).
• source connection layer 500, drain connection layer 510 and the third interconnection layer would be comprised of metal or another conductive material and the vias would be comprised of tungsten or other conductive material.
• This third interconnect layer would be connected to solder bumps in a manner similar to that shown in FIG. la.
• FIG. 6a and b show a top plan view.
• FIG. 6a shows source connection layer 500 with openings and cutouts 502 to permit connections to drains 530 from drain connection layer 510.
• FIG. 6b shows drain connection layer 510 for the drains with openings and cutouts 512 to permit access and contact to source connection layer 500, which connects to sources 520.
• FIG 5 As an example of interconnecting discrete components, if sources 520 and drains 530 were discrete components, those components are interconnected using the present invention in a manner described in more detail above with reference to FIG. 5 as an integrated device. Moreover, it is appreciated that more than two or three interconnect layers may be used and that there may be intermediate interconnect layers between, for instance, the first and second interconnect layers or between the second and third interconnect layers.

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Manufacturing & Machinery (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)
• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
• Electrodes Of Semiconductors (AREA)
• Semiconductor Integrated Circuits (AREA)

Priority Applications (2)

Applications Claiming Priority (4)

Publications (3)

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Cited By (5)

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• 2003
  • 2003-06-19 US US10/601,121 patent/US6972464B2/en not_active Expired - Lifetime
  • 2003-10-06 JP JP2005501099A patent/JP4641259B2/ja not_active Expired - Lifetime
  • 2003-10-06 WO PCT/US2003/031603 patent/WO2004034432A2/en not_active Ceased
  • 2003-10-06 AU AU2003284004A patent/AU2003284004A1/en not_active Abandoned
  • 2003-10-06 KR KR1020057006029A patent/KR101022867B1/ko not_active Expired - Fee Related

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