WO2004021427A1 - Plasma processing method and plasma processing device - Google Patents

Plasma processing method and plasma processing device Download PDF

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Publication number
WO2004021427A1
WO2004021427A1 PCT/JP2003/010937 JP0310937W WO2004021427A1 WO 2004021427 A1 WO2004021427 A1 WO 2004021427A1 JP 0310937 W JP0310937 W JP 0310937W WO 2004021427 A1 WO2004021427 A1 WO 2004021427A1
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WO
WIPO (PCT)
Prior art keywords
plasma processing
plasma
electrostatic chuck
processing method
semiconductor wafer
Prior art date
Application number
PCT/JP2003/010937
Other languages
French (fr)
Japanese (ja)
Inventor
Toshihiko Shindo
Shin Okamoto
Kimihiro Higuchi
Original Assignee
Tokyo Electron Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Limited filed Critical Tokyo Electron Limited
Priority to AU2003261790A priority Critical patent/AU2003261790A1/en
Publication of WO2004021427A1 publication Critical patent/WO2004021427A1/en
Priority to US11/066,260 priority patent/US7541283B2/en
Priority to US12/433,112 priority patent/US7799238B2/en
Priority to US12/686,899 priority patent/US8287750B2/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32431Constructional details of the reactor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/004Charge control of objects or beams
    • H01J2237/0041Neutralising arrangements
    • H01J2237/0044Neutralising arrangements of objects being observed or treated

Definitions

  • the present invention relates to a plasma processing method and a plasma processing apparatus, and more particularly to a plasma processing method and a plasma processing apparatus for performing a plasma etching process or the like on a substrate to be processed such as a semiconductor wafer or an LCD substrate.
  • a plasma processing method for processing a substrate to be processed such as a semiconductor wafer or an LCD substrate by using plasma has been frequently used.
  • a substrate to be processed such as a semiconductor wafer or an LCD substrate by using plasma
  • plasma plasma etching is often used to remove.
  • etching apparatus for performing such a plasma etching process
  • plasma is generated in a processing chamber (etching chamber) configured so that the inside can be hermetically closed. Then, a semiconductor wafer is placed on a susceptor provided in the etching chamber, and etching is performed.
  • various types of means for generating the plasma are known.
  • a device of the type that supplies high-frequency power to a pair of parallel plate electrodes provided so as to face each other up and down to generate plasma.
  • One of the parallel plate electrodes for example, the lower electrode also serves as a susceptor And a semiconductor wafer is placed on this lower electrode, A plasma is generated by applying a frequency voltage to perform etching.
  • the surface arcing often occurs, for example, when an insulator layer is formed on a conductor layer and the insulator layer is etched.
  • the insulator layer made of a silicon oxide film is etched to form a contact hole that leads to a conductor layer made of a lower metal layer, the silicon oxide film whose thickness has been reduced by etching is destroyed. In many cases, it occurs.
  • an object of the present invention is to provide a plasma processing method and a plasma processing apparatus which can prevent the occurrence of surface arcing on a substrate to be processed and can improve the productivity as compared with the related art. Things.
  • a plasma weaker than plasma used for the plasma processing is applied to the substrate before performing the plasma processing. And the state of electric charge of the substrate to be processed is kept constant, and thereafter, the plasma processing is performed. Further, in the plasma processing method of the present invention, in the plasma processing method, the weak plasma is applied to the substrate to be processed for a predetermined time, and thereafter, a DC voltage is applied to an electrostatic chuck for sucking and holding the substrate to be processed. It is characterized by applying.
  • the plasma processing method of the present invention is characterized in that in the above-described plasma processing method, before applying the weak plasma, application of a DC voltage to the electrostatic chuck is started.
  • the weak plasma is a plasma formed by an Ar gas, or a ⁇ 2 gas, or a CF 4 gas, or an N 2 gas. I do.
  • the plasma processing method of the present invention is characterized in that, in the above-mentioned plasma processing method, the weak plasma is formed by a high frequency power of 0.15 to 1.0 WZ cm 2.
  • the plasma processing method according to the present invention is the plasma processing method described above, wherein the weak plasma is applied to the substrate to be processed for 5 to 20 seconds.
  • the plasma processing method of the present invention in the above-described plasma processing method, at the start of the plasma processing, after the application of high-frequency power for generating plasma is started, the application of a DC voltage to the electrostatic chuck is started. The application of the high-frequency power is stopped after the application of the DC voltage to the electrostatic chuck is stopped at the end of the plasma processing.
  • a DC voltage of the electrostatic chuck is The application is started, and then the substrate is lowered and placed on the electrostatic chuck. It is characterized by doing.
  • the plasma processing method of the present invention is characterized in that in the above-mentioned plasma processing method, the plasma processing is an etching processing, and the weak plasma is applied to the substrate to be processed in a processing chamber for performing the etching processing.
  • the plasma processing apparatus of the present invention is a plasma processing apparatus including a plasma processing mechanism for performing a plasma processing on a substrate to be processed, wherein the control unit controls the plasma processing mechanism and performs the plasma processing method. It is characterized by having. BRIEF DESCRIPTION OF THE FIGURES
  • FIG. 1 is a diagram schematically showing a schematic configuration of an apparatus used in an embodiment of the present invention.
  • FIG. 2 is a view for explaining a plasma processing method according to one embodiment of the present invention.
  • FIG. 3 is a diagram schematically showing a schematic configuration of an apparatus used in another embodiment of the present invention.
  • FIG. 4 is a view for explaining a plasma processing method according to another embodiment of the present invention.
  • FIG. 5 is a view for explaining a plasma processing method according to a modification of the embodiment shown in FIG.
  • FIG. 6 is a diagram for explaining a chucking method using an electrostatic chuck.
  • FIG. 7 is a diagram for explaining a change in potential of each part in the checking method of FIG.
  • FIG. 8 is a diagram for explaining a change in potential of each part in another chucking method.
  • FIG. 9 is a diagram for explaining a comparative example of a chucking method using an electrostatic chuck.
  • FIG. 10 is a diagram for explaining a change in potential of each part in the chucking method of FIG.
  • FIG. 11 is a diagram showing the relationship between the voltage applied to the electrostatic chuck and the number of particles.
  • FIG. 1 schematically shows the overall configuration of a plasma processing apparatus (etching apparatus) used in an embodiment of the present invention.
  • reference numeral 1 denotes a cylindrical vacuum chamber which is made of, for example, aluminum and the like and is configured so as to be able to hermetically close the inside thereof, and which constitutes a processing chamber.
  • the vacuum chamber 11 is connected to a ground potential. Inside the vacuum chamber 1, there is provided a mounting table 2 made of a conductive material, for example, aluminum or the like in a block shape and also serving as a lower electrode.
  • the mounting table 2 is supported in a vacuum chamber 11 via an insulating plate 3 made of ceramic or the like.
  • An electrostatic chuck 4 is provided on the mounting surface of the mounting table 2 on which the semiconductor wafer W is mounted.
  • the electrostatic chuck 4 has a configuration in which an electrode 4 a for an electrostatic chuck is interposed in an insulating film 4 b made of an insulating material, and a DC power supply 5 is connected to the electrode 4 a for the electrostatic chuck. Have been.
  • the electrostatic chuck electrode 4a is made of, for example, copper or the like, and the insulating film 4b is made of polyimide or the like.
  • the inside of the mounting table 2 has insulating properties as a heat medium for temperature control.
  • a heat medium flow path 6 for circulating a fluid and a gas flow path 7 for supplying a temperature control gas such as a helium gas to the back surface of the semiconductor wafer W are provided.
  • the mounting table 2 is controlled to a predetermined temperature by circulating an insulating fluid controlled at a predetermined temperature in the heat medium flow path 6, and the space between the mounting table 2 and the back surface of the semiconductor wafer W is controlled.
  • a gas for temperature control is supplied through the gas flow path 7 to promote heat exchange between them, so that the semiconductor wafer W can be accurately and efficiently controlled to a predetermined temperature. I have.
  • a focus ring 8 made of a conductive material or an insulating material is provided on the outer periphery above the mounting table 2, and a power supply for supplying high-frequency power is provided substantially at the center of the mounting table 2.
  • Wire 9 is connected.
  • a high-frequency power supply (RF power supply) 11 is connected to the power supply line 9 via a matching unit 10 so that a high-frequency power of a predetermined frequency is supplied from the high-frequency power supply 11. .
  • an exhaust ring 12 which is formed in a ring shape and has a large number of exhaust holes, and through this exhaust ring 12, an exhaust port 13 is provided.
  • the processing space in the vacuum chamber 11 is evacuated by a vacuum pump or the like of an exhaust system 14 connected to the vacuum chamber.
  • a shower head 15 is provided on the top wall portion of the vacuum chamber 11 above the mounting table 2 so as to face the mounting table 2 in parallel, and this shower head 15 is grounded. I have. Therefore, the shower head 15 and the mounting table 2 function as a pair of electrodes (an upper electrode and a lower electrode).
  • the shower head 15 is provided with a number of gas discharge holes 16 on the lower surface, and has a gas inlet 17 on the upper part. And A gas diffusion space 18 is formed inside the shower head 15.
  • a gas supply pipe 19 is connected to the gas introduction section 17, and a gas supply system 20 is connected to the other end of the gas supply pipe 19.
  • the gas supply system 20 includes a mass flow controller (MFC) 21 for controlling a gas flow rate, a processing gas supply source 22 for supplying, for example, a processing gas for etching, and an Ar gas. It consists of an Ar gas supply source 23 for supplying water.
  • MFC mass flow controller
  • annular magnetic field forming mechanism (ring magnet) 24 is arranged around the outside of the vacuum chamber 11 concentrically with the vacuum chamber 11, and is located between the mounting table 2 and the shower head 15. A magnetic field is formed in the processing space. The whole of the magnetic field forming mechanism 24 is rotatable around the vacuum chamber 11 at a predetermined rotation speed by a rotating mechanism 25.
  • the plasma processing mechanism such as the DC power supply 5, the high-frequency power supply 11, and the gas supply system 20 for performing the plasma processing on the semiconductor wafer W is configured to be controlled by the control unit 40.
  • a gut valve (not shown) provided in the vacuum chamber 11 is opened, and a semiconductor wafer W is transferred by a transfer mechanism (not shown) through a load lock chamber (not shown) arranged adjacent to the gate valve. Is loaded into the vacuum chamber 1 and is mounted on the mounting table 2. Then, after the transfer mechanism is retracted out of the vacuum chamber 11, the gate valve is closed. At this time, the application of the DC voltage (HV) from the DC power supply 5 to the electrostatic chuck electrode 4a of the electrostatic chuck 4 was not performed.
  • HV DC voltage
  • the reason why the weak plasma is applied to the semiconductor wafer W is as follows.
  • the state of the semiconductor wafer W to be processed is not uniform due to the processing state in a previous step (for example, a film forming step such as CVD).
  • a previous step for example, a film forming step such as CVD.
  • electric charges are accumulated inside the semiconductor wafer w. May be. If strong plasma is applied in the state where the electric charge is accumulated inside the semiconductor wafer W, surface arcing or the like is likely to occur, so that the weak plasma is applied before the strong plasma is applied. The purpose of this is to uniformly adjust (initialize) the state and the like of the electric charge accumulated inside the semiconductor wafer W.
  • the electrode 4 a for the electrostatic chuck of the electrostatic chuck 4 is used to facilitate the movement of the electric charge from the inside of the semiconductor wafer W.
  • the semiconductor wafer is adjusted (initialized) by such weak plasma without applying a DC voltage (HV) to the semiconductor wafer.
  • the high-frequency applied power for generating such a weak plasma is about 0.15 W / cm 2 to about 1.0 WZ cm 2 , for example, about 100 to 500 W. Is applied to the semiconductor wafer W, for example, about 5 to 20 seconds.
  • Ar gas is used and plasma of Ar gas is applied. Case is described, but not gas species limited to this,
  • gas species 0 2 gas, CF 4 gas, a gas such as N 2 gas may be used, however, when the selection of the gas species It is necessary to select a plasma gas to be generated to such an extent that an undesired action such as etching is caused on the semiconductor wafer W and on the inner wall of the vacuum chamber 11 and on the semiconductor wafer W, and It is necessary to select one that easily ignites the plasma.
  • the optimum gas type may change depending on the type of processing performed on the semiconductor wafer W to be processed in the previous process. Is preferred.
  • a DC voltage (HV) from the DC power supply 5 is applied to the electrostatic chuck electrode 4a.
  • a predetermined processing gas (etching gas) is supplied from the processing gas supply source 22 into the vacuum chamber 11, and the high frequency power supply 11 supplies the gas to the mounting table 2 as a lower electrode.
  • high-frequency power frequency: 13.56 MHz
  • high power for normal processing such as 0 W
  • strong plasma is generated and normal plasma processing (etching processing) is performed.
  • the horizontal axis represents time
  • the vertical axis represents the voltage value in the case of the electrostatic chuck HV, and the power value in the case of the RF output.
  • the high frequency is applied to the mounting table 2 as the lower electrode.
  • a high-frequency electric field is formed in the processing space between the upper head 15 as the upper electrode and the mounting table 2 as the lower electrode, and a magnetic field forming mechanism 24 is formed.
  • a magnetic field is formed, and etching by plasma is performed in this state.
  • the etching process is stopped by stopping the supply of the high-frequency power from the high-frequency power supply 11.
  • the semiconductor wafer W is placed in a vacuum chamber in a procedure reverse to the procedure described above. One outside Take it out.
  • a weak plasma is applied to the semiconductor wafer W.- After that, when the semiconductor wafer w is subjected to an etching process, the rate at which surface arcing occurs on the semiconductor wafer W is independent of the lot. , Almost zero (less than 1%). On the other hand, when the process is started without applying the weak plasma as described above, the rate at which surface arcing occurs on the semiconductor wafer W may be about 80% depending on the lot. The reason is that the semiconductor wafer W was charged in a process before etching, and such surface arcing is performed when the so-called Low-K film is formed by CVD in the previous process. a, c thus the probability was high particularly generated, before starting the normal process, by the action of weak plasma to the semiconductor wafer W as described above, greatly reduced the rate at which the surface arcing occurs in the semiconductor wafer W I was able to confirm that I could.
  • FIG. 1 a case where a device having a configuration in which high-frequency power is applied only to the mounting table 2 as the lower electrode is described, for example, as shown in FIG.
  • a so-called upper and lower application type plasma processing apparatus configured to apply high-frequency power from the high-frequency power supply 31 via the matching unit 30 to the first head 15 as the upper electrode as well. Can also be applied.
  • the application of low-frequency high-frequency power to the mounting table 2 as the lower electrode is started, and then the low-frequency power is applied to the upper electrode 15 as the upper electrode.
  • the application of the high-frequency power is started, and the application of the high-frequency power to the mounting table 2 as the lower electrode is temporarily stopped here.
  • the application of the high-frequency power to the shower head 15 as the upper electrode is also stopped, and the plasma is once extinguished.
  • a DC voltage (HV) is applied to the electrostatic chuck electrode 4 a of the electrostatic chuck 4, and a normal high-frequency power (high-power high-frequency power) for processing on the mounting table 2 as the lower electrode is applied.
  • the application of normal high-frequency power for processing (high-frequency high-frequency power) to the shower head 15 as the upper electrode is started in this order, and normal processing of the semiconductor wafer W is started.
  • the present invention can be applied to the upper and lower applied plasma processing apparatus.
  • the ionizer may be installed in the chamber or may be installed in another location outside the chamber.
  • an electrostatic chuck is applied in a state in which a weak high-frequency power is applied to the mounting table 2 serving as the lower electrode and a weak plasma is not applied.
  • the application of DC voltage (HV) to the electrostatic chuck electrode 4a has started.
  • the application of the DC voltage (HV) to the chuck electrode 4a is started in a state where the high-frequency power is not applied after the weak high-frequency power is applied and the weak plasma is formed.
  • the application of DC voltage (HV) is started, a lightning-like discharge may occur, damaging the substrate.
  • FIG. 5 in a state where high-frequency power is applied to the mounting table 2 (a state in which weak plasma is generated), a DC voltage to the electrostatic chuck electrode 4 a ( By starting application of HV), the occurrence of discharge can be suppressed.
  • the method of forming a weak plasma using Ar gas before the plasma processing such as etching, and the electric charge for the electrostatic chuck at that time has been described.
  • the electrostatic chuck 4 includes a bipolar type and a monopolar type, and these types include a Coulomb type and a Johnson-Rahbek type, respectively.
  • a monopolar electrostatic chuck 4 of Coulomb type it is preferable that the semiconductor wafer W is suctioned in the following sequence.
  • Figure 6 shows the sequence.
  • the horizontal axis represents time
  • the vertical axis represents the applied high-frequency power value (W) for the dotted line
  • V DC voltage value
  • the high-frequency power applied to the mounting table 2 when generating plasma for the first time is set to a lower high-frequency power (for example, about 500 W) than when processing is performed. Therefore, it is preferable that the temperature of the semiconductor wafer W does not rise. Also, when the semiconductor wafer W is removed from the electrostatic chuck 4, as shown in the figure, after the plasma processing is completed, first, the applied high-frequency power value is reduced to a power value (0 (Not W). After this, the application of DC voltage (HV) to the electrostatic chuck electrode 4a was stopped.
  • the application of high frequency power is stopped to extinguish the plasma.
  • a voltage for example, about 200 V
  • a voltage is applied to a to remove the charge and facilitate removal of the semiconductor wafer W.
  • the application of such a voltage of the opposite polarity is performed as needed. If the semiconductor wafer W can be easily removed from the controversial check 4 without applying the voltage of the opposite polarity, the application of the opposite polarity is performed. No voltage is applied.
  • Figure 4 shows the sequence of the chucking of the semiconductor wafer W by the electrostatic chuck 4 as described above.
  • the potential of the semiconductor wafer W becomes a potential of about 100 V minus the number of negative electrodes determined by the state of the plasma, as shown by 3 in the figure.
  • the DC voltage (HV) is applied to the surface of the semiconductor wafer W to the electrode 4 a for the electrostatic chuck. Since the accompanying high voltage is not applied, it is possible to prevent undesirable abnormal discharge from occurring on the surface of the semiconductor wafer W.
  • the DC voltage is turned OFF after the OFF
  • a large voltage is applied to the semiconductor wafer W as shown in FIG. 10 when the semiconductor wafer W is attracted or desorbed.
  • the surface of the semiconductor wafer W may be damaged, specifically, a chip having a diameter of about several m may be generated.
  • arcing may occur during etching and a product defect may occur.
  • the chipped particles become particles and may adhere to the surface of the semiconductor wafer W.
  • FIG. 11 shows the result of examining the difference in the number of adhered particles due to the difference in the magnitude of the DC applied voltage of the electrostatic chuck for adsorbing the semiconductor wafer W.
  • a CF-based reactant serving as a source of particles is attached to the processing chamber 1 of the plasma processing apparatus (seasoning), and then the semiconductor wafer W is loaded into the processing chamber and placed on the electrostatic chuck.
  • the semiconductor wafer W is placed on the semiconductor wafer W, and the processing gas is circulated for a certain period of time.After that, the semiconductor wafer W is neutralized and unloaded from the processing chamber.
  • the DC voltage of the electrostatic chuck is 0 V, 1.5 kV, 2.0 kV, and 2.5 kV. In each case, This shows the results of an investigation.
  • the pressure, gas used, wafer backside pressure, and temperature conditions when the semiconductor wafer W is placed on the electrostatic chuck and gas is passed are the same as described above. 60 seconds.
  • the static elimination of the semiconductor wafer W is performed by applying a pressure of 26.6 Pa, an applied voltage of 1.5 kV, a voltage application time of 1 second, and a pressure of 53.2 Pa.
  • N 100 sccm
  • time 15 seconds
  • static elimination of the electrostatic chuck was performed at an applied voltage of —2, OkV, and a voltage applied time of 1 second. It is to be noted that such static elimination is performed because the semiconductor wafer W after the process is conveyed may cause extra particles to adhere again if the semiconductor wafer W jumps when the semiconductor wafer W is transferred. Thereby, such a jump of the semiconductor wafer W does not occur.
  • FIG. 1 after the seasoning process, placing the semiconductor wafer W to the processing chamber in one, generates a large number of particles from the reactant deposited in seasoning step performed 0 2 Doraiku cleaning in this state
  • the number of particles adhering to the semiconductor wafer W is calculated in the order of RFON ⁇ HVON at the start of processing, HVOFF ⁇ RFOFF at the end of processing, and HVON ⁇ RFON at the start of processing and RFOFF ⁇ HVOFF at the end of processing. This shows the results of measurements for the case of the sequence described above.
  • the number of attached particles can be significantly reduced.
  • HV is applied (2), and thereafter, the semiconductor wafer W is placed on the mounting table 2 by lowering the wafer supporting pins (3, 4), and the semiconductor wafer w is also attracted.
  • the surface of the semiconductor wafer w does not reach the potential of the applied DC voltage (HV).
  • abnormal discharge that occurs when the electrostatic chuck is attracted by the above-described electrostatic chuck can be prevented by using a bipolar electrostatic chuck even with the same Coulomb-type electrostatic chuck.
  • the present invention is not limited to such an embodiment, and it is needless to say that the present invention can be used for any plasma processing. It is. Further, in the above embodiment, the case where the weak plasma is applied in the vacuum chamber of the etching apparatus for performing the etching process has been described.
  • the body wafer w can be initialized.
  • the plasma processing method and the plasma processing apparatus according to the present invention can be used in a semiconductor manufacturing industry or the like that manufactures semiconductor devices.

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Abstract

Argon gas is supplied into a vacuum chamber (1). Keeping this condition, relatively small high-frequency power such as 300W is supplied to a platform (2) (lower electrode) from a high-frequency power supply (11) in order to produce a weak plasma which acts on a semiconductor wafer (W) so as to adjust the condition of charge built up within it (W). During this adjustment, no DC voltage (HV) is applied to an electrostatic chuck (4) for ease of charge movement. Thereafter a direct current voltage is started to be applied to the electrostatic chuck (4), and then strong high-frequency power such as 2000W for a normal processing is supplied to produce a strong plasma, performing a normal processing. Thus, surface arching that possibly occurs in the processed substrate is avoided, improving the productivity compared to the conventional ones.

Description

明 細 書 プラズマ処理方法及びプラズマ処理装置 技術分野  Description Plasma processing method and plasma processing apparatus
本発明は、 プラズマ処理方法及びプラズマ処理装置に係り、 特に半導 体ウェハや L C D用基板等の被処理基板にプラズマエッチング処理等を 施すプラズマ処理方法及びプラズマ処理装置に関する。 背景技術  The present invention relates to a plasma processing method and a plasma processing apparatus, and more particularly to a plasma processing method and a plasma processing apparatus for performing a plasma etching process or the like on a substrate to be processed such as a semiconductor wafer or an LCD substrate. Background art
従来から、 プラズマによって、 半導体ウェハや L C D用基板等の被処 理基板の処理を行うプラズマ処理方法が多用されている。 例えば、 半導 体装置の製造工程においては、 被処理基板、 例えば半導体ウェハに、 微 細な電気回路を形成するための技術として、 半導体ウェハ上に形成され た薄膜等を、 プラズマを用いてエッチングして除去するプラズマエッチ ング処理が多用されている。  BACKGROUND ART Conventionally, a plasma processing method for processing a substrate to be processed such as a semiconductor wafer or an LCD substrate by using plasma has been frequently used. For example, in a semiconductor device manufacturing process, as a technique for forming minute electric circuits on a substrate to be processed, for example, a semiconductor wafer, a thin film or the like formed on a semiconductor wafer is etched using plasma. Plasma etching is often used to remove.
かかるプラズマェツチング処理を行うェツチング装置では、 例えば、 内部を気密に閉塞可能に構成された処理チャンバ一 (ェツチングチャン バー) 内でプラズマを発生させるようになつている。 そして、 このエツ チングチャンバ一内に設けたサセプタ上に半導体ウェハを載置して、 エッチングを行う。  In an etching apparatus for performing such a plasma etching process, for example, plasma is generated in a processing chamber (etching chamber) configured so that the inside can be hermetically closed. Then, a semiconductor wafer is placed on a susceptor provided in the etching chamber, and etching is performed.
また、 上記プラズマを発生させる手段については、 種々のタイプが知 られている。 そのうち、 上下に対向するように設けられた一対の平行平 板電極に高周波電力を供給してプラズマを発生させるタイプの装置では. 平行平板電極のうちの一方、 例えば、 下部電極がサセプタを兼ねている, そして、 この下部電極上に半導体ウェハを配置し、 平行平板電極間に高 周波電圧を印加してプラズマを発生させ、 エッチングを行う。 Also, various types of means for generating the plasma are known. Among them, a device of the type that supplies high-frequency power to a pair of parallel plate electrodes provided so as to face each other up and down to generate plasma. One of the parallel plate electrodes, for example, the lower electrode also serves as a susceptor And a semiconductor wafer is placed on this lower electrode, A plasma is generated by applying a frequency voltage to perform etching.
しかしながら、 このようなエッチング装置では、 エッチング中に、 半 導体ウェハの表面で、 雷状の異常放電が生じる所謂表面アーキングが生 じることがある。  However, in such an etching apparatus, during etching, so-called surface arcing in which a lightning-like abnormal discharge occurs on the surface of the semiconductor wafer may occur.
上記表面アーキングは、 例えば、 導体層の上に絶縁体層が形成され、 かかる絶縁体層をエッチングするような場合に生じる場合が多い。 例え ば、 シリ コン酸化膜からなる絶縁体層をエッチングして、 下層のメタル 層からなる導体層に通じるコンタク トホールを形成する場合等に、 エツ チングによって膜厚が減少したシリ コン酸化膜を破壊するように生じる 場合が多い。  The surface arcing often occurs, for example, when an insulator layer is formed on a conductor layer and the insulator layer is etched. For example, when the insulator layer made of a silicon oxide film is etched to form a contact hole that leads to a conductor layer made of a lower metal layer, the silicon oxide film whose thickness has been reduced by etching is destroyed. In many cases, it occurs.
そして、 かかる異常放電が生じると、 半導体ウェハ中のシリ コン酸化 膜の多くの部分が破壊されてしまうため、 その半導体ウェハの大部分の 素子が不良となってしまう。 また、 これと と もに、 エッチングチャン バー内に金属汚染が生じ、 そのまま続けてエッチング処理を行うことが できず、 ェツチングチヤンバー内のク リ一ユングが必要となる。 このた め、 生産性が著しく低下してしまう という問題があった。 発明の開示  When such abnormal discharge occurs, many parts of the silicon oxide film in the semiconductor wafer are destroyed, and most of the elements on the semiconductor wafer become defective. At the same time, metal contamination occurs in the etching chamber, so that the etching process cannot be performed as it is, and the cleaning chamber in the etching chamber is required. For this reason, there was a problem that productivity was significantly reduced. Disclosure of the invention
そこで、 本発明の目的は、 被処理基板に生じる表面アーキングの発生 を防止して、 従来に較べて生産性の向上を図ることのできるプラズマ処 理方法及びプラズマ処理装置を提供しよ う とするものである。  Therefore, an object of the present invention is to provide a plasma processing method and a plasma processing apparatus which can prevent the occurrence of surface arcing on a substrate to be processed and can improve the productivity as compared with the related art. Things.
本発明のプラズマ処理方法は、 被処理基板にプラズマを作用させてプ ラズマ処理を行うにあたり、 前記プラズマ処理を行う前に、 当該プラズ マ処理に使用するプラズマより も弱いプラズマを前記被処理基板に作用 させて、 当該被処理基板の電荷の状態を一定の状態と し、 この後、 前記 プラズマ処理を行うことを特徴とする。 また、 本発明のプラズマ処理方法は、 上記プラズマ処理方法において、 前記弱いプラズマを前記被処理基板に所定時間作用させ、 この後、 前記 被処理基板を吸着保持するための静電チヤックに直流電圧を印加するこ とを特徴とする。 In the plasma processing method of the present invention, when performing plasma processing by applying plasma to a substrate to be processed, a plasma weaker than plasma used for the plasma processing is applied to the substrate before performing the plasma processing. And the state of electric charge of the substrate to be processed is kept constant, and thereafter, the plasma processing is performed. Further, in the plasma processing method of the present invention, in the plasma processing method, the weak plasma is applied to the substrate to be processed for a predetermined time, and thereafter, a DC voltage is applied to an electrostatic chuck for sucking and holding the substrate to be processed. It is characterized by applying.
また、 本発明のプラズマ処理方法は、 上記プラズマ処理方法において、 前記弱いプラズマを消す前に、 前記静電チャックに対する直流電圧の印 加を開始することを特徴とする。  Further, the plasma processing method of the present invention is characterized in that in the above-described plasma processing method, before applying the weak plasma, application of a DC voltage to the electrostatic chuck is started.
また、 本発明のプラズマ処理方法は、 上記プラズマ処理方法において、 前記弱いプラズマが、 A rガス、 又は〇2 ガス、 又は C F 4 ガス、 又は N 2 ガスによって形成されたプラズマであることを特徴とする。 Further, in the plasma processing method of the present invention, in the above-described plasma processing method, the weak plasma is a plasma formed by an Ar gas, or a 〇2 gas, or a CF 4 gas, or an N 2 gas. I do.
また、 本発明のプラズマ処理方法は、 上記プラズマ処理方法において、 前記弱いプラズマが、 0 . 1 5〜 1 . 0 WZ c m 2 の高周波電力によつ て形成されることを特徴とする。  Further, the plasma processing method of the present invention is characterized in that, in the above-mentioned plasma processing method, the weak plasma is formed by a high frequency power of 0.15 to 1.0 WZ cm 2.
また、 本発明のプラズマ処理方法は、 上記プラズマ処理方法において、 前記弱いプラズマを、 5〜 2 0秒の間前記被処理基板に作用させること を特徴とするプラズマ処理方法。  The plasma processing method according to the present invention is the plasma processing method described above, wherein the weak plasma is applied to the substrate to be processed for 5 to 20 seconds.
また、 本発明のプラズマ処理方法は、 上記プラズマ処理方法において, 前記プラズマ処理の開始時に、 プラズマを発生させるための高周波電力 の印加を開始した後、 前記静電チヤックに対する直流電圧の印加を開始 し、 前記プラズマ処理の終了時に、 前記静電チャックに対する直流電圧 の印加を停止した後、 前記高周波電力の印加を停止することを特徴とす る。  Further, in the plasma processing method of the present invention, in the above-described plasma processing method, at the start of the plasma processing, after the application of high-frequency power for generating plasma is started, the application of a DC voltage to the electrostatic chuck is started. The application of the high-frequency power is stopped after the application of the DC voltage to the electrostatic chuck is stopped at the end of the plasma processing.
また、 本発明のプラズマ処理方法は、 上記プラズマ処理方法において- 前記被処理基板を前記静電チヤックの上方に導体で接地された支持棒に より支持した状態で、 前記静電チャックに対する直流電圧の印加を開始 し、 この後、 前記被処理基板を下降させて前記静電チャックの上に載置 することを特徴とする。 Further, in the plasma processing method of the present invention, in the above-mentioned plasma processing method, in a state where the substrate to be processed is supported by a support bar grounded by a conductor above the electrostatic chuck, a DC voltage of the electrostatic chuck is The application is started, and then the substrate is lowered and placed on the electrostatic chuck. It is characterized by doing.
また、 本発明のプラズマ処理方法は、 上記プラズマ処理方法において- 前記プラズマ処理がエッチング処理であり、 当該ェツチング処理を行う 処理チャンバ一内で、 前記被処理基板に前記弱いプラズマを作用させる ことを特徴とする。  Further, the plasma processing method of the present invention is characterized in that in the above-mentioned plasma processing method, the plasma processing is an etching processing, and the weak plasma is applied to the substrate to be processed in a processing chamber for performing the etching processing. And
また、 本発明のプラズマ処理装置は、 被処理基板にプラズマ処理を施 すプラズマ処理機構を具備したプラズマ処理装置であって、 前記プラズ マ処理機構を制御し、 上記プラズマ処理方法を行う制御部を具備したこ とを特徴とする。 図面の簡単な説明  Further, the plasma processing apparatus of the present invention is a plasma processing apparatus including a plasma processing mechanism for performing a plasma processing on a substrate to be processed, wherein the control unit controls the plasma processing mechanism and performs the plasma processing method. It is characterized by having. BRIEF DESCRIPTION OF THE FIGURES
図 1は、 本発明の一実施形態に使用する装置の概略構成を模式的に示 す図。  FIG. 1 is a diagram schematically showing a schematic configuration of an apparatus used in an embodiment of the present invention.
図 2は、 本発明の一実施形態に係るプラズマ処理方法を説明するため の図。  FIG. 2 is a view for explaining a plasma processing method according to one embodiment of the present invention.
図 3は、 本発明の他の実施形態に使用する装置の概略構成を模式的に 示す図。  FIG. 3 is a diagram schematically showing a schematic configuration of an apparatus used in another embodiment of the present invention.
図 4は、 本発明の他の実施形態に係るプラズマ処理方法を説明するた めの図。  FIG. 4 is a view for explaining a plasma processing method according to another embodiment of the present invention.
図 5は、 図 2に示す実施形態の変形例に係るプラズマ処理方法を説明 するための図。  FIG. 5 is a view for explaining a plasma processing method according to a modification of the embodiment shown in FIG.
図 6は、 静電チヤックによるチヤック方法を説明するための図。  FIG. 6 is a diagram for explaining a chucking method using an electrostatic chuck.
図 7は、 図 6のチヤック方法における各部の電位の変化を説明するた めの図。  FIG. 7 is a diagram for explaining a change in potential of each part in the checking method of FIG.
図 8は、 他のチャック方法における各部の電位の変化を説明するため の図。 図 9は、 静電チヤックによるチャック方法の比較例を説明するための 図。 FIG. 8 is a diagram for explaining a change in potential of each part in another chucking method. FIG. 9 is a diagram for explaining a comparative example of a chucking method using an electrostatic chuck.
図 1 0は、 図 9のチャック方法における各部の電位の変化 ¥説明する ための図。  FIG. 10 is a diagram for explaining a change in potential of each part in the chucking method of FIG.
図 1 1は、 静電チャックの印加電圧とパーティクルの数との関係を示 す図。  FIG. 11 is a diagram showing the relationship between the voltage applied to the electrostatic chuck and the number of particles.
図 1 2は、 シーケンスの相違によるパーティクルの数の相違を示す図 c 発明を実施するための最良の形態 1 2, the best mode for carrying out the Figure c invention showing the difference in the number of particles due to the difference of the sequence
以下、 本発明の詳細を、 図面を参照して実施形態について説明する。 図 1は、 本発明の実施の形態に使用するプラズマ処理装置 (エツチン グ装置) 全体の概略構成を模式的に示すものである。 同図において、 符 号 1は、 材質が例えばアルミユウム等からなり、 内部を気密に閉塞可能 に構成され、 処理チャンバ一を構成する円筒状の真空チャンバ一を示し ている。  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 schematically shows the overall configuration of a plasma processing apparatus (etching apparatus) used in an embodiment of the present invention. In the figure, reference numeral 1 denotes a cylindrical vacuum chamber which is made of, for example, aluminum and the like and is configured so as to be able to hermetically close the inside thereof, and which constitutes a processing chamber.
上記真空チャンバ一 1は、 接地電位に接続されている。 真空チャン パー 1の内部には、 導電性材料、 例えばアルミニウム等からブロック状 に構成され、 下部電極を兼ねた載置台 2が設けられている。  The vacuum chamber 11 is connected to a ground potential. Inside the vacuum chamber 1, there is provided a mounting table 2 made of a conductive material, for example, aluminum or the like in a block shape and also serving as a lower electrode.
この載置台 2は、 セラミックなどの絶縁板 3を介して真空チャンバ一 1内に支持されている。 載置台 2の半導体ウェハ W載置面には、 静電 チャック 4が設けられている。 この静電チャック 4は、 静電チャック用 電極 4 aを、 絶縁性材料からなる絶縁膜 4 b中に介在させた構成とされ ており、 静電チャック用電極 4 aには直流電源 5が接続されている。 静 電チャック用電極 4 aは、 例えば銅等から構成されており、 絶縁膜 4 b はポリイミ ド等から構成されている。  The mounting table 2 is supported in a vacuum chamber 11 via an insulating plate 3 made of ceramic or the like. An electrostatic chuck 4 is provided on the mounting surface of the mounting table 2 on which the semiconductor wafer W is mounted. The electrostatic chuck 4 has a configuration in which an electrode 4 a for an electrostatic chuck is interposed in an insulating film 4 b made of an insulating material, and a DC power supply 5 is connected to the electrode 4 a for the electrostatic chuck. Have been. The electrostatic chuck electrode 4a is made of, for example, copper or the like, and the insulating film 4b is made of polyimide or the like.
また、 載置台 2の内部には、 温度制御のための熱媒体としての絶縁性 流体を循環させるための熱媒体流路 6 と、 ヘリゥムガス等の温度制御用 のガスを半導体ウェハ Wの裏面に供給するためのガス流路 7が設けられ ている。 In addition, the inside of the mounting table 2 has insulating properties as a heat medium for temperature control. A heat medium flow path 6 for circulating a fluid and a gas flow path 7 for supplying a temperature control gas such as a helium gas to the back surface of the semiconductor wafer W are provided.
そして、 熱媒体流路 6内に所定温度に制御された絶縁性流体を循環さ せることによって、 載置台 2を所定温度に制御し、 かつ、 この載置台 2 と半導体ウェハ Wの裏面との間にガス流路 7を介して温度制御用のガス を供給してこれらの間の熱交換を促進し、 半導体ウェハ Wを精度良くか つ効率的に所定温度に制御することができるようになつている。  Then, the mounting table 2 is controlled to a predetermined temperature by circulating an insulating fluid controlled at a predetermined temperature in the heat medium flow path 6, and the space between the mounting table 2 and the back surface of the semiconductor wafer W is controlled. A gas for temperature control is supplied through the gas flow path 7 to promote heat exchange between them, so that the semiconductor wafer W can be accurately and efficiently controlled to a predetermined temperature. I have.
また、 載置台 2の上方の外周には導電性材料または絶縁性材料で形成 されたフォーカスリング 8が設けられており、 さらに、 載置台 2のほぼ 中央には、 高周波電力を供給するための給電線 9が接続されている。 こ の給電線 9には整合器 1 0を介して、 高周波電源 (R F電源) 1 1が接 続され、 高周波電源 1 1からは、 所定の周波数の高周波電力が供給され るようになつている。  Further, a focus ring 8 made of a conductive material or an insulating material is provided on the outer periphery above the mounting table 2, and a power supply for supplying high-frequency power is provided substantially at the center of the mounting table 2. Wire 9 is connected. A high-frequency power supply (RF power supply) 11 is connected to the power supply line 9 via a matching unit 10 so that a high-frequency power of a predetermined frequency is supplied from the high-frequency power supply 11. .
また、 上述したフォーカスリング 8の外側には、 環状に構成され、 多 数の排気孔が形成された排気リング 1 2が設けられており、 この排気リ ング 1 2を介して、 排気ポート 1 3に接続された排気系 1 4の真空ボン プ等により、 真空チャンバ一 1内の処理空間の真空排気が行われるよう 構成されている。  Outside the focus ring 8, there is provided an exhaust ring 12, which is formed in a ring shape and has a large number of exhaust holes, and through this exhaust ring 12, an exhaust port 13 is provided. The processing space in the vacuum chamber 11 is evacuated by a vacuum pump or the like of an exhaust system 14 connected to the vacuum chamber.
一方、 載置台 2の上方の真空チャンバ一 1の天壁部分には、 シャワー ヘッ ド 1 5が、 載置台 2と平行に対向する如く設けられており、 この シャワーヘッ ド 1 5は接地されている。 したがって、 これらのシャワー ヘッ ド 1 5 と載置台 2は、 一対の電極 (上部電極と下部電極) として機 能するようになつている。  On the other hand, a shower head 15 is provided on the top wall portion of the vacuum chamber 11 above the mounting table 2 so as to face the mounting table 2 in parallel, and this shower head 15 is grounded. I have. Therefore, the shower head 15 and the mounting table 2 function as a pair of electrodes (an upper electrode and a lower electrode).
上記シャワーヘッド 1 5は、 その下面に多数のガス吐出孔 1 6が設け られており、 且つその上部にガス導入部 1 7を有している。 そして、 シャワーへッ ド 1 5の内部にはガス拡散用空隙 1 8が形成されている。 ガス導入部 1 7にはガス供給配管 1 9が接続されており、 このガス供給 配管 1 9の他端には、 ガス供給系 2 0が接続されている。 このガス供給 系 2 0は、 ガス流量を制御するためのマスフローコン トローラ (M F C ) 2 1 と、 例えばエッチング用の処理ガス等を供給するための処理ガ ス供給源 2 2、 及び、 A rガスを供給するための A rガス供給源 2 3等 から構成されている。 The shower head 15 is provided with a number of gas discharge holes 16 on the lower surface, and has a gas inlet 17 on the upper part. And A gas diffusion space 18 is formed inside the shower head 15. A gas supply pipe 19 is connected to the gas introduction section 17, and a gas supply system 20 is connected to the other end of the gas supply pipe 19. The gas supply system 20 includes a mass flow controller (MFC) 21 for controlling a gas flow rate, a processing gas supply source 22 for supplying, for example, a processing gas for etching, and an Ar gas. It consists of an Ar gas supply source 23 for supplying water.
一方、 真空チャンバ一 1の外側周囲には、 真空チャンバ一 1 と同心状 に、 環状の磁場形成機構 (リング磁石) 2 4が配置されており、 载置台 2とシャワーヘッ ド 1 5との間の処理空間に磁場を形成するようになつ ている。 この磁場形成機構 2 4は、 回転機構 2 5によって、 その全体が、 真空チャンバ一 1の回りを所定の回転速度で回転可能とされている。  On the other hand, an annular magnetic field forming mechanism (ring magnet) 24 is arranged around the outside of the vacuum chamber 11 concentrically with the vacuum chamber 11, and is located between the mounting table 2 and the shower head 15. A magnetic field is formed in the processing space. The whole of the magnetic field forming mechanism 24 is rotatable around the vacuum chamber 11 at a predetermined rotation speed by a rotating mechanism 25.
また、 半導体ウェハ Wにプラズマ処理を施すための上記直流電源 5、 高周波電源 1 1、 ガス供給系 2 0等のプラズマ処理機構は、 制御部 4 0 によって制御されるよう構成されている。  The plasma processing mechanism such as the DC power supply 5, the high-frequency power supply 11, and the gas supply system 20 for performing the plasma processing on the semiconductor wafer W is configured to be controlled by the control unit 40.
次に、 上記のように構成されたエッチング装置によるエッチング処理 の手順について説明する。  Next, the procedure of the etching process by the etching apparatus configured as described above will be described.
(第 1実施例)  (First embodiment)
まず、 真空チャンバ一 1に設けられた図示しないグートバルブを開放 し、 このゲートバルブに隣接して配置されたロードロック室 (図示せ ず) を介して、 搬送機構 (図示せず) により半導体ウェハ Wを真空チヤ ンパー 1内に搬入し、 載置台 2上に載置する。 そして、 搬送機構を真空 チャンバ一 1外へ退避させた後、 ゲートバルブを閉じる。 なお、 この時 点では、 静電チヤック 4の静電チヤック用電極 4 aへの直流電源 5から の直流電圧 (H V ) の印加は、 行っていない。  First, a gut valve (not shown) provided in the vacuum chamber 11 is opened, and a semiconductor wafer W is transferred by a transfer mechanism (not shown) through a load lock chamber (not shown) arranged adjacent to the gate valve. Is loaded into the vacuum chamber 1 and is mounted on the mounting table 2. Then, after the transfer mechanism is retracted out of the vacuum chamber 11, the gate valve is closed. At this time, the application of the DC voltage (HV) from the DC power supply 5 to the electrostatic chuck electrode 4a of the electrostatic chuck 4 was not performed.
この後、 排気系 1 4の真空ポンプにより排気ポート 1 3を通じて真空 チャンバ一 1内を所定の真空度に排気しつつ、 まず、 A rガス供給源 2 3から、 真空チャンバ一 1内に A rガスを供給する。 そして、 この状態 で、 図 2に示すように、 まず高周波電源 1 1から下部電極としての載置 台 2に、 例えば、 3 0 O W等の比較的パワーの低い高周波電力 (周波数 例えば 1 3 . 5 6 M H z ) を供給して、 弱いプラズマを発生させ、 この 弱いプラズマを半導体ウェハ Wに作用させる。 Thereafter, vacuum is exhausted through the exhaust port 13 by the vacuum pump of the exhaust system 14. First, Ar gas is supplied from the Ar gas supply source 23 into the vacuum chamber 11 while evacuating the chamber 11 to a predetermined degree of vacuum. Then, in this state, as shown in FIG. 2, first, a high-frequency power having a relatively low power such as 30 OW (frequency of 13.5 6 MHz) to generate a weak plasma, which acts on the semiconductor wafer W.
このように、 弱いプラズマを半導体ウェハ Wに作用させるのは、 以下 のような理由による。  The reason why the weak plasma is applied to the semiconductor wafer W is as follows.
すなわち、 処理を行う半導体ウェハ Wは、 前工程 (例えば C V D等の 成膜工程) における処理の状態等によって、 その状態が一様でなく、 例 えば、 半導体ウェハ wの内部に電荷が蓄積されている場合がある。 そし て、 このように半導体ウェハ Wの内部に電荷が蓄積された状態で、 強い プラズマを作用させると、 表面アーキング等を生じさせる可能性が高い ため、 かかる強いプラズマを作用させる前に、 弱いプラズマを作用させ て、 半導体ウェハ Wの内部に蓄積された電荷の状態等を一様に調整する (初期化する) ためである。  That is, the state of the semiconductor wafer W to be processed is not uniform due to the processing state in a previous step (for example, a film forming step such as CVD). For example, electric charges are accumulated inside the semiconductor wafer w. May be. If strong plasma is applied in the state where the electric charge is accumulated inside the semiconductor wafer W, surface arcing or the like is likely to occur, so that the weak plasma is applied before the strong plasma is applied. The purpose of this is to uniformly adjust (initialize) the state and the like of the electric charge accumulated inside the semiconductor wafer W.
そして、 このような半導体ウェハ Wの内部に蓄積された電荷の状態を 調整するに当たり、 半導体ウェハ Wの内部から電荷が移動し易くするた めに、 静電チャック 4の静電チャック用電極 4 aへの直流電圧 (H V ) の印加を行わない状態で、 かかる弱いプラズマにより半導体ウェハの調 整 (初期化) を行う。  In adjusting the state of the electric charge accumulated inside the semiconductor wafer W, the electrode 4 a for the electrostatic chuck of the electrostatic chuck 4 is used to facilitate the movement of the electric charge from the inside of the semiconductor wafer W. The semiconductor wafer is adjusted (initialized) by such weak plasma without applying a DC voltage (HV) to the semiconductor wafer.
なお、 このよ うな弱いプラズマを発生させるための高周波印加電力は. 0 . 1 5 W/ c m2 〜 1 . 0 WZ c m2 程度、 例えば、 1 0 0〜 5 0 0 W程度であり、 弱いプラズマを半導体ウェハ Wに作用させる時間は、 例 えば、 5〜2 0秒程度である。 The high-frequency applied power for generating such a weak plasma is about 0.15 W / cm 2 to about 1.0 WZ cm 2 , for example, about 100 to 500 W. Is applied to the semiconductor wafer W, for example, about 5 to 20 seconds.
また、 上記では、 A rガスを用い、 A rガスのプラズマを作用させる 場合について説明しているが、 ガス種はこれに限るものではなく、 例え ば、 02 ガス、 C F 4 ガス、 N 2 ガス等のガスも使用することができる 但し、 このガス種の選択に当たっては、 発生させるガスのプラズマが、 半導体ウェハ Wに対して、 及ぴ、 真空チャンバ一 1 の内壁に対して、 ェツチング等の不所望な作用を起こす程度の少ないものを選択する必要 があり、 かつ、 プラズマが着火し易いものを選択する必要がある。 さら に、 処理を行う半導体ウェハ Wが、 前工程でどのような処理を施された ものであるかによつても、 最適なガス種が変わる場合があり、 これらを 考慮して適宜選択することが好ましい。 In the above description, Ar gas is used and plasma of Ar gas is applied. Case is described, but not gas species limited to this, For example, 0 2 gas, CF 4 gas, a gas such as N 2 gas may be used, however, when the selection of the gas species It is necessary to select a plasma gas to be generated to such an extent that an undesired action such as etching is caused on the semiconductor wafer W and on the inner wall of the vacuum chamber 11 and on the semiconductor wafer W, and It is necessary to select one that easily ignites the plasma. Furthermore, the optimum gas type may change depending on the type of processing performed on the semiconductor wafer W to be processed in the previous process. Is preferred.
そして、 上記のようにして半導体ウェハ Wに弱いプラズマを作用させ た後、 図 2に示すように、 静電チヤック用電極 4 aへの直流電源 5から の直流電圧 (H V ) の印加を行う。 この後、 処理ガス供給源 2 2から真 空チャンバ一 1内に所定の処理ガス (エッチングガス) を供給し、 高周 波電源 1 1から下部電極としての載置台 2に、 例えば、 2 0 0 0 W等の 通常の処理用のパワーの高い高周波電力 (周波数例えば 1 3 . 5 6 M H z ) を供給して、 強いプラズマを発生させ、 通常のプラズマ処理 (エツ チング処理) を行う。 なお、 図 2において、 横軸は時間を表し、 縦軸は 静電チヤック H Vの場合には電圧値、 R F出力の場合には電力値を表す c この時、 下部電極である载置台 2に高周波電力が印加されることによ り、 上部電極であるシャヮ一へッ ド 1 5 と下部電極である載置台 2との 間の処理空間には高周波電界が形成されるとともに、 磁場形成機構 2 4 による磁場が形成され、 この状態でプラズマによるエッチングが行われ る。 Then, after the weak plasma is applied to the semiconductor wafer W as described above, as shown in FIG. 2, a DC voltage (HV) from the DC power supply 5 is applied to the electrostatic chuck electrode 4a. Thereafter, a predetermined processing gas (etching gas) is supplied from the processing gas supply source 22 into the vacuum chamber 11, and the high frequency power supply 11 supplies the gas to the mounting table 2 as a lower electrode. By supplying high-frequency power (frequency: 13.56 MHz) with high power for normal processing such as 0 W, strong plasma is generated and normal plasma processing (etching processing) is performed. In FIG. 2, the horizontal axis represents time, and the vertical axis represents the voltage value in the case of the electrostatic chuck HV, and the power value in the case of the RF output. C At this time, the high frequency is applied to the mounting table 2 as the lower electrode. By the application of power, a high-frequency electric field is formed in the processing space between the upper head 15 as the upper electrode and the mounting table 2 as the lower electrode, and a magnetic field forming mechanism 24 is formed. Thus, a magnetic field is formed, and etching by plasma is performed in this state.
そして、 所定のエッチング処理が実行されると、 高周波電源 1 1から の高周波電力の供給を停止することによって、 エッチング処理を停止し. 上述した手順とは逆の手順で、 半導体ウェハ Wを真空チャンバ一 1外に 搬出する。 Then, when the predetermined etching process is performed, the etching process is stopped by stopping the supply of the high-frequency power from the high-frequency power supply 11. The semiconductor wafer W is placed in a vacuum chamber in a procedure reverse to the procedure described above. One outside Take it out.
上記のようにして、 まず、 半導体ウェハ Wに弱いプラズマを作用させ- この後、 半導体ウェハ wのエッチング処理を行ったところ、 半導体ゥェ ハ Wに表面アーキングが生じる割合を、 ロッ トによらず、 略ゼロ ( 1 % 以下) とすることができた。 一方、 上記のような弱いプラズマを作用さ せずに処理を開始した場合は、 半導体ウェハ Wに表面アーキングが生じ る割合がロッ トによっては、 8 0 %程度となる場合があった。 エツチン グより前の工程において、 半導体ウェハ Wが帯電してしまったことが原 因であり、 このような表面アーキングは、 前工程が、 C V Dによって所 謂 L o w— K膜を形成する工程の場合に、 特に発生する確率が高かった c したがって、 通常の処理を開始する前に、 上記のように半導体ウェハ Wに弱いプラズマを作用させることによって、 半導体ウェハ Wに表面 アーキングが生じる割合を大幅に低下できることが確認できた。 As described above, first, a weak plasma is applied to the semiconductor wafer W.- After that, when the semiconductor wafer w is subjected to an etching process, the rate at which surface arcing occurs on the semiconductor wafer W is independent of the lot. , Almost zero (less than 1%). On the other hand, when the process is started without applying the weak plasma as described above, the rate at which surface arcing occurs on the semiconductor wafer W may be about 80% depending on the lot. The reason is that the semiconductor wafer W was charged in a process before etching, and such surface arcing is performed when the so-called Low-K film is formed by CVD in the previous process. a, c thus the probability was high particularly generated, before starting the normal process, by the action of weak plasma to the semiconductor wafer W as described above, greatly reduced the rate at which the surface arcing occurs in the semiconductor wafer W I was able to confirm that I could.
ところで、 上記の実施形態では、 図 1に示すように、 下部電極である 載置台 2にのみ高周波電力が印加される構成の装置を使用した場合につ いて説明したが、 例えば、 図 3に示すよ うに、 上部電極としてのシャ ヮ一へッ ド 1 5にも、 整合器 3 0を介して高周波電源 3 1から高周波電 力を印加するように構成された所謂上下部印加型のプラズマ処理装置に ついても、 適用することができる。  By the way, in the above embodiment, as shown in FIG. 1, a case where a device having a configuration in which high-frequency power is applied only to the mounting table 2 as the lower electrode is described, for example, as shown in FIG. Thus, a so-called upper and lower application type plasma processing apparatus configured to apply high-frequency power from the high-frequency power supply 31 via the matching unit 30 to the first head 15 as the upper electrode as well. Can also be applied.
この場合、 例えば、 図 4に示すように、 まず、 下部電極である載置台 2に、 低いパワーの高周波電力の印加を開始し、 その後に上部電極であ るシャヮ一へッ ド 1 5に低いパワーの高周波電力の印加を開始し、 ここ で一旦下部電極である載置台 2に対する高周波電力の印加を停止する。 そして、 この状態で所定期間半導体ウェハ Wに弱いプラズマを作用させ た後、 上部電極であるシャワーヘッ ド 1 5に対する高周波電力の印加も 停止して、 一旦プラズマを消す。 しかる後、 静電チャック 4の静電チヤック用電極 4 aへの直流電圧 ( H V ) の印加、 下部電極である載置台 2に対する処理用の通常の高周 波電力 (高パワーの高周波電力) の印加、 上部電極であるシャワーへッ ド 1 5に対する処理用の通常の高周波電力 (高パワーの高周波電力) の 印加を、 この順で開始し、 半導体ウェハ Wの通常の処理を開始する。 In this case, for example, as shown in FIG. 4, first, the application of low-frequency high-frequency power to the mounting table 2 as the lower electrode is started, and then the low-frequency power is applied to the upper electrode 15 as the upper electrode. The application of the high-frequency power is started, and the application of the high-frequency power to the mounting table 2 as the lower electrode is temporarily stopped here. Then, in this state, after the weak plasma is applied to the semiconductor wafer W for a predetermined period, the application of the high-frequency power to the shower head 15 as the upper electrode is also stopped, and the plasma is once extinguished. Thereafter, a DC voltage (HV) is applied to the electrostatic chuck electrode 4 a of the electrostatic chuck 4, and a normal high-frequency power (high-power high-frequency power) for processing on the mounting table 2 as the lower electrode is applied. The application of normal high-frequency power for processing (high-frequency high-frequency power) to the shower head 15 as the upper electrode is started in this order, and normal processing of the semiconductor wafer W is started.
このようにして、 上下部印加型のプラズマ処理装置についても、 本発 明は適用することができる。  In this way, the present invention can be applied to the upper and lower applied plasma processing apparatus.
なお、 上記のように弱いプラズマを作用させるのに加えて、 または、 単独で、 処理を開始する前に、 半導体ウェハ Wに例えば、 ィオナイザ一 を作用させて、 その内部の電荷を低減させることも好ましい。 このよう なィオナイザ一の作用によって、 表面アーキングの発生を抑制すること もできる。 このィオナイザ一は、 チャンバ一内に設置してもよく、 ある いはチャンバ一外の別の場所に設置してもよい。  In addition, in addition to applying weak plasma as described above, or by itself, it is also possible to reduce the charge inside the semiconductor wafer W by, for example, applying an ionizer to the semiconductor wafer W before starting the processing. preferable. By such an operation of the ionizer, the occurrence of surface arcing can be suppressed. The ionizer may be installed in the chamber or may be installed in another location outside the chamber.
ところで、 図 2に示したプラズマ処理方法では、 下部電極である載置 台 2に弱い高周波電力を印加して弱いプラズマをたてた後の高周波電力 が印加されていない状態で、 静電チヤック 4の静電チヤック用電極 4 a への直流電圧 (H V ) の印加を開始している。 このように、 弱い高周波 電力を印加して弱いプラズマをたてた後の高周波電力が印加されていな い状態で、 チャック用電極 4 aへの直流電圧 (H V ) の印加を開始する と、 この直流電圧 (H V ) の印加を開始した際に、 雷状の放電を発生さ せ基板に損傷を与える可能性がある。 このような場合は、 図 5に示すよ うに、 載置台 2に高周波電力が印加されている状態 (弱いプラズマが生 起されている状態) で、 静電チャック用電極 4 aへの直流電圧 (H V ) の印加を開始すれば、 放電の発生を、 抑制することができる。  By the way, in the plasma processing method shown in FIG. 2, an electrostatic chuck is applied in a state in which a weak high-frequency power is applied to the mounting table 2 serving as the lower electrode and a weak plasma is not applied. The application of DC voltage (HV) to the electrostatic chuck electrode 4a has started. As described above, when the application of the DC voltage (HV) to the chuck electrode 4a is started in a state where the high-frequency power is not applied after the weak high-frequency power is applied and the weak plasma is formed, When the application of DC voltage (HV) is started, a lightning-like discharge may occur, damaging the substrate. In such a case, as shown in FIG. 5, in a state where high-frequency power is applied to the mounting table 2 (a state in which weak plasma is generated), a DC voltage to the electrostatic chuck electrode 4 a ( By starting application of HV), the occurrence of discharge can be suppressed.
以上、 第 1実施例において、 エッチング等のプラズマ処理前に A rガ スを用いて弱いプラズマをたてる方法、 及びその際の静電チヤック用電 極 4 aへの直流電圧印加のタイミングについて説明した。 As described above, in the first embodiment, the method of forming a weak plasma using Ar gas before the plasma processing such as etching, and the electric charge for the electrostatic chuck at that time. The timing of applying the DC voltage to the pole 4a has been described.
(第 2実施例)  (Second embodiment)
次にエッチング処理等のプラズマ処理を行う際の高周波電力印加のタ ィミング及び静電チヤック用電極 4 aへの直流電圧印加のタイミングと の関係について、 好適な例を説明する。  Next, a preferred example of the relationship between the timing of the application of high-frequency power and the timing of the application of a DC voltage to the electrostatic chuck electrode 4a when performing a plasma process such as an etching process will be described.
なお、 上記の静電チャック 4には、 双極型と単極型があり、 また、 こ れらのタイプに夫々クーロン型とジョンソンラ一ベック型とがある。 こ のうち、 単極型でクーロン型の静電チャック 4を使用した場合、 次のよ うなシーケンスで半導体ウェハ Wの吸着を行うことが好ましい。 図 6に そのシーケンスを表す。 横軸は時間、 縦軸は点線については印加高周波 電力値 (W) 、 実線については印加直流電圧値 (V ) を表している。 すなわち、 半導体ウェハ Wを載置台 2 (静電チャック 4 ) 上に載置し た後、 真空チャンバ一 1内にガスの導入を開始する。 そして、 この後、 図 6に点線で示すように、 まず、 載置台 2に高周波電力の印加を開始し てプラズマを発生させ、 この後、 同図に実線で示すように、 静電チヤッ ク用電極 4 aへの直流電圧 (H V ) の印加を行う。  The electrostatic chuck 4 includes a bipolar type and a monopolar type, and these types include a Coulomb type and a Johnson-Rahbek type, respectively. Among them, when a monopolar electrostatic chuck 4 of Coulomb type is used, it is preferable that the semiconductor wafer W is suctioned in the following sequence. Figure 6 shows the sequence. The horizontal axis represents time, the vertical axis represents the applied high-frequency power value (W) for the dotted line, and the applied DC voltage value (V) for the solid line. That is, after the semiconductor wafer W is mounted on the mounting table 2 (electrostatic chuck 4), introduction of gas into the vacuum chamber 11 is started. Then, as shown by a dotted line in FIG. 6, first, application of high-frequency power is started to the mounting table 2 to generate plasma, and thereafter, as shown by a solid line in FIG. Apply DC voltage (HV) to electrode 4a.
なお、 静電チャック用電極 4 aへの直流電圧 (H V ) の印加開始前は. 半導体ウェハ Wが静電チヤック 4に吸着されていないため、 その温度制 御が充分に行われてはいない。 このため、 最初にプラズマを発生させる 際に載置台 2に印加する高周波電力は、 処理を行う時に比べて低いパ ヮ一の高周波電力 (例えば 5 0 0 W程度) とし、 プラズマの作用によつ て、 半導体ウェハ Wの温度が上昇しないようにすることが好ましい。 そして、 半導体ウェハ Wを静電チャック 4から取り外す際も、 同図に 示すように、 プラズマ処理が終了した後、 まず、 印加高周波電力値を、 処理を行う時に比べて低いパワーの電力値 (0 Wではない) に下げる。 この後、 静電チャック用電極 4 aへの直流電圧 (H V ) の印加を停止し. しかる後、 高周波電力の印加を停止してプラズマを消す。 なお、 静電 チャック用電極 4 aへの直流電圧 (HV) の印加を停止する際に、 一旦 吸着時とは逆極性の電圧 (例えば一 2 0 0 0 V程度) を静電チャック用 電極 4 aへ印加して、 電荷を除去し、 半導体ウェハ Wを外し易くする。 このような逆極性の電圧の印加は、 必要に応じて行われ、 かかる逆極性 の電圧の印加を行わなく とも半導体ウェハ Wを諍電チヤック 4から簡単 に取り外すことができる場合は、 逆極性の電圧の印加は行わない。 Before the start of the application of the DC voltage (HV) to the electrostatic chuck electrode 4a. Since the semiconductor wafer W is not attracted to the electrostatic chuck 4, its temperature control is not sufficiently performed. For this reason, the high-frequency power applied to the mounting table 2 when generating plasma for the first time is set to a lower high-frequency power (for example, about 500 W) than when processing is performed. Therefore, it is preferable that the temperature of the semiconductor wafer W does not rise. Also, when the semiconductor wafer W is removed from the electrostatic chuck 4, as shown in the figure, after the plasma processing is completed, first, the applied high-frequency power value is reduced to a power value (0 (Not W). After this, the application of DC voltage (HV) to the electrostatic chuck electrode 4a was stopped. Thereafter, the application of high frequency power is stopped to extinguish the plasma. When the application of the DC voltage (HV) to the electrostatic chuck electrode 4a is stopped, a voltage (for example, about 200 V) having a polarity opposite to that of the suction is temporarily applied to the electrostatic chuck electrode 4a. A voltage is applied to a to remove the charge and facilitate removal of the semiconductor wafer W. The application of such a voltage of the opposite polarity is performed as needed. If the semiconductor wafer W can be easily removed from the controversial check 4 without applying the voltage of the opposite polarity, the application of the opposite polarity is performed. No voltage is applied.
図 Ίは、 上記のような静電チヤック 4による半導体ウェハ Wの吸着の シーケンスの際の、 静電チャック (E S C) の銅製の電極部 (C u) 及 びポリイミ ド製の絶縁膜部 (P I ) と、 多層半導体ウェハ (Multi Layer Wafer ) の裏面酸化膜部 (B . S . O x ) 及ぴシリ コン基板部 (S i sub ) 及び酸化膜部 ( O x ) と、 真空チャ ンパ一内の処理空間部 (Space ) 及び上部電極部 (Wall) の各部の電位の変化を示すものであ る。  Figure 4 shows the sequence of the chucking of the semiconductor wafer W by the electrostatic chuck 4 as described above. The copper electrode part (Cu) of the electrostatic chuck (ESC) and the polyimide insulating film part (PI ), The backside oxide layer (B.S.Ox) of the multi-layer semiconductor wafer (Multi Layer Wafer), the silicon substrate (Sisub) and the oxide layer (Ox), and the inside of the vacuum chamber. It shows changes in the potential of each part of the processing space (Space) and upper electrode part (Wall).
同図に示すように、 まず、 載置台 2に設けられたウェハ支持用のピン を降下させて半導体ウェハ Wを載置台 2上に載置すると、 図中①で示す ように、 各部の電位はゼロの状態であり、 この後、 真空チャンバ一 1内 にガスの導入を開始した際も図中②で示すように、 各部の電位はゼロの 状態である。  As shown in the figure, first, when the semiconductor wafer W is mounted on the mounting table 2 by lowering the wafer supporting pins provided on the mounting table 2, as shown by 部 in the figure, the potential of each part becomes In this state, when the introduction of gas into the vacuum chamber 11 is started thereafter, the potential of each part is in the state of zero as shown by ② in the figure.
この後、 高周波電力の印加を開始してプラズマを発生させると、 図中 ③で示すように、 半導体ウェハ Wの電位が、 プラズマの状態で決まるマ イナス数 1 0 0 V程度の電位となる。  Thereafter, when the application of high-frequency power is started to generate plasma, the potential of the semiconductor wafer W becomes a potential of about 100 V minus the number of negative electrodes determined by the state of the plasma, as shown by ③ in the figure.
そして、 この状態で、 静電チャック用電極 4 aへの直流電圧 (HV) の印加を開始すると、 図中④で示すように、 静電チャック用電極 4 aの 電位が、 印加した直流電圧 (HV) の電位 (例えば、 1. 5 KV程度) となり、 絶縁膜部 (P I ) に電位差が生じて半導体ウェハ Wの吸着が行 われる。 Then, in this state, when the application of the DC voltage (HV) to the electrostatic chuck electrode 4a is started, the potential of the electrostatic chuck electrode 4a is changed to the applied DC voltage ( HV) (for example, about 1.5 KV), causing a potential difference in the insulating film portion (PI) and causing the semiconductor wafer W to be attracted. Is
このように、 上記のような静電チヤック 4による半導体ウェハ Wの吸 着のシーケンスによれば、 半導体ウェハ Wの表面に、 静電チャック用電 極 4 aへの直流電圧 (H V ) の印加に伴なう高い電圧がかからないので、 半導体ウェハ Wの表面に不所望な異常放電が生じることを防止すること ができる。  As described above, according to the sequence of adsorption of the semiconductor wafer W by the electrostatic chuck 4 as described above, the DC voltage (HV) is applied to the surface of the semiconductor wafer W to the electrode 4 a for the electrostatic chuck. Since the accompanying high voltage is not applied, it is possible to prevent undesirable abnormal discharge from occurring on the surface of the semiconductor wafer W.
なお、 第 2の実施例において説明してきた、 高周波電力を印加した後 に直流電圧を印加するシーケンスについて、 以下に説明するような効果 がある。  Note that the sequence described in the second embodiment for applying a DC voltage after applying high-frequency power has the following effects.
図 9に示すようなシーケンス、 すなわちプラズマ処理開始時における 静電チヤック用電極 4 aへの直流電圧印加後の下部電極 (または上部電 極) への高周波電力印加、 及びプラズマ処理終了後における高周波電力 O F F後の直流電圧 O F Fを行う と、 半導体ウェハ Wを吸着又は離脱さ せる際に、 図 1 0に示すように半導体ウェハ Wに大きな電圧がかかる。 それにより、 半導体ウェハ W表面に損傷、 具体的には直径数 + m程度 の欠けが発生する可能性があり、 その欠けが発生する場所によっては エッチング中にアーキングを引き起こし、 製品不良を起こしてしまう。 また、 欠けたものがパーティクルとなり、 半導体ウェハ W表面に付着し てしまうこともある。  A sequence as shown in FIG. 9, that is, high-frequency power is applied to the lower electrode (or upper electrode) after applying a DC voltage to the electrostatic chuck electrode 4a at the start of the plasma processing, and high-frequency power is applied after the plasma processing is completed When the DC voltage is turned OFF after the OFF, a large voltage is applied to the semiconductor wafer W as shown in FIG. 10 when the semiconductor wafer W is attracted or desorbed. As a result, the surface of the semiconductor wafer W may be damaged, specifically, a chip having a diameter of about several m may be generated. Depending on a place where the chip is generated, arcing may occur during etching and a product defect may occur. . In addition, the chipped particles become particles and may adhere to the surface of the semiconductor wafer W.
しかし、 本実施例において説明してきた、 処理開始時に R F O N→ H V O N、 処理終了時に H V O F F→R F O F Fというシーケン スの場合には、 半導体ウェハ Wに高電圧がかからないので、 半導体ゥェ ハ Wへの損傷がなくなるとともに、 半導体ウェハ W表面のパーティクル を防ぐことができる。  However, in the case of the sequence described in this embodiment, in which RFON → HVON at the start of the process and HVOFF → RFOFF at the end of the process, the semiconductor wafer W is not damaged because a high voltage is not applied to the semiconductor wafer W. As a result, particles on the surface of the semiconductor wafer W can be prevented.
また、 図 9のようなシーケンスで、 半導体ウェハ W表面に損傷が起こ らない場合であっても、 静電チャック用電極 4 aへの直流電圧の印加に より半導体ウェハ Wが帯電してしまうため、 その静電気力により処理室 内に通常浮遊している帯電パーティクルが、 半導体ウェハ wに付着して しまう可能性がある。 In addition, in the sequence shown in FIG. 9, even if the surface of the semiconductor wafer W is not damaged, the DC voltage is not applied to the electrostatic chuck electrode 4a. Since the semiconductor wafer W is more charged, the charged particles normally floating in the processing chamber may adhere to the semiconductor wafer w due to the electrostatic force.
しかし、 処理開始時に R F O N→H V O N、 処理終了時に H V O F F→R F O F Fというシーケンスの場合には、 静電チャックへの 直流電圧の印加前に高周波放電が維持されているため、 浮遊している帯 電パーティクルはイオンシース中にトラップされることになり、 結果的 にパーティクルの半導体ウェハ W表面への付着を減少させることができ る。 このような効果もある。  However, in the case of the sequence of RFON → HVON at the start of the process and HVOFF → RFOFF at the end of the process, the high-frequency discharge is maintained before the DC voltage is applied to the electrostatic chuck. The particles are trapped in the ion sheath, and as a result, the adhesion of particles to the surface of the semiconductor wafer W can be reduced. There is also such an effect.
以下に、 イオンシース中トラップの効果を検証した結果を示す。  The results of verifying the effect of the trap in the ion sheath are shown below.
図 1 1は、 半導体ウェハ Wを吸着するための静電チヤックの直流印加 電圧の大きさの相違による付着パーティクル数の相違を調べた結果を示 すものである。  FIG. 11 shows the result of examining the difference in the number of adhered particles due to the difference in the magnitude of the DC applied voltage of the electrostatic chuck for adsorbing the semiconductor wafer W.
すなわち、 まず、 プラズマ処理装置の処理チャンバ一内にパーテイク ル発生源となる C F系の反応物を付着させ (シーズニング) 、 この後、 処理チヤンバー内に半導体ウェハ Wを搬入して静電チヤック上に載置し て一定時間処理ガスを流通させ、 しかる後、 半導体ウェハ Wの除電を 行って処理チヤンバー内から搬出し、 半導体ウェハ Wに付着したパー ティクル数を、 パーティクルの大きさを 3種類に分けて、 この 3種類の 大きさごとにカウントしたもので、 静電チャックの直流電圧を、 0 V、 1 . 5 k V、 2 . O k V、 2 . 5 k Vと して、 夫々の場合について調べ た結果を示すものである。  That is, first, a CF-based reactant serving as a source of particles is attached to the processing chamber 1 of the plasma processing apparatus (seasoning), and then the semiconductor wafer W is loaded into the processing chamber and placed on the electrostatic chuck. The semiconductor wafer W is placed on the semiconductor wafer W, and the processing gas is circulated for a certain period of time.After that, the semiconductor wafer W is neutralized and unloaded from the processing chamber. The DC voltage of the electrostatic chuck is 0 V, 1.5 kV, 2.0 kV, and 2.5 kV. In each case, This shows the results of an investigation.
同図に示すように、 静電チャックの直流印加電圧を高めると、 半導体 ウェハ Wに付着するパーティクルの数が、 増加することが分かる。 すな わち、 静電チャックへの直流電圧の印加が、 半導体ウェハ Wに対する パーティクルの付着に影響を与えることが分かる。 なお、 上記シーズニング工程の処理条件は、 圧力 : 6. 6 5 P a、 高 周波電力 : 3 5 0 0 W、 使用ガス : C4 F8 /A r /C H2 F2 = 1 3 /6 0 0/5 s c c ms ウェハ裏面圧力 (中央/周縁) : 1 3 3 0 Z 3 9 9 0 P a、 温度 (天井/側壁/底部) : 6 0/ 6 0//6 0°C、 高周波 印加時間 : 3分である。 As shown in the figure, it can be seen that increasing the DC applied voltage of the electrostatic chuck increases the number of particles adhering to the semiconductor wafer W. That is, it can be seen that the application of a DC voltage to the electrostatic chuck affects the adhesion of particles to the semiconductor wafer W. The processing conditions of the seasoning process were as follows: pressure: 6.65 Pa, high-frequency power: 350 W, gas used: C 4 F 8 / Ar / CH 2 F 2 = 1 3/60 0/5 sccm s Wafer back pressure (center / peripheral): 1330Z3990Pa, temperature (ceiling / sidewall / bottom): 60/60/60 ° C, high frequency application time : 3 minutes.
また、 半導体ウェハ Wを静電チヤック上に配置してガスを流通させる 際の圧力、 使用ガス、 ウェハ裏面圧力、 温度の条件は、 上記と同じであ り、 高周波電力 = 0、 ガス流通時間は 6 0秒である。  The pressure, gas used, wafer backside pressure, and temperature conditions when the semiconductor wafer W is placed on the electrostatic chuck and gas is passed are the same as described above. 60 seconds.
さらに、 上記除電工程は、 半導体ウェハ Wの除電を、 圧力 : 2 6. 6 P a、 印加電圧 : 一 1. 5 k V、 電圧印加時間 : 1秒、 及び、 圧力 : 5 3. 2 P a、 Nつ : 1 0 0 0 s c c m、 時間 : 1 5秒の条件で行い、 静 電チャックの除電を、 印加電圧: — 2. O k V、 電圧印加時間 : 1秒で 行った。 なお、 このように除電を行うのは、 プロセス終了後の半導体ゥ ェハ Wを搬送する際に半導体ウェハ Wが跳ねてしまうと余計なパーティ クルの再付着を招く恐れがあるため、 つまり、 除電により、 このような 半導体ウェハ Wの跳ねが起きないようにするためである。  Further, in the above static elimination step, the static elimination of the semiconductor wafer W is performed by applying a pressure of 26.6 Pa, an applied voltage of 1.5 kV, a voltage application time of 1 second, and a pressure of 53.2 Pa. , N: 100 sccm, time: 15 seconds, and static elimination of the electrostatic chuck was performed at an applied voltage of —2, OkV, and a voltage applied time of 1 second. It is to be noted that such static elimination is performed because the semiconductor wafer W after the process is conveyed may cause extra particles to adhere again if the semiconductor wafer W jumps when the semiconductor wafer W is transferred. Thereby, such a jump of the semiconductor wafer W does not occur.
また、 図 1 2は、 上記のシーズニング工程の後、 半導体ウェハ Wを処 理チャンバ一内に配置し、 この状態で 02 ドライク リーニングを行って シーズニング工程で付着した反応物から多数のパーティクルを発生させ. 半導体ウェハ Wに付着したパーティクルの数を、 処理開始時に R F O N→H V ON、 処理終了時に HV O F F→R F O F Fというシー ケンスの場合と、 処理開始時に HV ON→R F ON、 処理終了時に R F O F F→H V O F Fというシーケンスの場合とについて測定し た結果を示すものである。 なお、 かかる測定において、 シーズエングェ 程及び除電工程は、 前述した場合と同様であり、 O2 ドライク リーニン グ工程は、 圧力 : 1 3. 3 P a、 高周波電力 : 1 0 0 0 W、 使用ガス : 02 = 1 0 0 0 s c c m ウェハ裏面圧力 (中央ノ周縁) : 1 3 3 0ノFurther, FIG. 1 2, after the seasoning process, placing the semiconductor wafer W to the processing chamber in one, generates a large number of particles from the reactant deposited in seasoning step performed 0 2 Doraiku cleaning in this state The number of particles adhering to the semiconductor wafer W is calculated in the order of RFON → HVON at the start of processing, HVOFF → RFOFF at the end of processing, and HVON → RFON at the start of processing and RFOFF → HVOFF at the end of processing. This shows the results of measurements for the case of the sequence described above. In this measurement, the seeds enging process and the static elimination process are the same as those described above, and the O 2 dry cleaning process is performed under the following conditions: pressure: 13.3 Pa, high-frequency power: 1000 W, gas used: 0 2 = 1 0 0 0 sccm Wafer back pressure (central edge): 133 0
3 9 9 0 P a、 温度 (天井ノ側壁ノ底部) : 6 0/ 6 0Z6 0°C、 高周 波印加時間 : 3 0秒である。 390 Pa, temperature (top and bottom): 60 / 60Z60 ° C, high-frequency application time: 30 seconds.
同図に示すように、 処理開始時に R F ON→H V ON、 処理終了 時に HV O F F→R F O F Fというシーケンスを採用することに よって、 付着するパーティクルの数を大幅に減少させることができる。 なお、 図 8に示すシーケンスのように、 半導体ウェハ Wを載置台 2に 設けられたウェハ支持用のピン (支持棒) で支持した状態 (①) で静電 チャック用電極 4 aへの直流電圧 (HV) の印加を開始し (②) 、 この 後、 ウェハ支持用のピンを下降させて半導体ウェハ Wを載置台 2上に載 置し (③、 ④) 、 半導体ウェハ wを吸着させる場合も、 半導体ウェハ w の表面が印加した直流電圧 (HV) の電位となることがない。 したがつ て、 このよ うな吸着シーケンスによっても、 半導体ウェハ Wの表面に不 所望な異常放電が生じることを防止することができる。 伹し、 このよう なシーケンスは、 ウェハ支持用のピンが導電性であり、 このピンから半 導体ウェハ Wに電荷が供給される構成となっていなければ行うことがで きない。  As shown in the figure, by adopting the sequence of RF ON → HV ON at the start of the process and HVOFF → RFOFF at the end of the process, the number of attached particles can be significantly reduced. As shown in the sequence of FIG. 8, the DC voltage applied to the electrostatic chuck electrode 4a while the semiconductor wafer W is supported by the wafer support pins (support rods) provided on the mounting table 2 (台). (HV) is applied (②), and thereafter, the semiconductor wafer W is placed on the mounting table 2 by lowering the wafer supporting pins (③, ④), and the semiconductor wafer w is also attracted. However, the surface of the semiconductor wafer w does not reach the potential of the applied DC voltage (HV). Therefore, even by such a suction sequence, it is possible to prevent occurrence of an undesirable abnormal discharge on the surface of the semiconductor wafer W. However, such a sequence cannot be performed unless the pins for supporting the wafer are conductive and electric charges are supplied to the semiconductor wafer W from the pins.
また、 上記のような静電チヤックによる吸着の際に生じる異常放電は. 同じクーロン型の静電チヤックであっても、 双極型の静電チヤックを使 用すれば、 防止することができる。  In addition, abnormal discharge that occurs when the electrostatic chuck is attracted by the above-described electrostatic chuck can be prevented by using a bipolar electrostatic chuck even with the same Coulomb-type electrostatic chuck.
なお、 以上の例では、 平行平板型のエッチング装置を使用したエッチ ング処理の実施形態について説明したが、 本発明はかかる実施形態に限 定されるものではなく、 あらゆるプラズマ処理に使用できることは勿論 である。 また、 上記の実施形態では、 エッチング処理を行うエッチング 装置の真空チャンパ一内で弱いプラズマを作用させる場合について説明 したが、 処理を行う装置とは別の場所で弱いプラズマを作用させ、 半導 体ウェハ wを初期化することもできる。 In the above example, an embodiment of an etching process using a parallel plate type etching apparatus has been described. However, the present invention is not limited to such an embodiment, and it is needless to say that the present invention can be used for any plasma processing. It is. Further, in the above embodiment, the case where the weak plasma is applied in the vacuum chamber of the etching apparatus for performing the etching process has been described. The body wafer w can be initialized.
以上詳細に説明したように、 本発明によれば、 被処理基板に生じる表 面アーキングの発生を防止して、 従来に較べて生産性の向上を図ること ができる。 産業上の利用可能性  As described above in detail, according to the present invention, it is possible to prevent surface arcing occurring on a substrate to be processed and to improve productivity as compared with the related art. Industrial applicability
本発明に係るプラズマ処理方法及びプラズマ処理装置は、 半導体装置 の製造を行う半導体製造産業等において使用することが可能である。  The plasma processing method and the plasma processing apparatus according to the present invention can be used in a semiconductor manufacturing industry or the like that manufactures semiconductor devices.
したがって、 産業上の利用可能性を有する。  Therefore, it has industrial applicability.

Claims

請 求 の 範 囲 The scope of the claims
1 . 被処理基板にプラズマを作用させてプラズマ処理を行うにあたり、 前記プラズマ処理を行う前に、 当該プラズマ処理に使用するプラズマよ りも弱いプラズマを前記被処理基板に作用させて、 当該被処理基板の電 荷の状態を一定の状態とし、 この後、 前記プラズマ処理を行うことを特 徴とするブラズマ処理方法。 1. In performing plasma processing by applying plasma to a substrate to be processed, before performing the plasma processing, a plasma weaker than the plasma used for the plasma processing is applied to the substrate to be processed, and the plasma processing is performed. A plasma processing method characterized in that the state of charge on a substrate is kept constant, and thereafter, the plasma processing is performed.
2 . 請求項 1記載のプラズマ処理方法において、  2. The plasma processing method according to claim 1,
前記弱いプラズマを前記被処理基板に所定時間作用させ、 この後、 前 記被処理基板を吸着保持するための静電チヤックに直流電圧を印加する ことを特徴とするプラズマ処理方法。  A plasma processing method, comprising: applying the weak plasma to the substrate to be processed for a predetermined time; and thereafter, applying a DC voltage to an electrostatic chuck for suction-holding the substrate to be processed.
3 . 請求項 2記載のプラズマ処理方法において、  3. In the plasma processing method according to claim 2,
前記弱いプラズマを消す前に、 前記静電チヤックに対する直流電圧の 印加を開始することを特徴とするプラズマ処理方法。  A plasma processing method characterized by starting applying a DC voltage to the electrostatic chuck before extinguishing the weak plasma.
4 . 請求項 1〜 3いずれか 1項記載のプラズマ処理方法において、 前記弱いプラズマが、 A rガス、 又は 0 2 ガス、 又は C F 4 ガス、 又 は N 2 ガスによって形成されたプラズマであることを特徴とするプラズ マ処理方法。 4. In the claims 1-3 plasma processing method according to any one, said weak plasma, A r gas, or 0 2 gas, or CF 4 gas, also a plasma formed by the N 2 gas A plasma processing method characterized by the following.
5 . 請求項 1〜 4いずれか 1項記載のプラズマ処理方法において、 前記弱いプラズマが、 0 . 1 5〜 1 . 0 WZ c m 2 の高周波電力に よって形成されることを特徴とするプラズマ処理方法。  5. The plasma processing method according to any one of claims 1 to 4, wherein the weak plasma is formed by a high-frequency power of 0.15 to 1.0 WZ cm2. .
6 . 請求項 1〜 5いずれか 1項記載のプラズマ処理方法において、 前記弱いプラズマを、 5〜 2 0秒の間前記被処理基板に作用させるこ とを特徴とするプラズマ処理方法。  6. The plasma processing method according to any one of claims 1 to 5, wherein the weak plasma is applied to the substrate to be processed for 5 to 20 seconds.
7 . 請求項 1〜 6いずれか 1項記載のプラズマ処理方法において、 前記プラズマ処理の開始時に、 プラズマを発生させるための高周波電 力の印加を開始した後、 前記静電チヤックに対する直流電圧の印加を開 始し、 前記プラズマ処理の終了時に、 前記静電チャックに対する直流電 圧の印加を停止した後、 前記高周波電力の印加を停止することを特徴と するプラズマ処理方法。 7. The plasma processing method according to any one of claims 1 to 6, wherein at the start of the plasma processing, a high-frequency power for generating plasma is provided. After the application of force is started, the application of a DC voltage to the electrostatic chuck is started.At the end of the plasma processing, the application of the DC voltage to the electrostatic chuck is stopped, and then the application of the high-frequency power is stopped. A plasma processing method.
8 . 請求項 1 ~ 6いずれか 1項記載のプラズマ処理方法において、 前記被処理基板を前記静電チヤックの上方に導体で接地された支持棒 により支持した状態で、 前記静電チヤックに対する直流電圧の印加を開 始し、 この後、 前記被処理基板を下降させて前記静電チャックの上に載 置することを特徴とするプラズマ処理方法。  8. The plasma processing method according to any one of claims 1 to 6, wherein the substrate to be processed is supported by a support bar grounded by a conductor above the electrostatic chuck, and a DC voltage is applied to the electrostatic chuck. A plasma processing method comprising: starting application of a substrate; thereafter, lowering the substrate to be processed and mounting the substrate on the electrostatic chuck.
9 . 請求項 1〜 8いずれか 1項記載のプラズマ処理方法において、 前記プラズマ処理がェツチング処理であり、 当該ェツチング処理を行 う処理チャンバ一内で、 前記被処理基板に前記弱いプラズマを作用させ ることを特徴とするプラズマ処理方法。  9. The plasma processing method according to any one of claims 1 to 8, wherein the plasma processing is etching processing, and the weak plasma is caused to act on the substrate to be processed in a processing chamber that performs the etching processing. A plasma processing method comprising:
1 0 . 被処理基板にプラズマ処理を施すプラズマ処理機構を具備したプ ラズマ処理装置であって、 前記プラズマ処理機構を制御し、 請求項 1〜 9いずれか 1項記載のプラズマ処理方法を行う制御部を具備したことを 特徴とするブラズマ処理装置。  10. A plasma processing apparatus comprising a plasma processing mechanism for performing plasma processing on a substrate to be processed, wherein the plasma processing mechanism is controlled to perform the plasma processing method according to any one of claims 1 to 9. A plasma processing apparatus comprising:
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