Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
  • H03M13/23—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using convolutional codes, e.g. unit memory codes
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes

Definitions

• the present invention relates to the field of wireless communications and is particularly, but not exclusively, applicable to methods and apparatus for encoding sets of information bits for use in a wireless communications system.
• One such encoding can be convolutional encoding.
• the encoded data (with the encoding producing more data than was input to allow for the inclusion of the error correction redundancies in the data), when received by the receiver, is decoded by a decoder.
• Such decoders normally use the well known Niterbi decoding method in one form or another to retrieve the original data.
• transmission speeds and decoding speeds have been pushed higher and higher, the encoding is still executed in a serially bitwise manner. Essentially, data to be encoded is serially fed to the encoder and the resulting encoded data is also output serially.
• serial convolutional encoders Unfortunately, such an approach would not only lead to increased power consumption but also to elevated device temperatures and more complex circuit layouts when implementing the design.
• the present invention relates to methods and devices for encoding in parallel a set of data bits for use in communications systems.
• the set of data bits to be encoded is divided into two subsets with the first subset being encoded in parallel using the second subset.
• the first subset is also encoded in parallel using a subset of an immediately preceding set of data bits.
• Parallel encoding is realized by using an encoding module utilizing multiple single bit submodules. Each submodule receives a single bit from the first subset and either the second subset or the subset of the immediately preceding data set.
• Each single bit submodule produces a pair of output bits from the convolutional encoding of a single bit of the first subset using either the second subset or the subset of the immediately preceding data set.
• the present invention provides a method for encoding a plurality of data bits for use in communications device, the method comprising: a) receiving a set of data bits for encoding; b) encoding in parallel a subset of said set of data bits using at least one other subset of data bits to produce at least one first set of output bits; c) encoding in parallel said subset of said set of data bits using at least one previous subset of data bits to produce at least one second set of output bits, the or each of said previous subset being a subset of a previous set of data bits.
• the present invention provides a method for encoding a set of data bits for use in a communications system, the method comprising the steps of: a) receiving first and second subsets of said set of data bits; b) convolutionally encoding said first subset using said second subset to produce a first set of output bits; c) convolutionally encoding said first subset using a previous subset of an immediately preceding set of data bits to produce a second set of output bits; and d) replacing said previous subset with said second subset of said set of data bits for use with a next set of data bits, wherein said encoding in steps b) and c) are executed in a bitwise parallel manner.
• the present invention provides a device for encoding a set of data bits for use in a communications system, the device comprising:
• first encoding means for convolutionally encoding a subset of data bits, said first encoding means receiving inputs from said first receiving means and from said second receiving means to produce a first set of output bits
• second encoding means for convolutionally encoding a subset of data bits, said second encoding means receiving inputs from said first receiving means and from said storage means to produce a second set of output bits
• the present invention provides a system for encoding a current set of data bits for use in a communications device, the device comprising:
• each of said at least two stages comprising:
• - storage means for storing a subset of data bits, said subset of data bits being chosen from a group comprising:
• - encoding means for encoding contents of said first receiving means using contents of said storage means to produce a set of output bits, wherein at least one encoding stage receives a subset of dat bits form another encoding stage for storage in said storage means and for encoding a subset of said current set of data bits.
• Figure 1 is a block diagram of an encoder system according to one embodiment of the invention.
• Figure 2 is a block diagram of an encoding of an encoding module used in the encoder system of Figure 1;
• Figure 3 is logic diagram illustrating the logic implemented by a single-bit encoding submodule used in the encoding module of Figure 2;
• Figure 4 is a block diagram of a single-bit encoding submodule used in the encoding module of Figure 2.
• FIG. 1 a block diagram of a parallel encoder system 5 is illustrated.
• a bus 10 feeds a first receiving means 20 and a second receiving means 30 while a storage means 40 is coupled to the second receiving means 30.
• a first encoding module 50 (also referred to as first encoding means) is coupled to the first receiving means 20 and the second receiving means 30.
• a second encoding means 60 (also referred to as second encoding means 60) is coupled to the storage means 40 and the first receiving means 20.
• the encoder system 5 receives in parallel a current set of data bits to be encoded by way of the bus 10.
• the current set of data bits (CURRENT [11:0]) is separated into two subsets with a fist subset being fed into the first receiving means 20 and a second subset begin fed into the second receiving means 30.
• the storage means 40 stores a subset (PREVIOUS [11:6]) of an immediately preceding set of data bits. Once the current set of data bits are stored in the first and second receiving means, these are sent to the encoding modules 50, 60 with the first encoding module 50 receiving the first and second subsets of the current set of data bits.
• the second encoding module 60 receives the first subset and the subset stored in the storage means 40.
• the encoding modules 50, 60 then encodes, in a parallel bitwise manner, the first subset using the second subset and the subset stored in the storage means 40.
• Each encoding module independently produces a set of output bits which, when taken together, comprise the output of the encoder system 5.
• the encoder system output can then be fed into another bus (not shown) for transportation to a next stage in processing.
• the bus 10 is a 12 bit bus carrying a current set of 12 bits with each subset having 6 data bits.
• the 6 LSB (least significant bits CURRENT [5:0]) of the 12 bit current set is fed and stored by the first receiving means 20 while the 6 MSB (most significant bits CURRENT [11 :6]) of the 12 bit current set is fed and stored by the second receiving means 30.
• the storage means 40 receives the second subset (PREVIOUS [11:6]) stored in the second receiving means 30 when a new current set of data bits is clocked into the second receiving means.
• the switching means for storing the contents of the second receiving means 30 can be clocked into the storage means 40. Alternatively, the switching/storing can be done as soon as the set of output data bits are produced. To initiate the encoder system, all zeros are set as the content of the storage means 40.
• each of the encoding modules produce a 12 bit output set.
• the storage means 40 and the first and second receiving means 20, 30 can be constructed as registers or suitable flip-flop circuits. Data subsets can then be clocked into he registers or flip-flops in parallel and can also be fed in parallel into the encoding modules 50, 60.
• each encoding module has 12 data inputs - a 6 bit subset of the current set of data bits and a 6 bit subset from either the current set or the immediately preceding set of data bits. As previously mentioned, an output set of 12 data bits result from each of the encoding modules.
• Each encoding module may be implemented as illustrated in Figure 2.
• a number of single-bit encoding submodules 70A-70F are present with each submodule receiving 7 data inputs - a single bit from the first subset (one of CURRENT [5 :0] ) and 6 bits from either the second subset (CURRENT 11 :6]) or the subset stored in the storage means (PREVIOUS [11 :6])
• the single bit to be encoded is encoded using the other 6 bit input to result in two output bits.
• These output bits (x[0], y[0] to x[5], y[5]) comprise the output set of bits for the encoding module.
• Each submodule implements a combinational logic circuit that accomplishes the encoding.
• the logic to be implemented for encoding IEEE 802.1 la or Hiperlan 2 bitstreams is similar.
• s[a] the ath bit from the 6 bit input to the single bit encoding submodule
• the logic can therefore be simplified into the diagrams in Figure 3.
• Figure 3 each have 5 inputs and specifically implement the logical equations presented above.
• Figure 4 shows a single bit encoding submodule with 7 inputs and 2 outputs. The submodule can then implement any encoding scheme as long as the combinational circuit within is properly configured.
• the above concepts and designs can therefore encode, in a parallel bitwise manner, a set of current data bits.
• the system 5 in Figure 5 can be seen as a two stage encoding system with each stage having three components - a first receiving means (such as receiving means 20), a storage means (such as receiving means 30 or storage means 40), and an encoding module which encodes the data in the first receiving means using the dat in the storage means.
• Multiple stages can therefore be either cascaded or placed in parallel to encode multiple bit sets of data bits.
• the cascading need not be merely in terms of the output bits being cascaded in successive stages.
• the inputs may also be cascaded such as in the embodiment explained above where a current input subset (such as CURRENT [11 :6]) is subsequently used by a later stage in a succeeding step (such as becoming the subset PREVIOUS [11 :6]).
• a current input subset such as CURRENT [11 :6]
• a succeeding step such as becoming the subset PREVIOUS [11 :6]
• bit widths other than a 12 bit set or a 6 bit subset may be used.
• the design may be extended to other encoding schemes so that not all of the resulting or output bits of the encoder system 5 is valid or useful.
• different coding rates produce different numbers of valid or useful bits.
• a coding rate of l A all 24 outputs bits from the encoder system 5 are valid.
• a coding rate of 2/3 only the 18 LSB bits are valid.
• this encoding rate only 6 bits of the output set produced by the encoding module 50 are valid.
• For a coding rate of 3/4 only the 16 LSB bits of the overall set output are valid. Thus, only 4 bits of the output set produced by the encoding module 50 are valid.

Landscapes

• Physics & Mathematics (AREA)
• Probability & Statistics with Applications (AREA)
• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Error Detection And Correction (AREA)
• Compression Or Coding Systems Of Tv Signals (AREA)

Priority Applications (2)

Applications Claiming Priority (4)

Publications (2)

Family

ID=31191297

Family Applications (1)

Country Status (5)

Families Citing this family (27)

Family Cites Families (17)

• 2003
  • 2003-07-29 US US10/629,644 patent/US7318189B2/en not_active Expired - Fee Related
  • 2003-07-31 JP JP2004525088A patent/JP4292298B2/ja not_active Expired - Fee Related
  • 2003-07-31 KR KR1020057001719A patent/KR101026444B1/ko not_active Expired - Fee Related
  • 2003-07-31 AU AU2003249822A patent/AU2003249822A1/en not_active Abandoned
  • 2003-07-31 WO PCT/CA2003/001133 patent/WO2004013974A2/en not_active Ceased
• 2007
  • 2007-11-30 US US11/948,953 patent/US7765457B2/en not_active Expired - Fee Related

Also Published As

Similar Documents

Legal Events