WO2003090362A1 - Codeur et decodeur de detection d'erreur, et diviseur - Google Patents
Codeur et decodeur de detection d'erreur, et diviseur Download PDFInfo
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- WO2003090362A1 WO2003090362A1 PCT/JP2002/003965 JP0203965W WO03090362A1 WO 2003090362 A1 WO2003090362 A1 WO 2003090362A1 JP 0203965 W JP0203965 W JP 0203965W WO 03090362 A1 WO03090362 A1 WO 03090362A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
- H03M13/091—Parallel or block-wise CRC computation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
- H03M13/093—CRC update after modification of the information word
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0041—Arrangements at the transmitter end
- H04L1/0043—Realisations of complexity reduction techniques, e.g. use of look-up tables
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
- H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
- H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
- H04L1/1829—Arrangements specially adapted for the receiver end
Definitions
- the present invention relates to an error detection coding / decoding device and a division device, and more particularly to an error detection coding device and a parity generation device for generating an error detection parity bit of an input data sequence and adding the parity bit to the data sequence.
- the present invention relates to an error detection decoding device that performs error detection processing on an input data sequence to which a bit is added to detect an error in an input data sequence, and a division device that can be used in these error detection encoding and decoding devices.
- Error detection codes are used in systems that require data to be transmitted without error when performing data communications, such as mobile communications, faxes, and cash dispensers in banks, or large-capacity devices such as magnetic disks and CDs. Applied to systems that require data to be read without error when storing data.
- An error detection code is usually used in combination with an error correction code to detect an error that cannot be completely corrected by error correction. If an error is detected, retransmission control and reread control are performed. Will be
- Figure 42 shows a configuration example of a system to which error detection is applied.
- the error detection coding unit 1b performs an error detection coding process on the data string of a predetermined bit length generated by the information generation unit 1a, and the error correction coding unit 1c performs convolutional coding or
- the input data sequence is error-correction-coded by turbo coding or the like, and transmitted to the receiving side 3 via the communication channel 2.
- the error correction decoding unit 3a decodes the input coded data sequence by an error correction decoding process, and inputs the decoded data sequence to the error detection decoding unit 3b.
- Error detection decoding section 3b performs error detection decoding processing on the decoded data sequence to detect the presence or absence of an error, and if there is an error, sends a retransmission request signal RRQ to the transmitting side.
- the information extraction unit 3c extracts and outputs data if there is no error.
- CRC Cyclic Redundancy Check
- the CRC side on the transmitting side assumes that a data sequence of a predetermined bit length is a polynomial, divides it by a polynomial (generation polynomial) for generating an error detection code, and the remainder becomes zero.
- the receiving side regards the received data sequence as a polynomial, divides it by the same generator polynomial as the transmitting side, and determines that there is no error if the remainder is ⁇ and that there is an error if the remainder is not zero.
- k-bit information is regarded as a polynomial and is defined as K (x), and the polynomial ⁇ ( ⁇ ) is divided by the generator polynomial G (x) so that the parity bit is set so that the remainder becomes zero. Attach For example, if the generator polynomial G (x) is 16 bits,
- ⁇ 6 ⁇ ( ⁇ ) means a data string in which 16-bit “0” is added to the lower order side of a k-bit data string.
- This CRC calculation device is provided on the 16-stage shift register SR and on the input side at the 0-bit position, 5-bit position, and 12-bit position, and is exclusive of the output data of the previous stage and the built-in pack data.
- Exclusive OR circuit Exclusive OR circuit that performs a logical OR operation. It is composed of EOR1 to EOR3 and a switch SW provided on the output side at the 15-bit position.
- W '(X) is 48 bits during error detection decoding
- a 48-bit signal from a higher order is operated while operating the shift register SR in EOR1 of the CRC arithmetic unit with the same configuration as in Fig. 43 (A).
- the contents of register SR become the remainder R (x), so if this is all "0", it is determined that there is no error. If at least one is not "0", it is determined that there is an error. I do.
- Fig. 43 (B) shows the CRC calculation device (G (x)) in which the number of calculations is reduced by correcting the data input position in Fig. 43 (A).
- the EOR 1 position for data input has moved from the left end to the right end.
- division is performed by inputting EOR1 one bit at a time from the higher order side of the data row, as in the case of Fig. 2 (A). It positions the EOR1 than 2 (A) and just moved from the left end to the right end, which is equivalent to being input while multiplying ⁇ ⁇ 6 to the input data sequence.
- the CRC arithmetic unit In error detection decoding, if the input data sequence (X) is 48 bits with a parity bit (the lower 16 bits are parity bits), the CRC arithmetic unit with the same configuration as in Fig. 43 (B) Input a 32-bit data string from the higher order to the EOR1 while operating the shift register SR. When the 32-bit input is completed, the contents of register SR become a remainder, and this remainder is compared with the remaining 16-bit parity.If there is a perfect match, it is determined that there is no error. Judge that there is. With this, The number of calculations can be reduced to 32.
- error detection decoding can be performed as follows. In other words, if the input data string W (X) is 48 bits with parity bits (the lower 16 bits are parity bits), the EOR1 of the CRC arithmetic unit with the same configuration as in Figure 43 (B) Input all 48-bit data strings from the higher order while operating shift register SR. In this case, if all the contents of the shift register SR are "0", it is determined that there is no error, and if not all "0", it is determined that there is an error. Note that the content of the register SR in this error detection decoding method is not the remainder, but indicates the result of the match detection.
- K (x) ⁇ 31+ ⁇ 30 + ⁇ 29 + ⁇ 28 + ,, + ⁇ 2 + ⁇ 1 + 1
- R (x) ⁇ 15 + ⁇ 12 + ⁇ ⁇ + ⁇ 8 + ⁇ 7 + ⁇ 6 + ⁇ 3 + ⁇ 2 + ⁇ +1
- Fig. 43 (B) In the CRC calculation device shown in Fig. 43 (B), in the initial state, the value of register SR is all "0" To With the switch SW on the A side, only the information bits excluding the parity bit in the input data string W (x) 'are sequentially input. A match between the value of the register SR when only the information bits have been input and the parity bit, which is the remaining bits of the input data string, is detected. If they match, there is no error, and if they do not match, there is an error.
- Fig. 45 shows the encoded data obtained by adding a 16-bit parity bit to a 32-bit "all" data string and inputting one bit per clock to EOR1 in Fig. 43 (B) from the next side.
- Error detection is performed based on whether or not P 1 matches.As described above, error detection is performed based on whether or not the calculated parity and the parity added to the input data sequence match.
- the decoding method is called a match detection decoding method.
- Figure 46 shows encoded data in which a 16-bit parity bit is added to a 32-bit all-in-one data string. This indicates the contents of the register SR when input is performed.Check whether the value of the shift register SR is all 0 when input of 32 bits of encoded data and 16 bits of parity has been completed. However, if all 0, there is no error, and if there is at least one, there is an error.As described above, there is no error if all "0", and there is an error if there is even one "" ". Is referred to as an all "0" detection decoding method.
- the CRC operation requires at least the operation of the information bit length. That is, the error detection encoder and decoder of FIGS. 44 to 46 require at least 32 clocks.
- the 4th generation (new generation) mobile communication system is said to have a maximum information rate of 100 Mbps or more (wireless LANs of 1 Gbps or more).
- CRC calculation Requires a 100MHz clock. Even in this case, a delay of one packet length is caused only by CRC error detection.
- retransmission control is further taken into consideration, it takes time to generate a retransmission signal request, which leads to a significant reduction in data transmission speed.
- Fig. 47 shows the time chart on the receiving side in the case shown in Fig. 47. If packet # 1 is received and it is NG, it will be understood that the retransmission request will be made after packet # 7. If the CRC calculation is performed at high speed, a retransmission request can be made before that.
- an object of the present invention is to reduce the time required for CRC calculation.
- Another object of the present invention is to reduce the packet delay time even when retransmission control is performed.
- a first aspect of the present invention is an error detection encoding device that creates a parity bit by an error detection encoding process, adds the parity bit to an input data sequence, and encodes it.
- the data dividing means divides the input data sequence to be subjected to the error detection coding into a plurality of pieces, and the dividing means divides the divided sub-data strings by a generator polynomial, calculates the remainder, and performs conversion.
- the error detection encoding process of the present invention if the data sequence is divided into n by the data dividing means, the time required for the CRC operation (parity bit operation) can be reduced to approximately 1 / n. it can.
- the second and third aspects of the present invention are error detection decoding devices that perform error detection processing on an input data sequence to which a parity bit has been added and detect errors in the input data sequence.
- the data dividing means duplicates the input data sequence.
- the division means divides the divided sub-data sequence by a generator polynomial to calculate the remainder, and the conversion means performs, for each residue, a conversion process corresponding to the division position of the sub-data sequence to the remainder.
- the combining means combines the converted values obtained by the conversion processing and outputs a parity bit, and the error detection unit determines that the parity bit matches the parity bit added to the input data. The presence or absence of an error in the input data is detected based on whether or not there is an error.
- the data dividing means divides the input data sequence including the parity bit into a plurality of parts, and the dividing means divides the divided sub-data sequence by a predetermined generator polynomial and divides the remainder.
- the conversion means performs a conversion process on the remainder in accordance with the division position of the sub-data sequence for each of the residues, and a combining unit combines the converted values obtained by the conversion process, and performs error detection.
- the module detects whether or not there is an error in the input data based on whether or not the combination result is all bits "0".
- the time required for the CRC operation can be reduced to approximately one. Error detection can be performed in a short time. In addition, even when retransmission control is performed, the packet delay time can be reduced.
- the fourth invention is a division device that regards a K-bit input data sequence as a first polynomial, divides the same by a second polynomial, and calculates the remainder ⁇ ⁇ .
- the data dividing means divides the input data string into a plurality of pieces, and the dividing means divides the information bits of the sub data string by the second polynomial for each divided sub data string, treating the information bits of the sub data string as a polynomial.
- the conversion unit calculates the remainder, and performs a conversion process on the remainder in accordance with the division position of the sub-data string for each of the residues, and a combining unit combines the converted values obtained by the conversion process.
- the combined result is the remainder when the K-bit input data sequence is divided by the second polynomial.
- this division device if the data sequence is to be divided by ⁇ by the data dividing means, the division is performed.
- the time can be reduced to approximately 1 ⁇ ⁇ .
- FIG. 1 is a block diagram of an error detecting encoder according to the present invention.
- FIG. 2 is an explanatory diagram of a 16 x 16 matrix that performs 1-bit shift in the CRC calculation device.
- Fig. 7 is a connection configuration diagram of the CRC calculation device and the 8-bit shift device.
- Fig. 8 is a connection configuration diagram of the CRC calculation device and the 16-bit shift device.
- FIG. 9 is a connection configuration diagram of the CRC operation device and the 24-bit shift device.
- FIG. 10 is a diagram illustrating a first operation of the error detection encoder.
- FIG. 11 is an explanatory diagram of a second operation of the error detection encoder.
- FIG. 12 is a diagram illustrating a third operation of the error detection encoder.
- FIG. 13 is a diagram illustrating a fourth operation of the error detection encoder.
- FIG. 14 is an explanatory diagram of a fifth operation of the error detection encoder.
- FIG. 15 is a block diagram of the error detection decoder according to the present invention.
- FIG. 16 is a diagram illustrating a first operation of the error detection decoder.
- FIG. 17 is a diagram illustrating a second operation of the error detection decoder.
- FIG. 18 is a diagram illustrating a third operation of the error detection decoder.
- FIG. 19 is a diagram illustrating a fourth operation of the error detection decoder.
- FIG. 20 is a diagram illustrating a fifth operation of the error detection decoder.
- FIG. 21 is a block diagram of another error detection decoder according to the present invention.
- FIG. 22 is a diagram illustrating a first operation of the error detection decoder.
- FIG. 23 is an explanatory diagram of a second operation of the error detection decoder.
- FIG. 24 is a diagram illustrating a third operation of the error detection decoder.
- FIG. 25 is a diagram for explaining a fourth operation of the error detection decoder.
- FIG. 26 is a diagram illustrating a fifth operation of the error detection decoder.
- FIG. 27 is an explanatory diagram of a sixth operation of the error detection decoder.
- FIG. 28 is an explanatory diagram of a seventh operation of the error detection decoder.
- FIG. 29 is an explanatory diagram of advantages of the present invention.
- FIG. 30 is a configuration diagram of the error detection encoder according to the first embodiment.
- FIG. 31 is a configuration diagram of an error detection decoder according to the second embodiment.
- FIG. 32 is a configuration diagram of an error detection decoder according to the third embodiment.
- FIG. 33 is a configuration diagram of the error detection decoder of the fourth embodiment.
- FIG. 34 is a configuration diagram of the error detection decoder of the fifth embodiment.
- FIG. 35 is a configuration diagram of the error detection decoder of the sixth embodiment.
- FIG. 36 is a configuration diagram of the error detection decoder of the seventh embodiment.
- FIG. 37 is a configuration diagram of the entire system and an explanatory diagram of data processing.
- FIG. 38 is a configuration diagram of an error detection decoder as an application example of the seventh embodiment.
- FIG. 39 is a configuration diagram of the error detection decoder of the eighth embodiment.
- FIG. 40 is an explanatory diagram of data processing.
- FIG. 41 is another configuration diagram of the error detection decoder of the eighth embodiment.
- Figure 42 is an example of the configuration of a system to which error detection is applied.
- FIG. 44 illustrates the operation of the error detection encoder.
- FIG. 45 is an explanatory diagram of the coincidence detection decoding method.
- FIG. 46 is an explanatory diagram of the all- "0" detection decoding method.
- FIG. 47 is an explanatory diagram of a conventional problem.
- W '(x) / G (x) X 2 * A (x) / G (x) + xi6B (x) / G (x) + x 8 C (x) / G (x) + D (x) / G (x) Is expressed as
- RA (X) The calculation of RA '(X) is performed as follows. RA '(X)
- Figure 1 is a block diagram of the error detection encoder of the present invention when the error detection encoding target is a 32-bit data sequence b0 to b31.
- the input data division unit 11 converts the 32-bit input data system Ub0 to b31 into 8 bits each of b0 to b7 and b8 to! D 15, bl6 ⁇ b23, b24 ⁇ b31
- the polynomials represented by 8-bit information b24 to b31 are A (x), bl6 to!
- the polynomials represented by 323 8-bit information are B (x), b8 ⁇ ! )
- C (x) be the polynomial expressed by 15 pieces of 8-bit information
- D (x) the polynomial expressed by 8 bits of b0 to b7.
- Each of the CRC calculators 12A, 12B, 12C, and 12D has the configuration shown in FIG. Let 1 be a generator polynomial
- the 24-bit shift unit 13A processes the remainder RA (X) by 24 bits and calculates the remainder RA '(X) of ⁇ 24 ⁇ ( ⁇ ) / G (x), and the 16-bit shift unit 13B computes the remainder RB ( X) is subjected to 16-bit shift processing to calculate the remainder RB '(X) of ⁇ 6 ⁇ ( ⁇ ) G (x), and the 8-bit shift unit 13C shifts the remainder Rc (x) by 8 bits. Process and calculate the remainder Rc '(x) of xsCOOZ GOc). If RA ′ (x), RB ′ (X), RC ′ (X), and RD ′ (x) are obtained, the combining unit 14
- the remainder is synthesized by (exclusive OR (EX-OR) operation for each bit), and the remainder when the 32-bit input data sequence is divided by the generator polynomial G (x), that is, 16 Outputs the CRC parity bit of the bit.
- EX-OR exclusive OR
- the time required for the CRG operation can be reduced to one-fourth of the conventional time. can be shortened to n.
- N-bit shift device N-bit shift device
- FIG. 2 shows that the CRC operation device shown in FIG. 43 (B) performs one-bit shift operation equivalent to inputting one “0” and shifting the contents of the shift register SR by one bit.
- FIG. 4 is an explanatory diagram of a matrix of X 16. The way of looking at this matrix indicates which bit before shift is obtained by the EX-OR operation of each bit after shift in shift register SR. The bit before the shift that is the target of the EX-OR operation is the bit with a "1". For example, the 5th bit after the shift is obtained by the EX-OR of the 4th bit and the 15th bit before the shift, and the 12th bit after the shift is the 12th bit before the shift. It is determined by the 11-bit and 15-bit EX-OR.
- the 0th bit after the shift is the value of the 15th bit before the shift because only one “ ⁇ ” stands.
- the 1st bit after the shift is the value before the shift.
- the 0th bit and the 2nd bit after the shift are the value of the 1st bit before the shift.
- the 8-bit shift device 13C in FIG. 1 converts the 16-bit remainder Rc (x) (represented by a 16 ⁇ 1 matrix) output from the CRC operation device 12C into the right side of FIG. 4 (A). it can be realized Ri by the multiplication circuit for multiplying the conversion matrix a 8.
- FIG. 7 is a connection configuration diagram of the CRC operation device 12C and the 8-bit shift device 13C.
- 8-bit Toshifu Bok device 13C are No ⁇ result of the conversion matrix A 8 and remainder RCG 16 bit Rc '(x) 16 EOR It is configured to output using a circuit.
- the 16-bit shift unit 13B in FIG. 1 converts the 16-bit remainder RB (X) (represented by a 16 ⁇ 1 matrix) output from the CRC operation unit 12B into a conversion matrix on the right side of FIG. 4 (B). This can be realized by a multiplication circuit that multiplies A.
- Fig. 8 is a connection configuration diagram of the CRC calculation device 12B and the 16-bit shift device 13B.
- the 16-bit shift device 13B has a conversion matrix A And the remainder: 16-bit RB '(X), which is the result of multiplication with RB (X), is output using 16 EOR circuits.
- FIG. 9 is a connection configuration diagram of the CRC operation device 12A and the 24-bit shift device 13A.
- 24 bit Toshifu winding device 13A although not shown, FIG. 7, the multiplication result is a 16-bi Tsu Bok and 8 similarly to the transformation matrix A 24 and a remainder RA (X) RA 'of 16 (X) It is configured to output using an EOR circuit.
- 10 to 14 are explanatory diagrams of the operation of each unit of the error detection encoder, and assume that the input data is 32-bit all " ⁇ ".
- FIG 10 (A), (B) is an operation explanatory diagram of the respective CRC arithmetic unit 12A and 24 bit Toshifu winding device 13A, the CRC arithmetic unit 12B sequentially Kai3i ⁇ chi 24 is input at 8 clock higher order side Then, when the input of 24 is completed, the contents of the shift register SR become the remainder RA (X) of A (x) / G (x).
- the 24-bit shift device 13A multiplies the transformation matrix A 24 by the matrix RA (X) of 16X1 and outputs the remainder RA ′ (X) of x 24 A (x) ZG (x).
- x A m in the figure refers to X m.
- Figure 11 (A), (B) is an operation explanatory diagram of the respective CRC arithmetic unit 12B and 16-bit Toshifu winding device 13B, the CRC arithmetic unit 12B sequentially X 23 ⁇ x "in 8 clock higher order side
- the contents of the shift register SR become the remainder RB (X) of B (x) / G (x)
- the 16-bit shift unit 13B converts the transformation matrix and the 16X1 matrix RB ( X) multiplied by x to output the remainder R B '(x) of x ls B ( X ) / G (x).
- Figure 12 (A), (B) is an operation explanatory diagram of the respective CRC arithmetic unit 12C and 8-bit Toshifu winding device 13C, sequential X i 5 ⁇ x the CRC arithmetic unit 12C in 8 clock Ri by higher order side 8 is input, and when the input of ⁇ 8 is completed, the contents of the shift register SR become C (x) ZG (x). The remainder is Rc (x). 8 bit Bok shift device 13C outputs the remainder Rc '(x) of by multiplying matrix Hc (x) of the transformation matrix A 8 and 16X1 x 8 C (x) _ G (x).
- FIG. 14 is an explanatory diagram of the operation of the synthesizing unit 14.
- the combining unit 14 performs an EX-OR operation corresponding to the bits of the calculated remainders RA '(X), RB' (X), RC '(X), and RD (X) to obtain a 16-bit CRC parity. Output.
- FIG. 15 is a block diagram of an error detection decoder according to the present invention when a CRC parity bit of 16 bits is added to the lower order side of input data of 32 bits.
- the data dividing section 21 has a 32-bit input data string bl6 to! 6 excluding the CRC parity bit. ) 47 in 8-bit bl6-b23, b24-! ) 31, b32 ⁇ b39, b40 ⁇ ! Harm to 47)! ) Then ⁇ 24 ⁇ ( ⁇ ) + ⁇ 6 ⁇ ( ⁇ ) + ⁇ 8 C (x) + D (x)
- the polynomials represented by 8-bit information b40 to b47 are A (x), b32 to! B (x) represents the polynomial represented by 339 8-bit information, C (x) represents the polynomial represented by 8-bit information b24 to b31, and bl6 to! )
- D (x) be the polynomial represented by 23 8-bit information.
- the data division unit 21 separates and outputs the CRC parity bits P (x) of b0 to bl5.
- Each of the CRC calculation devices 22A, 22B, 22C, and 22D has the configuration shown in FIG. As a generator polynomial
- the 24-bit shift unit 23A processes the remainder I (x) by 24 bits to calculate the remainder of ⁇ 24 ⁇ ( ⁇ ) / G (x), and the 16-bit shift unit 23B converts the remainder R B (x) to 16 Bit shift processing is performed to calculate the remainder RB '(X) of xi 6 B (x) / G (x), and the 8-bit shift unit 23C performs 8-bit shift processing on the remainder Rc (x).
- the remainder R c '(x) of x8C (x) ZG (x) is calculated.
- Each of the shift devices 23A to 23 can be configured similarly to the error detection encoder. If R A '(x), RB' (X), RC '(X) and RD' (x) are obtained,
- G (x), ie, the parity bit P '(x ) Is output.
- the comparator 25 compares the calculated 16-bit parity bit P ′ ( ⁇ ) with the 16-bit parity bit P (x) added to the input data in a bit-by-bit manner, and if all match, Judge that there is no error, and if even one does not match, judge that there is an error.
- 16 to 2 0 are each part operation explanatory view of the error detection decoder, input data of 48 bit - 16-bit ⁇ ⁇ ⁇ 5 lower order side of the data is CRC parity bits, high-order of the side 32-bit ⁇ 6 ⁇ ⁇ 4? it is assumed to be all "1".
- Figure 16 (A), ( ⁇ ) is a diagram for describing the operation of CRC arithmetic unit 22 ⁇ and 24 bit Toshifu winding device 23 ⁇ respectively, the CRC arithmetic unit 22 ⁇ sequential X 47 ⁇ 8 clock Ri by higher order side. Is input, and the content of the shift register when the input of « ⁇ is completed becomes the remainder RA (X) of ⁇ ( ⁇ ) / G (x).
- the 24-bit Toshifu winding device 23A outputs the remainder RA '(X) of by multiplying matrix RA of the transformation matrix and 16X1 (X) x 24 A ( x) ZG (x).
- Figure 17 (A), (B) is a diagram for describing the operation of each CRC arithmetic unit 22B and 16-bit Toshifu winding device 23B, the CRC arithmetic unit 22B sequentially X 39 ⁇ X 32 8 clock Ri by higher order side type, the contents of the shift register SR is beta (chi) / remainder RB of G (x) (X) when the input of X 32 is completed.
- the 16-bit shift device 23B multiplies the transformation matrix A ⁇ 6 by the matrix RB (X) of 16X1 and outputs the remainder RB '(X) of xisB (x) "G (x).
- FIGS. 18 (A) and (B) are explanatory diagrams of the operation of the CRC operation unit 22C and the 8-bit shift unit 23C, respectively.
- the CRC operation unit 22C has xsi to ⁇ 24 in 8 clocks from the higher side. There type, the contents of the input is complete and Kino shift register SR X 24 is C (x) / G remainder Rc of (x) (x).
- 8-bit Toshifu winding device 23C outputs the remainder Rc '(x) of by multiplying matrix Rc (x) of the transformation matrix A 8 and 16X1 x 8 C (x) G (x).
- Figure 19 is a diagram for describing the operation of CRC arithmetic unit 22D, sequentially X 23 ⁇ ? Is entered in 8 click Lock Repetitive by higher order side to the CRC arithmetic unit 22D, shift when the input of 7 has been completed
- FIG. 20 is an explanatory diagram of the operation of the synthesizing unit 24.
- the combining unit 24 calculates the remainder R A '(x), Performs an EX-OR operation corresponding to the RB '(X), RC' (X), and RD (X) bits and outputs a 16-bit CRC parity ⁇ '(X).
- the time required for error detection can be reduced to 1/4 in the past, and if the input data sequence is divided into 1 / ⁇ , the time required for error detection is required. Time can be reduced to 1 / ⁇ . Therefore, even when retransmission control is performed, the packet delay time can be reduced.
- FIG. 21 is a block diagram of another error detection decoder according to the present invention.
- the data division unit 31 is configured to input a 48-bit input data string b0-! Including a 16-bit CRC parity.
- 347 is divided into 8 bits b0 to b7, b8 to bl5, bl6 to b23, b24 to b31, b32 to b39, b40 to b47.
- a (x) represents a polynomial represented by 47 8-bit information
- B (x) represents a polynomial represented by 8-bit information from b32 to b39
- C (x) the polynomial expressed by the 8-bit information bl6-b23 is D (x)
- the polynomial expressed by the 8-bit information b8-bl5 is E (x)
- the 8-bit information b0-b7 Let F (X) be the polynomial represented by the default information.
- Each of the CRC calculation devices 32A, 32B, 32C, 32D, 32E, and 32F has the configuration shown in FIG.
- the 40-bit shift unit 33A processes the remainder I (x) by 40 bits to calculate the remainder RA '(X) of ⁇ 40 ⁇ ( ⁇ ) / G (x), and the 32-bit shift unit 33B performs the remainder RB and (X) the 32-bit shift process calculates the remainder RB '(X) of x 32 B (x) / G (x), 24 -bit Toshifu Bok apparatus 33C is the remainder Rc (x) 24 bit Toshifu Calculates the remainder Rc '(x) of x 24 C (x) / G (x), and the 16-bit shift unit 33D shifts the remainder R D (x) by 16 bits to obtain xi6D ( x) / G (x) is calculated by the remainder RD '(X), and the 8-bit shift unit 33E shifts the remainder RE (X) by 8 bits.
- the 40-bit shift unit 33A uses a multiplication circuit that multiplies the 16-bit remainder (represented by a 161 matrix) output from the CRC operation unit 32A with the transformation matrix A «on the right side of FIG. 6 (B).
- the 32-bit shifter 33B converts the 16-bit remainder RB (X) (represented by a matrix of 16 1) output from the CRC calculator 32B into a conversion matrix A 32 on the right side of FIG. 6 (A).
- This can be realized by a multiplication circuit that performs multiplication.
- the 24-bit shift device 33C, the 16-bit shift device 33D, and the 8-bit shift device 33E can be configured similarly to the error detection encoder.
- the remainder is synthesized (bit-wise EX-OR operation) to generate a 48-bit input data sequence.
- the remainder when divided by the polynomial G (x), that is, the parity bit P '(x) Output.
- the error detection unit 35 checks whether all the calculated 16-bit parity bits P ′ ( ⁇ ) are “0”, and if all the bits are “0”, determines that there is no error. (CRC O), if at least one is not "0”, judge that there is an error (CRC NG) D
- Fig. 22 to Fig. 28 are explanatory diagrams of the operation of each part of the error detection decoder in Fig. 21.
- the lower 16 bits ⁇ to ⁇ 5 are CRC parity bits, and the higher 32 bits ⁇ 6 to ⁇ 47 of the bit are all “1”.
- Figure 22 (A), ( ⁇ ) is an operation explanatory diagram of the CRC arithmetic unit 32 ⁇ and 40 bit Toshifu winding device 33 ⁇ respectively, the CRC arithmetic unit 32 ⁇ sequentially X 47 ⁇ 40 in 8 clock higher order side Input, the contents of the shift register SR when the other input is completed become the remainder of A (x) / G (x).
- the conversion matrix A 4 is provided by the 40-bit shift device 33A. Is multiplied by the 16X1 matrix RA (X) to output the remainder R A '(x) of x 4 oA (x) ZG (x).
- FIGS. 23 (A) and (B) are explanatory diagrams of the operation of the GRC arithmetic unit 32B and the 32-bit shift unit 33B, respectively.
- the CRC arithmetic unit 32B sequentially stores X39 to ⁇ 32 at 8 clocks from the primary side. type, the contents of the input is complete and Kino shift register SR X 32 is B (x) / G remainder RB of (x) (X).
- the 32-bit shift device 33B multiplies the transformation matrix A32 by the 16X1 matrix RB (X) and outputs the remainder RB '(X) of ⁇ 32 ⁇ ( X ) / G (x).
- Figures 24 (A) and (B) show the operation of the CRC calculator 32C and the 24-bit shifter 33C, respectively. It is an explanatory diagram of the operation.
- ⁇ 3 ⁇ to # 24 are sequentially input to the CRC operation device 32C in eight clocks from the higher-order side, the contents of the shift register SR when the input of X24 is completed are set to C.
- the 8-bit shift device 33C multiplies the transformation matrix A 24 by the 16X1 matrix Rc (x) and outputs the remainder Rc '(x) of xC (x) ZG (x).
- Figure 25 (A) Fig. B) is an operation explanatory diagram of the CRC arithmetic unit 32D and 16 bit Bok shift Bok apparatus 33D respectively, sequentially X 23 ⁇
- the CRC arithmetic unit 32D in 8 clock Ri by higher order side x 16 inputs, the remainder RD (X) of the contents of the shift register SR at the time of the input of ⁇ 6 is completed D (x) / G (x ).
- the 16-bit shift unit 33D multiplies the transformation matrix A by the matrix RD (X) of 16X1 and outputs the remainder RD '(X) of xi 6 D (x) / G (x).
- Figure 26 (A), (B) is an operation explanatory diagram of the CRC arithmetic unit 32E and 8-bit Toshifu winding device 33E respectively, sequentially X i 5 the CRC arithmetic unit 32E in 8 click lock higher order side ⁇ x 8 is input, the contents of the shift register SR when the input has been completed X 8 is E (x) / G (x ) D remainder RE (X). 8 bit Bok shift device 33E outputs a remainder RE '(X) of the multiplied transformation matrix A S and 16X1 matrix RE (X) and x 8 E (x) / G (x).
- Figure 27 is a diagram for describing the operation of CRC arithmetic unit 32F, Schiff when the CRC arithmetic unit 32F sequentially X 7 ⁇ is entered in 8 click Lock Repetitive by higher side, the input of chi o is completed
- the remainder of the register SR is F (x) / G (x), the remainder RF (X) Becomes
- FIG. 28 is an explanatory diagram of the operation of the combining section 34.
- the synthesizing unit 34 generates an EX- corresponding to the bits of the calculated remainders I '(x), RB' (X), RG '(X), RD' (X), RE '(X), and RF (X). Performs OR operation and outputs 16-bit CRC parity P '(X).
- the error detection unit 35 determines that there is no error if the CRC parity ⁇ '(X) has a total bit power of “0”, and determines that there is an error if there is at least one “ ⁇ ”.
- the conventional error detection encoder requires 32 clocks to generate parity.
- the required number of clocks is eight, so that the operation time is reduced to 1/4.
- the conventional error detection decoder using the coincidence detection decoding method requires 32 clocks.
- the encoder and the decoder of the present invention have a hardware scale of 4 times, 4 times and 6 times, respectively, in inverse proportion to the operation time. This is because the operations that were performed in series were performed in parallel. However, for example, when a CRC calculation is performed on an information rate of 100 Mbps with a clock of 25 MHz, the scale of one door is equal to that of the conventional example.
- Table 1 shows (1) the hardware scale of the error detection decoder, (2) the number of hardware required to perform the CRC operation on the information rate of 100 Mbps with a 25 MHz clock, and (3) the operation time. It becomes as shown in. From this, it can be seen that according to the present invention, the calculation time can be shortened without changing the total hardware scale.
- the error detection decoder has been described above, but the same applies to the error detection encoder.
- the initial value of the shift register SR in all the CRC calculation units 12A to 12D is set to "0".
- the data division unit (not shown) converts a 32-bit data string into 8-bit data strings.
- each CRC arithmetic unit input to each CRC arithmetic unit is divided into chi. 24 to chi 31.
- x si to x 24 are input from the high-order side in 8 clocks, and the calculation result (residual RA (X) of A (x) / G (x)) is is converted 24 bit Toshifu winding devices are 24 bit Toshifu preparative process in 13A to ⁇ 24 ⁇ ( ⁇ ) / G (x ) modulo RA of '(X).
- CRC arithmetic unit 12B shift ⁇ 23 ⁇ ⁇ ⁇ 6 in 8 clocks to registers is input from the high order side, the calculated result of (B (remainder RB of x) / G (x) ( X)) is 16-bit The data is converted into a remainder RB '(X) of x "B (x) / G (x) by 16-bit shift processing in the shifter 13B.
- CRC operation unit X to X8 are input from the high-order side in 8 clocks to the shift register of the 12C, and the calculation result (residue Rc (x) of C (x) / G (x)) It is converted to the remainder Rc (X) of the 8 bits Toshifu preparative treated with 8-bit Toshifu winding device 13C in x 8 C (x) / G (x).
- FIG. 31 is a configuration diagram of the error detection decoder according to the second embodiment, and the same parts as those in FIG. 15 are denoted by the same reference numerals.
- 32-bit CRC parity of 16 bits in the lower order side of the input data is appended to Bok
- the initial value of the shift register SR in all the CRC calculation units 22A to 22D is set to "0". Keep it.
- Data dividing unit (not shown) separates the data string of 48 bits in the lower order side 16-bit CRC Roh utility ⁇ 5 and higher side of the 32 input data one data ⁇ ⁇ 47 of bit Bok, further, 32-bit input data to 8 bits at a time of ⁇ 16 ⁇ 23, ⁇ 24 ⁇ 31, ⁇ 32 ⁇ 39, ⁇ 40
- CRC X ⁇ X 32 is to shift register of the arithmetic unit 22B at 8 clock inputs Ri by higher ⁇ , the CRC arithmetic unit 22B of the arithmetic result (B (x) / G ( x remainder RB of) (X) ) Is input to the 16-bit shift pad 23B, where it is converted to the remainder RB '(X) of x "B (x) / G (x) by 16-bit shift processing.
- x si to 4 are input from the high-order side to the shift register of the CRC operation device 22C in 8 clocks, and the operation result (C (x) / G (x) of the CRC operation device 22C is calculated.
- remainder RG (X)) is input to 8-bit Toshifu Bok device 23C, where it is converted is 8 bits Toshifu preparative process x 8 C (x) / G (x) of the retained surplus Rc (X).
- the above operations are performed simultaneously, and the combining unit 24 calculates the EX-OR of the remainders RA ′ (X), RB ′ (X), RC ′ (X), and RD (X) that are the result of these operations for each bit.
- the CRC parity P '(x) is output.
- the comparing unit 25 calculates the 16-bit CRC parity P '(x) and the CRC number added to the input data.
- Utility bits [rho (chi) detecting errors by ( ⁇ 5 ⁇ ⁇ ⁇ ) and every bit Bok and the EX-OR connexion addition (logical OR).
- the CRC parity bit ⁇ '( ⁇ ), which is the operation result, and the GRC parity bit ⁇ ( ⁇ ) added to the input data are all equal, and if there is no error, the comparator 25 outputs “0”, If there is an error, output '' ⁇ .
- FIG. 32 is a configuration diagram of an error detection decoder according to the third embodiment, and the same parts as those in FIG. 21 are denoted by the same reference numerals.
- the 16-bit CRC code is on the lower side of the 32-bit input data.
- the initial value of the shift register SR in all the CRC calculation devices 32A to 32F is set to "0".
- Data dividing unit 48 bits of de one data string 8 bits at a time of ⁇ 7, ⁇ 8 ⁇ 15, ⁇ 16 ⁇ 23 , ⁇ 24 ⁇ 31, ⁇ 32 ⁇ 39, ⁇ 40 ⁇ ⁇ 47 And input to each CRC calculation device.
- CRC arithmetic unit 32A of the operation result (A (x) / G ( x) modulo RA of (X) ) is 40-bit input to Toshi oice device 33A, is where 40-bit Toshifu preparative process x 4.
- a (x) is converted to the remainder RA '(X) of G (x).
- Bok register CRC arithmetic unit 32F is 8 clock at ⁇ 7 ⁇ enter Ri by higher side, F (x) / G remainder of RF (x) (X) is calculated.
- the above operations are performed simultaneously, and the combining unit 34 calculates the residuals RA ′ (X), RB ′ (X), RC ′ (X), RD ′ (X), RE ′ (X), RF ( X) is EX-ORed for each bit, and a 16-bit CRC parity P '(x) is output.
- the error detection unit 35 calculates the OR of all the bits of P' (x). If all bits of the CRC noise F (x) are "0", there is no error, and the error detection unit 35 outputs "0". However, if at least one is "1", there is an error, and the error detection unit 35 outputs "".
- FIG. 33 is another configuration diagram of the error detection decoder of the fourth embodiment, and the decoding method is the same as the decoding method of FIG.
- the error detection decoder in FIG. 33 includes four CRC calculation devices 42A and 42D.
- the input data division control unit 41 determines the bit length to be input to each CRG arithmetic unit 42A 42D.
- the input data division control unit 41 For example, if the CRC error detection coding bit length is 40 bits including CRC parity, the input data division control unit 41
- the CRC calculation units 42 ⁇ , 42 ⁇ , 42C, and 42D input them to the CRC calculation units 42 ⁇ , 42 ⁇ , 42C, and 42D together with the number of input bits (number of operations) 10. Further, the input data dividing unit 41 inputs the bit shift amount to each shift converter 43 ⁇ , 43 43, 43C. In the above IB example, 30-bit shift is instructed to shift converter 43A, 20-bit shift is instructed to shift converter 43B, and 10-bit shift is instructed to shift converter 43C. As described above, the CRC arithmetic units 42A, 42B, 42C, and 42D store the contents of the shift register at the time when the data of the indicated number of bits is input, with the remainder RA (X), RB (X), RC ( X) and RD (X) are output.
- the shift converter 43A performs a 30-bit shift process on the input remainder RA (X) to convert it into a remainder i ′ (x), and the shift converter 43B converts the input remainder RB (X) into an input remainder RB (X). Performs a 20-bit shift process to convert to a remainder RB '(X), and shift converter 43C performs a 10-bit shift process on the input remainder Rc (x) to convert to a remainder Rc' (x).
- the combining unit 44 combines the remainders R A '(x), RB' (X), RC '(X), and RD (X) by performing an EX-OR operation for each bit and combining all bits with "0". Error detection is performed based on whether or not ".
- the input data division control unit 41 divides the input data by 13, 13, 12, and 12 bits x49 y48 y47. ⁇ 38 ⁇ 37
- the input data division control unit 41 inputs the bit shift amount to each of the shift converters 43 ⁇ , 43 ⁇ , and 43C.
- 37-bit shift is instructed to shift converter 43 #
- 24-bit shift is instructed to shift converter 43 #
- 12-bit shift is instructed to shift converter 43C.
- the CRC arithmetic units 42A, 42B, 42C, and 42D store the contents of the shift register at the time when the data of the indicated number of bits is input, with the remainder RA (X), RB (X), RC ( X) and RD (X) are output.
- the shift converter 43A performs a 37-bit shift process on the input remainder RA (X) to convert it to a remainder RA '(X), and the shift converter 43B outputs a 24-bit shift to the input remainder RB (X).
- the shift converting device 43C performs a to-shift process to convert the input remainder Rc (x) into a remainder Rc '(x) by performing a 12-bit shift process on the input remainder Rc (x).
- the synthesizing unit 44 synthesizes the remainders RA '(X), RB' (X), RC '(X), and RD (X) by performing an EX-OR operation for each bit and checking whether all bits are 0 " Error detection is performed based on whether or not it is not.
- the calculation time of each CRC calculation device can be made uniform, so that the CRC calculation time can be reduced.
- the idea of dividing the input data sequence into approximately 1 / n equally can be applied to the error detection decoder in FIG. 15 and the error detection encoder in FIG. That is, for the data divisions 11 and 21 in FIGS. 1 and 15, the input data sequence is divided so that the bit length of the divided data sequence is equal, and each divided data sequence is 1 bit from the higher side. Input to the CRC calculation device (division means).
- FIG. 34 is another block diagram of the error detection decoder of the fifth embodiment, and the decoding method is the same as the decoding method of FIG. In the error detection decoder,
- the maximum CRC error detection coding bit length is 60 bits
- the shift converters 53A to 53C perform 45-bit shift processing, 30-bit shift processing, and 15-bit shift processing, respectively.
- the input data division control part 51 divides these 40 bits into 15 bits from the lower order side, and sequentially performs CRC calculation.
- Device 52D input to CRC operation device 52C, input the remaining 10 bits to CRC operation device 52B, and do not input to CRC operation device A. That is, the input data division unit 51 does not input data to the CRC operation device 52A, and inputs the data to the CRC operation devices 52B ; 52C and 52D, respectively.
- the input data division unit 51 inputs the number of input bits (the number of operations) 0, 10, 15, 15 to each of the CRC operation devices 52A, 52B, 52C, 52D.
- the device 53B performs a 30-bit shift process on the input remainder RB (X) and
- the 15-bit shift converter 53C converts the input remainder Rc (x) into a remainder Rc '(x) by performing a 15-bit shift process.
- the combining unit 54 combines the remainders RA '(X), RB' (X), RG '(X), and RD (X) by performing an EX-OR operation for each bit, and determines whether all bits are 0 ". Error detection is performed according to the above.
- the input data division control unit 51 outputs the input data from the lower-order side to 15, 15, 15, 5 And divided into CRC calculation units 52A, 52B, 52C, and 52D, respectively.
- the input data division control unit 51 inputs the number of input bits (number of operations) 5, 15, 15, 15 to each of the CRC operation devices 52A, 52B, 52C, 52D.
- the CRC operation devices 52A, 52B, 52C, and 52D store the contents of the shift register at the time when the data of the designated number of bits is input, with the remainder I (x), RB (X), and RC (X ), Output as RD (X).
- the 45-bit shift converter 53A performs a 45-bit shift process on the input remainder I (x) to convert it to a remainder RA '(X)
- the 30-bit shift converter 53B outputs the input remainder RB (X ) Is converted to a remainder RB '(X) by 30-bit shift processing
- the 15-bit shift converter 53C performs 15-bit shift processing on the input remainder Rc (x) to generate a remainder Rc' (x).
- the combining unit 54 combines the remainders R A '(x), RB' (X), RC '(X), and RD (X) by performing an EX-OR operation for each bit and obtaining a total bit power of 0 ". Error detection is performed depending on whether or not there is.
- each bit shift converter since each bit shift converter only needs to always perform a fixed number of bit shift processes, the configuration can be simplified.
- FIG. 35 is another configuration diagram of the error detection decoder of the sixth embodiment, and the decoding method is the same as the decoding method of FIG. In the error detection decoder,
- the maximum CRC error detection coding bit length is 60 bits
- the maximum number of input bits to each of the CRC calculation units 62A to 62D is 15 bits.
- the shift converters 63A to 63C perform 45-bit shift processing, 30-bit shift processing, and 15-bit shift processing, respectively.
- the input data division control unit 61 divides the 40 bits into 15 bits from the lower order side, and sequentially performs CRC calculation. Input to the device 62D and CRC calculation device 62C. For devices with less than 15 bits, insert "0" on the higher order side and input a total of 15 bits. Therefore, the input data division control unit 61 sends the data to the CRC operation units 62A, 62B, 62C, and 62D respectively.
- the device 63B performs a 30-bit shift process on the input remainder RB (X) to convert it to a remainder RB '(X), and the 15-bit shift converter 63C performs a 15-bit shift on the input remainder Rc (x). Perform processing and convert to remainder Rc '(x).
- the combining unit 64 combines the remainders RA '(X), RB' (X), RC '(X), and RD (X) by performing an EX-OR operation for each bit, and determines whether the total bit power is 0 ". Erroneous detection is performed depending on whether or not.
- the input data division control unit 61 divides the input data into 15, 15, 15, and 5 parts from the low-order side, and performs CRC calculation.
- Apparatus 62A, 62B, 62C, 62D respectively
- the CRC calculation units 62 ⁇ , 62B, 62C, and 62D store the contents of the shift register at the time when the 15-bit data is input as the remainder I (x), RB (X), RC (X), RD Output as (X). Also, the 45-bit shift converter 63A performs 45-bit shift processing on the input remainder RA (X) to convert it to a remainder RA '(X), and the 30-bit shift converter 63B outputs the input remainder RB (X).
- X> is converted to a remainder RB '(X) by performing a 30-bit shift process, and the 15-bit shift converter 63C performs a 15-bit shift process on the input remainder Rc (x) to perform a remainder RG'
- the combining unit 64 combines the remainders I '(x), RB' (X), RG '(X), and RD (X) by performing an EX-OR operation for each bit and combining them. Error detection is performed based on whether or not it is Toka 0.
- the configuration can be simplified. Since the shift converter only needs to always perform a certain number of bit shift processes, the configuration can be further simplified.
- FIG. 36 is a configuration diagram of the error detection decoder of the seventh embodiment, and the same parts as those of the error detection decoder of FIG. 31 are denoted by the same reference numerals. The difference is that the storage devices 26A to 26D for storing the remainders RA '(X), RB' (X), RC '(X), and RD (X) obtained by the bit shift process are provided. (2) The remainder is calculated again only for the 8-bit divided data re-input by error detection, and the remainder is combined with the remaining remainder of the divided data to generate a CRC parity. Is output.
- the first error detection is performed in the same manner as in FIG. 31, but if an error is detected and the data is partially re-input, the error is re-input.
- the remainder is calculated again only for the divided data of 8 bits, and the remainder is combined with the remainder of other stored divided data to output CRC parity.
- Data dividing unit (not shown) separates the data string of 48 bits in the input data ⁇ 6 ⁇ ⁇ 47 of 32-bit CRC parity Kaishita ⁇ chi 5 and higher side of the lower-order side 16 bits, further, 32-bit ⁇ 6 ⁇ of 8 bits at a time the input data of Bok ⁇ 23, ⁇ 24 ⁇ ⁇ 31, ⁇ 32
- 1-9 is divided into ⁇ 4 ⁇ 47 input to each CRC arithmetic unit. 22A to 22D.
- x "to x « are input from the higher order side in eight clocks, and the operation result of the CRC operation unit 22A (the remainder R A of A (x) / G (x) (x)) is input to the 24-bit shift unit 23A, where it is subjected to 24-bit shift processing, converted to the remainder I '(X) of x «A (x) / G (x), and stored in the storage unit. It is recorded on 26A.
- CRC remainder RB arithmetic device X ⁇ X 32 is the shift register in 8 clock inputs Ri by higher order side 22B
- the CRC arithmetic unit 22B of the arithmetic result (B (x) / G ( x) (X)) is input to 16-bit Bok shift device 23B, and converted where 16-bit Toshifu preparative processed by the remainder RB '(X) of ⁇ 6 ⁇ ( ⁇ ) / G (x), a storage device 26B Is stored.
- the shift register of the CRC arithmetic unit 22 C 8 black Tsu x 3 i ⁇ x 24 is high ⁇ Ri by side input using the clock
- the CRC arithmetic unit 22C of the operation result (C (x) / G ( x) remainder Rc (x)) is 8 input to bit Toshifu winding device 23C, where it is 8 bit Toshifu preparative process is converted into x 8 C (x) / G (x retained surplus Rc'G of)), storage Stored in device 26C.
- the synthesizing unit 24 calculates the remainders R A '(x), RB' (X), RG '(X), and RD (X), which are the result of the operation, EXOR And outputs the CRC parity bit P '(x). Comparing unit 25, this CRC Bruno utility bits P '(x), the CRC bits Tobi' preparative ⁇ ( ⁇ ) ( ⁇ 5 ⁇ ⁇ ⁇ ) and EX-OR the each bit added to the input data Then, an error is detected by adding (OR).
- the comparator 25 If the parity bit P '(x) and the CRC parity bit P (x) added to the input data are all equal and there is no error, the comparator 25 outputs “0”, and if there is an error, the comparator 25 outputs “0”. and outputs the gamma.
- CRC arithmetic unit 22B of the shift register only 8 click lock with 8-bit data x 39 ⁇ x 32 Is input again, and the operation result (remainder RB (X) of B (x) / G (x)) of the CRC operation device 22B is input to the 16-bit shift device 23B, where it is shifted by 16 bits to ⁇ 6 ⁇ ( ⁇ ) Converted to the remainder RB '(X) of / G (x).
- the synthesizing unit 24 reads the remainders RA '(X), RG' (X), and RD (X) stored in the storage devices 26A, 26C, and 26D, and outputs these to the 16-bit shift circuit 23B.
- the result RB '(X) obtained by processing is XORed bit by bit.
- Comparing section 25 includes a CRC parity P of the 16-bit '(x>, CRC bits added to the input data: ⁇ ( ⁇ ) ( ⁇ 5 ⁇ ) and every bit Bok EX- OR An error is detected by adding (logical sum) using.
- FIG. 37 (A) is a block diagram of the entire system
- FIG. 37 (B) is an explanatory diagram of data processing.
- the transmitting side 101 performs L2 layer CRC error detection coding on the entire information. Then, the error detection coded data (data with CRC parity of the L2 layer) is divided into a to d, and the divided data is subjected to L1 layer CRC error detection coding, and finally the error correction code And send it.
- the receiving side 102 divides the decoded data into a plurality of A to D, and performs L1 layer CRC error detection processing on each of the divided data.
- L1 layer CRC error detection processing if it is determined that no error is detected, performing CRC error detection processing of the L2 layer is inefficient because the calculation is divided into two. Therefore, error detection processing in both the L1 and L2 layers is performed simultaneously.
- the CRC error detection processing in the L2 layer is wasted, Even if only the wrong part of one layer is retransmitted, the same operation is performed from the beginning.
- the method of the seventh embodiment is applied.
- the CRC calculation unit of L1 layer error detection is Make the length the same, save the calculation result, and calculate only that part if the data is partially retransmitted. In this way, efficient CRC error detection of the L2 layer can be performed. Since the processing of the higher layer of the L2 layer or higher is often performed by software, it is preferable to obtain a result by a partial operation because the processing efficiency of the processor is improved.
- FIG. 38 is a configuration diagram of an error detection decoder as an application example of the seventh embodiment.
- the input data division control unit 71 divides the input data sequence into L1 layer CRC operation units A to D (see FIG. 37 (B)) and inputs each to the LI CRC error detection devices 72A to 72D.
- the L2 CRC error detection device 70 inputs the CRC calculation devices 74A to 74D.
- the Ll CRC error detection devices 72A to 72D and the L2 CRC error detection device 70 simultaneously perform error detection processing.
- the Ll CRC error detectors 72A to 72D perform CRC calculations on the divided data strings A to D, and output the calculation results.
- the CRC monitoring unit 73 monitors the presence or absence of an error in the L1 layer based on the error detection results of the Ll CRC error detection devices 72A to 72D, and if there is no error, inputs a synthesis enable signal to the synthesis unit of the L2 CRC error detection device 70. I do.
- the CRC calculation devices 74A to 74D of the L2 CRC error detection device 70 output the remainder obtained by dividing the data portion excluding the L1 CRC parity included in the input data sequences A to D by the generator polynomial.
- the shift converters 75A to 75C perform bit-shift processing on the remainders obtained by the CRC calculators 74A to 74C for the bit shifts corresponding to the division positions of the data A to C columns, and convert them. Save to ⁇ 76D.
- the combining unit 77 combines the remainders stored in the storage units 76A to 76D based on the combining permission signal from the CRC monitoring unit 73 (EX-OR operation for each bit), and the error detection unit 78 combines Based on the result, L2 layer CRC error detection is performed.
- the CRC monitoring unit 73 requests the transmission side to retransmit the erroneous data portion. For example, if the data string B contains an error, a request is made to retransmit the data string B.
- the input data division control unit 71 inputs the data to the Ll CRC detection device 72B and the CRC calculation device 74B of the L2 CRC error detection device 70 if the data column B is retransmitted.
- the Ll CRC error detection device 72B performs a CRC operation on the divided data sequence B and outputs the operation result.
- the CRC monitor 73 detects the error of the Ll CRC error detector 72A to 72D. Based on the result, the presence / absence of an error in the L1 layer is monitored, and if there is no error, the synthesizing unit 77 is permitted to synthesize.
- the CRC operation unit 74B outputs the remainder obtained by dividing the data portion excluding the L1 CRC parity included in the input data B by the generator polynomial, and the shift conversion unit 75B splits the data B
- the remainder obtained by the CRC operation unit 74B for the bit shift corresponding to the position is subjected to bit shift processing, converted, and stored in the storage unit 76B.
- the combining unit 77 combines the remainders stored in the storage units 76A to 76D (EX-OR operation for each bit) based on the permission signal from the CRC monitoring unit 73, and the error detection unit 78 Performs L2 layer GRC error detection based on
- FIG. 39 is another block diagram of the error detection decoder of the eighth embodiment, which can be applied in the system configuration shown in FIG. 37 (A) in which CRC is doubled, and FIG. 40 is a diagram for explaining data processing. .
- the error detection encoder side performs L2 layer CRC error detection coding on the entire 112-bit information and adds a 16-bit L2 CRC noise.
- the 128-bit data (data with L2 CRC parity) coded by error detection is divided into a plurality of 32-bit data strings A to D, and each divided data string A to D is divided into 16-bit data strings. LI CRC parity is added to the data, and error correction coding is performed at the end, and the data is transmitted.
- the LI CRC calculation unit 80 (Fig. 39) provided on the receiving side performs L1 CRC calculation by the match detection decoding method. Note that the LI CRC calculation unit 80 can use any decoding method such as the all- "0" detection decoding method or the decoding method of the present invention. Also, the L2 CRC calculation unit 90 performs the L2 CRC calculation by the decoding method shown in FIG.
- the LI CRC operation unit 80 first performs the first LI CRC operation. That is, data A 32bit ( ⁇ 191, ⁇ 190; ⁇ 189;.. ⁇ 188> ⁇ , ⁇ 161, ⁇ 160) the input to the shift register SR of the divider 81.
- the error detection unit 82 off Bok register value of SR (the remainder RA (X)) and LI CRC Bruno literals I (X159, ⁇ 158, ⁇ 157 ; x i 5e,... ) X 5 ; x i44), and performs LI CRC error detection based on whether all bits match.
- the value of the shift register (remainder RA (X)) is passed to the L2 CRC operation unit 90.
- the L2 CRC operation unit 90 stores this value by controlling the switch 91. Store in device 92A.
- the LI CRC calculation unit 80 clears the shift register SR and performs the next LI CRC calculation. That is, the data B of 32Tbit (x "3, x" 2, x i 4i, x "o,..., X iis, ⁇ ⁇ 2) the input to the shift register SR.
- the error detection unit 82 calculates the value of the shift register SR (remainder RB (X)) and the LI CRC number ( x m, X no ;
- X 109, X 108,.. ⁇ , X 97 compared with the chi 96>, performs L 1 CRC error detected on whether they match all bits.
- the value of the shift register (remainder RB (X)) is passed to the L2 CRC operation unit 90.
- the L2 CRC operation unit 90 stores this value in the storage device 92B by controlling the switch 91.
- the LI CRC calculation unit 80 clears the shift register SR and performs the next LI CRC calculation. That, 32bit data ⁇ ( ⁇ 95, ⁇ , 3 , 2,.. ⁇ , ⁇ 65, the inputs to the shift register SR.
- the error detection unit 82 shift the value of bets register SR (the remainder Rc (x)) and the LI CRC parity (xss, x es; x si , X 60, ⁇ ⁇ ⁇ , X 49, ⁇ 48) and comparing the match or all bits L] CRC error detection is performed based on whether or not, and at the same time, the value of the shift register (remainder Rc (x)) is delivered to the L2 CRC calculation unit 90.
- the L2 CC calculation unit 90 controls the switch 91. Then, this value is stored in the storage device 92C.
- the LI CRC calculation unit 80 clears the shift register SR and performs the next LI CRC calculation. That, 32bit data ⁇ ( ⁇ 47, ⁇ 46, ⁇ 45 , ⁇ 44, ⁇ .., X 17, ⁇ 16) is input to shift register SR.
- the error detection unit 82 calculates the value of the shift register SR (remainder RD (X)) and the LI CRC value. Utility (xs, x i 4; x Interview 3, x 12, ⁇ ⁇ ⁇ , ⁇ , ⁇ ) and compares, in whether they match all bits; performing LI CRG error discovery.
- the value of the shift register (remainder RD (X)) is passed to the L2 CRC calculation unit 90.
- the L2 CRC operation unit 90 controls the switch 91 to store this value in the storage device 92D.
- the L2 CRC calculation unit 90 starts the L2 CRC calculation. That is, the 96-bit shift unit 93A reads the storage data (remainder RA (X)) from the storage device 92A and performs a 96-bit shift process on the remainder.
- the 64-bit shift unit 93B reads the storage data (remainder RB (X)) from the storage device 92B and adds the 64-bit shift to the remainder. Perform processing.
- the 32-bit shift unit 93C reads the stored data (remainder Rc (x)) from the storage device 92C, and performs a 32-bit shift process on the remainder.
- LI CRC arithmetic unit 80 is serially remainder RA (X), R B ( X), RC (X), but calculates the RD (X), by sea urchin input data divided as shown in FIG. 41 part 83 and provided four LI CRC arithmetic unit 80a to 80d, the remainder RA (X) performs LI CRC check on each, R B (X), Rc (x), to compute the RD (X) It can also be configured.
- the LI CRC calculation units 80A to 80D have the same configuration as the LI CRC calculation unit 80 in FIG.
- the shift register operation of the L2 CRC operation unit can be eliminated, and the hardware configuration can be simplified.
- the error detection encoder in FIG. 1 treats the K-bit input data sequence as it is as the first polynomial KG, and the second polynomial (generation polynomial) G (x)), and can be used as a divider for calculating the remainder.
- the division device divides the input data sequence into a plurality of data by the second polynomial, assuming that the information bits of the sub-data sequence are polynomials for each divided sub-data sequence.
- Dividing means 12A to 12D for calculating the remainder, and 3) converting means 13A to 13 for performing a conversion process (bit shift process) according to the division position of the sub data sequence for each of the remainders.
- a combining unit 14 that combines the converted values obtained by the above and sets the combined result to the remainder obtained by dividing the K-bit input data sequence by the second polynomial. Can be.
- Such a division device is not limited to an error detection encoder and can be used in various encodings.
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- Physics & Mathematics (AREA)
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- Detection And Correction Of Errors (AREA)
Description
Claims
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
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DE60236896T DE60236896D1 (de) | 2002-04-22 | 2002-04-22 | Fehlerdetektionscodierer und -decodierer |
EP10150593A EP2175559A1 (en) | 2002-04-22 | 2002-04-22 | Error-detecting decoder with re-calculation of a remainder upon partial re-transmission of a data string. |
EP02720542A EP1499024B1 (en) | 2002-04-22 | 2002-04-22 | Error-detection encoder and decoder |
JP2003587014A JP3930479B2 (ja) | 2002-04-22 | 2002-04-22 | 誤り検出符号化及び復号装置並びに除算装置 |
PCT/JP2002/003965 WO2003090362A1 (fr) | 2002-04-22 | 2002-04-22 | Codeur et decodeur de detection d'erreur, et diviseur |
US10/970,859 US7428693B2 (en) | 2002-04-22 | 2004-10-20 | Error-detecting encoding and decoding apparatus and dividing apparatus |
Applications Claiming Priority (1)
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PCT/JP2002/003965 WO2003090362A1 (fr) | 2002-04-22 | 2002-04-22 | Codeur et decodeur de detection d'erreur, et diviseur |
Related Child Applications (1)
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US10/970,859 Continuation US7428693B2 (en) | 2002-04-22 | 2004-10-20 | Error-detecting encoding and decoding apparatus and dividing apparatus |
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WO2003090362A1 true WO2003090362A1 (fr) | 2003-10-30 |
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ID=29227609
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PCT/JP2002/003965 WO2003090362A1 (fr) | 2002-04-22 | 2002-04-22 | Codeur et decodeur de detection d'erreur, et diviseur |
Country Status (5)
Country | Link |
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US (1) | US7428693B2 (ja) |
EP (2) | EP1499024B1 (ja) |
JP (1) | JP3930479B2 (ja) |
DE (1) | DE60236896D1 (ja) |
WO (1) | WO2003090362A1 (ja) |
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WO2009025221A1 (ja) * | 2007-08-17 | 2009-02-26 | Ntt Docomo, Inc. | データ送信方法、データ受信方法、移動端末及び無線通信システム |
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JP2008005419A (ja) * | 2006-06-26 | 2008-01-10 | Alaxala Networks Corp | 情報処理装置および情報処理方法 |
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WO2008023684A1 (fr) * | 2006-08-22 | 2008-02-28 | Panasonic Corporation | Unité d'opération arithmétique de résidus en parallèle et procédé d'opération arithmétique de résidus en parallèle |
JPWO2008023684A1 (ja) * | 2006-08-22 | 2010-01-14 | パナソニック株式会社 | 並列剰余演算器及び並列剰余演算方法 |
US8700971B2 (en) | 2006-08-22 | 2014-04-15 | Panasonic Corporation | Parallel residue arithmetic operation unit and parallel residue arithmetic operating method |
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US8689078B2 (en) | 2007-07-13 | 2014-04-01 | Intel Corporation | Determining a message residue |
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Also Published As
Publication number | Publication date |
---|---|
JP3930479B2 (ja) | 2007-06-13 |
EP1499024A1 (en) | 2005-01-19 |
DE60236896D1 (de) | 2010-08-12 |
EP1499024A4 (en) | 2007-05-23 |
US20050097432A1 (en) | 2005-05-05 |
EP2175559A1 (en) | 2010-04-14 |
JPWO2003090362A1 (ja) | 2005-08-25 |
EP1499024B1 (en) | 2010-06-30 |
US7428693B2 (en) | 2008-09-23 |
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