WO2003065455A1 - Circuit integre a semi-conducteurs - Google Patents

Circuit integre a semi-conducteurs Download PDF

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Publication number
WO2003065455A1
WO2003065455A1 PCT/JP2002/000742 JP0200742W WO03065455A1 WO 2003065455 A1 WO2003065455 A1 WO 2003065455A1 JP 0200742 W JP0200742 W JP 0200742W WO 03065455 A1 WO03065455 A1 WO 03065455A1
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WO
WIPO (PCT)
Prior art keywords
circuit
output
pad
signal
logic circuit
Prior art date
Application number
PCT/JP2002/000742
Other languages
English (en)
Japanese (ja)
Inventor
Yoshikazu Saitoh
Kenichi Osada
Takehiko Kijima
Naoki Kitai
Original Assignee
Renesas Technology Corp.
Hitachi Ulsi Systems Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp., Hitachi Ulsi Systems Co., Ltd. filed Critical Renesas Technology Corp.
Priority to PCT/JP2002/000742 priority Critical patent/WO2003065455A1/fr
Priority to JP2003564938A priority patent/JPWO2003065455A1/ja
Priority to TW091105866A priority patent/TW594973B/zh
Publication of WO2003065455A1 publication Critical patent/WO2003065455A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/105—Aspects related to pads, pins or terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires

Definitions

  • the present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit including an input buffer and an output buffer.
  • the first method for determining the function by changing the signal level supplied to the predetermined terminal of the semiconductor integrated circuit on the substrate on which the semiconductor integrated circuit is mounted according to the setting information such as the mode register, after assembly The second method for determining the function using an electrical fuse in the test process, the third method for determining the function by bonding option during assembly, and the fourth method for determining the function using fuses etc.
  • the functions determined by the above option function selection include the input threshold value in the input buffer, the rising / falling (tr / tf) characteristics of the output waveform in the output buffer, operating power supply voltage, package, capacitance, bit Width, and function (truth table, state transition diagram).
  • the third method is effective as a relatively easy and simple method.
  • inventory management of the wafer process plant is managed in wafer state after completion of the test.
  • wafer inventory is determined for each function determined by the fuse state. It becomes difficult to keep up with market changes.
  • the fifth method is widely used because it can change specifications with a high degree of functionality and flexibility. Compared to the first method and the fourth method, the fifth method is an optional function. The decision process is earlier in the production process, and there is a need to have wafer inventory as in the fourth method above.
  • function selection by option is effective to respond quickly to specification changes in a semiconductor integrated circuit.
  • the function selection circuit for each option increases.
  • the pad size for bonding increases as the number of options increases, thereby inhibiting the reduction of the chip size of the semiconductor integrated circuit.
  • options other than bonding such as a fuse circuit, are used.
  • the output circuit has a function of externally outputting data read from the memory cell array in the semiconductor memory device, but a relatively large number of control signals are used to control the operation thereof.
  • control signals are generated in relation to other timing signals in a control circuit that generates various timing signals for internal operation of the semiconductor memory device. Since this control circuit generates various timing signals for the internal operation of the semiconductor memory device, it is desirable to arrange the control circuit closer to the center of the semiconductor chip than to arrange it at the edge of the semiconductor chip.
  • the control circuit is usually formed at a position away from the signal output pad for externally outputting read data from the memory cell array.
  • the signal line for controlling the operation must be routed to the vicinity of the external terminal, and the wiring becomes complicated ( and so on).
  • the signal wiring for transmitting the output signal from the output circuit to the signal output pad is routed inside the semiconductor chip.
  • the signal wiring for transmitting the output signal to the signal output pad is not Since a relatively large current flows, it is not preferable to route such a signal wiring to the inside of the semiconductor chip because it causes noise in other internal circuits.
  • An object of the present invention is to provide a technique for reducing the scale of a function selection circuit.
  • Another object of the present invention is to provide a technique for reducing an undesired current flowing in a transistor exhibiting GIDL characteristics.
  • Another object of the present invention is to provide a technique for optimizing the layout of an output circuit for externally outputting data read from a memory cell array.
  • a semiconductor integrated circuit is configured with a controller capable of changing the logical threshold value in the input buffer.
  • the controller determines the rising and falling characteristics of the signal waveform output from the output buffer and the logic in the input buffer accordingly. Change the threshold. For this reason, it is not necessary to form a function selection circuit for each function to be selected. This reduces the scale of the function selection circuit.
  • a step-down circuit for stepping down the input power supply voltage to a predetermined level, a first logic circuit that operates when the power supply voltage is supplied, and a stage subsequent to the first logic circuit, are provided from the step-down circuit.
  • a semiconductor integrated circuit having a second logic circuit that operates when the output voltage is supplied and a coupling circuit that couples the first logic circuit and the second logic circuit.
  • the coupling circuit includes the depletion type first transistor. The depletion-type first transistor lowers the voltage level of the signal input to the second circuit, and in the transistor included in the second circuit, a potential having a polarity opposite to the potential for turning on the channel is gated. It works to avoid being applied between the sources.
  • a semiconductor integrated circuit including a memory cell array in which a plurality of memory cells are arranged in an array and an output circuit for outputting data read from the memory cell array to the outside, An output buffer for outputting, and an output driver arranged to face the output buffer via the memory cell array and for driving the output buffer based on a data read from the memory cell array.
  • the output circuit is configured.
  • the output buffer and the output driver are coupled via a signal wiring formed using the upper layer of the portion where the memory cell array is formed. This avoids complication of signal wiring and suppresses noise generation in other circuits, thereby achieving optimization of the output circuit layout.
  • FIG. 1 is a block diagram showing a configuration example of a semiconductor memory device which is an embodiment of a semiconductor integrated circuit according to the present invention.
  • FIG. 2, c 3 FIG is a configuration example illustrating the main part of the semiconductor memory device is another configuration example illustration of a main part of the semiconductor memory device.
  • FIG. 4 is a circuit diagram of a configuration example of an electrostatic breakdown protection element included in the semiconductor memory device.
  • FIG. 5 is a circuit diagram of another configuration example of the electrostatic breakdown protection element included in the semiconductor memory device.
  • FIG. 6 is a circuit diagram of another configuration example of the electrostatic breakdown protection element included in the semiconductor memory device.
  • FIG. 7 is an explanatory diagram of another configuration example of the main part in the semiconductor memory device.
  • FIG. 8 is an explanatory diagram of another configuration example of the main part of the semiconductor memory device.
  • FIG. 9 is an explanatory diagram of another configuration example of the main part in the semiconductor memory device.
  • FIG. 10 is an explanatory diagram of another configuration example of the main part in the semiconductor memory device.
  • FIG. 11 is an explanatory diagram of another configuration example of the main part in the semiconductor memory device.
  • FIG. 12 is an explanatory diagram of another configuration example of the main part of the semiconductor memory device.
  • FIG. 13 is a circuit diagram of a basic configuration example of an input buffer included in the semiconductor memory device.
  • FIG. 14 is a circuit diagram of a configuration example of a circuit to be compared with the input buffer shown in FIG.
  • FIG. 15 is an explanatory diagram of the GIDL characteristics of the MOS transistor.
  • FIG. 16 is a circuit diagram showing another basic configuration example of the input buffer included in the semiconductor memory device.
  • FIG. 17 is a waveform diagram for explaining the operation of the input buffer.
  • FIG. 18 is a circuit diagram of a configuration example of an input buffer included in the semiconductor memory device.
  • FIG. 19 is a circuit diagram showing a detailed configuration example of the input buffer included in the semiconductor memory device.
  • FIG. 20 is a circuit diagram showing another configuration example of the input buffer included in the semiconductor memory device.
  • FIG. 21 is a circuit diagram showing another configuration example of the input buffer included in the semiconductor memory device.
  • FIG. 22 is a circuit diagram showing another configuration example of the input buffer included in the semiconductor memory device.
  • FIG. 23 is a characteristic diagram of an input buffer included in the semiconductor memory device.
  • FIG. 24 is a circuit diagram showing a configuration example of an output driver and an output buffer included in the semiconductor memory device.
  • the second Fig. 5, t second 6 Figure is a configuration example circuit diagram of a main part of the output driver is an operation example illustration of the output driver.
  • FIG. 27 is a circuit diagram showing a detailed configuration example of the main part of the output driver.
  • Figure 28 is a circuit diagram showing a detailed configuration example of the main part of the output driver.
  • FIG. 29 is a circuit diagram showing a detailed configuration example of the output buffer and its peripheral portion.
  • FIG. 30 shows the output driver and output cover in FIGS. 27 to 29. It is operation
  • FIG. 31 is an explanatory diagram of a layout example of the output driver and the output buffer in FIGS. 27 to 29.
  • FIG. 32 is a block diagram showing a configuration example of the step-down circuit included in the input buffer.
  • FIG. 33 is a circuit diagram showing a configuration example of a main part in the step-down circuit.
  • FIG. 34 is a circuit diagram showing another configuration example of the main part of the step-down circuit.
  • FIG. 35 is an explanatory diagram of an example of forming main elements used in the semiconductor memory device.
  • FIG. 36 is an explanatory diagram of a formation example of main elements used in the semiconductor memory device.
  • FIG. 37 is an explanatory diagram of a formation example of main elements used in the semiconductor memory device.
  • FIG. 38 is an explanatory diagram of a formation example of main elements used in the semiconductor memory device.
  • FIG. 39 is an explanatory diagram of the characteristics of the LV-CMOS interface used in the semiconductor memory device.
  • FIG. 40 is an explanatory diagram of the characteristics of the LV-T T interface used in the semiconductor memory device. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 1 shows a semiconductor memory device 10 which is an embodiment of a semiconductor integrated circuit according to the present invention.
  • the semiconductor memory device 10 of this embodiment is not particularly limited, but is formed as a semiconductor integrated circuit on one semiconductor substrate 9 such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique.
  • the semiconductor memory device 10 shown in FIG. 1 is not particularly limited, but four Memory cell arrays 28, 29, 30, and 31.
  • the memory cell arrays 28, 29, 30, and 31 are arranged so that a plurality of word lines and a plurality of pairs of data lines cross each other, and a plurality of static memory cells are arranged at the intersections. It is provided in an array.
  • the plurality of grid lines are driven to a selected level based on an output signal of a mouth address decoder (not shown) for decoding the mouth address.
  • a mouth address decoder not shown
  • the memory cell arrays 28, 29, 30, and 3 1 each include a data line selection circuit 32, 33, 34 for selectively coupling a plurality of data line pairs in the corresponding memory cell array to a common line pair. , 35 are combined.
  • the data line selection circuit 32, 33, 34, 35 performs the data line selection operation based on the output signal of the column address decoder that decodes the column address signal.
  • Sense amplifiers 36, 37, 38, 39 for amplifying the signal level of the corresponding common line pair are arranged in the vicinity of the delay line selection circuits 32, 33, 34, 35.
  • the common line pair is coupled to the output driver 42, and the signal amplified by the sense amplifiers 36, 37, 38, 39 is transmitted to the output driver 42 through the common line.
  • a pad 17 for outputting read data from the memory cell arrays 28, 29, 30, and 31 to the outside is provided on the edge of the semiconductor chip 9.
  • Pad 17 is connected to an external terminal (not shown) by a bonding wire.
  • the output signal from the output cover 43 is transmitted to the above-mentioned par 17.
  • the output buffer 43 is driven by the output driver 42. That is, the output buffer 4 3 is driven by the output driver 4 2 based on the data read from the memory cell arrays 2 8, 29, 3 0, 3 1. As a result, external output of read data from the memory cell arrays 28, 29, 30, 31 is possible.
  • the output driver 42 and the output buffer 43 driven by the output driver 42 are opposed to each other via the memory cell array 31.
  • the output signal from the output driver 42 is sent to the upper layer of the memory cell array 31. It is transmitted to the output buffer 43 through the formed metal wiring 52.
  • an electrostatic breakdown protection element 26 is arranged at the subsequent stage of the output driver 26.
  • a predetermined wiring resistance exists in the metal wiring 52 formed in the upper layer of the formation part of the memory cell array 31. However, this wiring resistance also causes the components of the output driver 42 to be destroyed by static electricity It helps to prevent.
  • a pad 16 for capturing input data for writing is formed at the edge of the semiconductor chip 9.
  • This pad 16 is bonded to an input terminal (not shown) for signal acquisition.
  • An input buffer 40 is coupled to the pad 16 via a metal wiring 53 formed in an upper layer of the memory cell array 30, and externally input write data passes through the metal wiring 53. Via the input buffer 40.
  • an electrostatic breakdown protection element 23 is disposed in the vicinity of the pad 16, and electrostatic breakdown is performed in the vicinity of the input buffer 40.
  • a protective element 24 is arranged.
  • the output signal from the input buffer 40 is transmitted to a write circuit (not shown) for writing data to the memory cell arrays 30 and 31.
  • a pad 15 for capturing input data for writing is formed on the edge of the semiconductor chip 9.
  • This pad 15 is bonded to an input terminal (not shown) for signal acquisition.
  • This pad 15 is connected to the input buffer 41 through the metal wiring 54 formed on the upper layer of the memory cell array 29, and the write data input from the outside is connected to the metal wiring. It is transmitted to the input buffer 4 1 via 5 4.
  • an electrostatic breakdown protection element 21 is disposed in the vicinity of the pad 15 and the electrostatic breakdown is in the vicinity of the input buffer 41. Protection element 2 2 is arranged.
  • the output signal from the input buffer 41 is transmitted to a write circuit (not shown) for writing data to the memory cell arrays 28 and 29.
  • the input buffers 40 and 41 and the output driver 42 are selectively activated by a chip select signal CSB output from the chip controller 46.
  • the input buffers 40 0 and 41 and the output driver 42 are activated while the chip select signal CSB is asserted low by the chip controller 46. It is like that.
  • the chip controller 46 is part of the function of a control circuit (not shown) for controlling the overall operation of the semiconductor memory device 10.
  • the input buffers 4 0 and 4 1 can change the logic threshold for the input signal by the control signal CTL.
  • the output driver 4 2 can output the rising and falling edges (tr / tf) The characteristic can be changed.
  • the control signal C T L is formed by the interface controller 45.
  • the output driver 4 2 and the output buffer 4 3 are collectively referred to as an output circuit and are usually arranged adjacent to each other.
  • this output circuit (output driver 42 and output cover 4 3) is provided at the formation position of output buffer 43 in FIG. 1, many signal lines coupled to output driver 42 are connected to It is necessary to wire up to the formation position of the output buffer 43 in FIG. 1, which is not preferable because wiring in the upper layer of the formation region of the memory cell array 31 becomes complicated.
  • the output circuit (output driver 4 2 and output buffer 4 3) is provided at the formation position of the output driver 4 2 in FIG. 1, the output signal of the output buffer 4 3 is transmitted.
  • the signal line is routed to the position of ESD protection element 27.
  • the output buffer 43 Since the output buffer 43 has a high driving capability and a relatively large current flows through the signal line for transmitting the output signal, it is easy to generate noise if such a signal line is routed in the semiconductor chip 9. Therefore, it is not preferable. Therefore, in this example, as shown in FIG. 1, the output driver 4 2 and the output buffer 4 3 are arranged to face each other via the memory cell array 3 1. In this way, the output driver 42 is arranged in the vicinity of the chip controller 45 and the chip controller 46 and the output buffer 43 is arranged in the vicinity of the pad 17. . In addition, in that case, the wiring in the upper layer of the formation region of the memory cell array 31 only needs to be a signal line for transmitting the output signal of the output driver 42 to the output buffer 43. It is possible to avoid complicated wiring in the upper layer of the formation site. In addition, since the drive capability of the output driver 42 is smaller than that of the output buffer 43, noise hardly occurs.
  • An interface controller 45 is provided, and this inverter controller 45 has a logic threshold value in the input buffers 40, 41. And the change of the waveform rising / falling (tr / tf) characteristics of the output signal in the output driver 42 according to the logic level of the common node signal given to the control line 55 by the bonding option. adjust. That is, a bonding option pad 13 is formed at one end of the semiconductor chip 9, and a bonding option pad 18 is formed at the other end of the semiconductor chip 9.
  • the logic level of the control line 55 is determined by coupling the node 18 to the high-potential side power supply VCC or ground GND (low-potential side power supply VSS) by the bonding option, the above input is selected according to the logic level.
  • the logic threshold values in the buffers 40 and 41 and the waveform rising / falling (tr / tf) characteristics of the output signal in the output driver 42 are determined.
  • the pad 14 formed in the vicinity of the bonding option pad 13 is used to take in the high potential side power supply VCC from the outside, and is formed in the vicinity of the bonding option pad 18.
  • Node 19 is used to capture the low potential power supply (ground GND) from the outside.
  • LV—CMO as a type of interface for semiconductor integrated circuits
  • the LV-CMO interface has the horizontal axis as the high-potential side power supply VC C and the vertical axis as the input voltage Vin.
  • Low level is guaranteed below 0.25 XV CC, and high level is guaranteed above 0.75 XV CC.
  • the difference 131 between the VCC / 2 line and the 0.25 XVCC line is the low level
  • the difference 132 between the VCC / 2 line and ⁇ .75 XVCC line is regarded as the noise margin on the high level side. As is apparent from FIG.
  • the noise margin 131 on the low level side and the noise margin 132 on the high level side are expanded as the level of the high potential side power supply V CC increases.
  • the output buffer can be driven at high speed.
  • the LV-TTL interface guarantees a low level when the input voltage Vin is 0.8 V or less, regardless of the fluctuation of the high-potential side power supply VCC. Since the high level is guaranteed when the input voltage Vin is 2.0 V or higher, the lower the high-side power supply VCC level, the lower the low-side noise margin 141 and the higher the high-side power supply VCC level. The higher the noise margin 142 on the high level side, the smaller. Therefore, when supplying a signal to a circuit employing such an LV-TTL interface, it is necessary to suppress noise contained in the output signal by driving the output buffer at a low speed.
  • the logic in the input buffers 40 and 41 is selected according to the bonding option so as to meet the interface specifications adopted in the user system to which the interface is applied. It is desirable to be able to adjust the threshold and the waveform rising / falling (tr / tf) characteristics of the output signal from the output buffer 43. Logic threshold in input buffers 40 and 41, and rising and falling of output signal waveform from output buffer 43 above (tr / tf) characteristics can be adjusted individually with separate bonding options, but this requires a function selection circuit for each option, so many pads are used for bonding options. Since it must be formed at the edge of the chip, it reduces the reduction of the chip size of the semiconductor integrated circuit.
  • the rising and falling characteristics of the signal waveform output from the output buffer 43 and the logic threshold values of the input buffers 40 and 41 are determined by the logic of the common node signal on the control line 55. It can be adjusted according to the level.
  • the logic level of the control line 55 is determined by bonding options, so that the rising and falling characteristics of the signal waveform output from the output buffer 43 and the logic threshold value in the input buffers 40 and 41 are determined. Is done. In this way, the function selection circuit can be made common by the bonding option, thereby reducing the scale of the function selection circuit.
  • FIG. 2 shows a main part of the semiconductor memory device 10 shown in FIG.
  • An optional pad 18 is formed.
  • the other end of the semiconductor chip 9 is formed with a pad 15 for data input and a pad 14 to which a low potential side power supply (ground GND) is supplied.
  • a pad 13 for bonding options is formed.
  • Pad 1 6 and external terminal 5 7 are connected by wire 6 3 by bonding, and pad 1 9 and external terminal 1 1 are connected by wire 6 2 by bonding.
  • Pin 1 5 and external terminal 5 8 are bonded. Are connected by wire 65, and pad 14 and external terminal 12 are Combined at 64.
  • the logic of the control line 55 is to be set to a high level by the bonding option, the external terminal 11 and the pad 18 are connected by the wire 61 by bonding. As a result, the logic of the control line 55 can be set to a high level.
  • the pad 18 for the bonding option is placed in the vicinity of the pad 19 for supplying the high-potential-side power source V CC, so that the bonding between the external terminal 11 and the pad 18 can be performed easily. .
  • you want to make the logic of the control line 55 low by the bonding option connect the external terminal 1 2 and pad 1 3 with bonding wire 6 6 as shown in Fig. 3. .
  • the logic of the control line 55 can be set to a single level. Bonding pad 13 is placed near pad 14 for supplying low potential power (ground GD), so bonding between external terminal 12 and pad 13 is easy. be able to.
  • the ESD protection elements 2 1 and 2 3 are not particularly limited, but the first protection circuit (ESDI) shown in Fig. 4 is adopted.
  • This first protection circuit (E SD 1) is placed in the downstream of the series circuit consisting of the npn bipolar transistor 67 and the pnp bipolar ⁇ range transistor 68. And a time constant circuit with a capacitance by an n-channel type MOS transistor 70.
  • the electrostatic breakdown protection elements 20 and 25 are not particularly limited, but a second protection circuit (ESD 2) as shown in FIG. 5 is adopted.
  • This second protection circuit (ESD 2) includes a resistance 7 1 and a time constant circuit with a capacitance by an n-channel type MOS transistor 72.
  • ESD 3) electrostatic breakdown protection circuit
  • a series circuit of a p-channel type MO S transistor 7 4 coupled to the potential side power supply VC C and a ⁇ -channel type MO S transistor ⁇ 5 coupled to the ground GND, and a resistor 73 for signal input are coupled. Made up. The detailed configuration of the input buffers 40 and 41 will be described.
  • Figure 13 shows the basic configuration of the input buffer.
  • the step-down circuit 81 generates an internal power supply VDD I having a lower level based on the input high potential side power supply VC C.
  • the internal power supply VDD is set to 1 and 2 V when the high potential side power supply V CC is set to 3.3 V.
  • the first logic circuit 10 0 1 that is operated by the supply of the high-potential-side power supply VC C and the second logic circuit 10 0 that is disposed at the subsequent stage and is operated by the supply of the internal power supply VDD I 2 is provided, and a ⁇ channel type MOS transistor 85 is provided as a coupling circuit for coupling the first logic circuit 1001 and the second logic circuit 102.
  • This ⁇ channel type MOS transistor 85 is a depletion type, and is turned on when the internal power supply VDDI is supplied to its gate electrode.
  • the first circuit 10 0 1 is an inverter composed of a ⁇ channel type MO S transistor 8 3 and a ⁇ channel type ⁇ OS transistor 84 connected in series, and the second logic circuit 1 0 2 is p
  • the channel type MOS transistor 86 and the n channel type MOS transistor 87 are connected in series.
  • the p-channel type MO S transistors 8 3 and 8 6 are coupled to the high potential side power supply VCC, and the n-channel type MO S transistors 84 and 87 are coupled to the ground GND.
  • a signal transmission path from the n-channel type MOS transistor 85 to the input terminal of the second logic circuit 102 is a node 6.
  • the input signal is logically inverted by the first logic circuit 101, further logically inverted by the second logic circuit 102 at the subsequent stage, and then output through the output terminal OUT.
  • the step-down circuit 81 is not particularly limited, as shown in FIG. 32, a constant voltage generation circuit 3 01 for generating a reference voltage V ref of a predetermined level and an internal power source based on the reference voltage Vr ef are shown. And a negative feedback amplifier circuit 302 for generating VDD I.
  • the negative feedback amplifier circuit 302 is not particularly limited, as shown in FIG. 33, a difference formed by coupling n-channel MOS transistors 31 1 and 312 to a ground GND via a constant current source 313.
  • the dynamic coupling circuit, p-channel type MOS transistors 314, 3 15 forming a current mirror type load of the differential coupling circuit, and the internal power supply VDD I are output based on the output signal from the differential coupling circuit.
  • Capacitance function 316 is formed of a depletion type MOS transistor, and the other MOS transistors are an enhancement type.
  • the phase compensation capacitor 316 is coupled between the drain electrode of the p-channel M 0 S transistor 3 17 and the ground GND via a resistor 3 18 as shown in FIG. Sometimes.
  • the capacitor 316 for phase compensation is formed by the gate capacitance of a depletion type MOS transistor
  • the n-channel type MOS transistor 85 in FIG. 13 is the same process as the capacitor 3 16. Formed by.
  • the p-channel type MOS transistor 86 is connected to the GIDL «: G at Indudu ced D rain L eakage) characteristics may cause an undesired current to flow.
  • the p-channel type MO S transistor has a sub-threshold from the drain (D rain) to the source (S ou rce) as the gate-source voltage VGS increases. ⁇ Shows the characteristic that the threshold current (Sub hr es ho ldcurre nt) increases. As the gate-source voltage VGS decreases, the drain current from the drain (D rain) to the source (Sour ce) generally decreases.
  • the p-channel type MOS transistor 8 is a transistor exhibiting the above-mentioned GIDL characteristics, in the configuration shown in FIG. 14, the p-channel type MO S transistor 83 is coupled to the high-potential side power source V CC. Because the p-channel type MOS transistor 8 6 is coupled to the internal power supply VDDI, the high-level potential of the node 7 becomes equal to the high-side power supply VCC. An undesired current due to the GIDL characteristic flows between the gate and source of 86 by applying a potential of the opposite polarity to the potential for turning on the channel.
  • a depletion type M 0 S transistor 85 is provided between the first logic circuit 1 0 1 and the second logic circuit 1 0 2, and the high level of the node 6 is increased. The potential of the level is lowered. In other words, the threshold of the depletion type M ⁇ S transistor 85 is set to Vt h. When this happens, the high level potential of node 6 is reduced to VDDI – V th. As a result, it is possible to avoid applying a reverse polarity to the channel-on potential between the gate and source of the p-channel MOS transistor 86, and to suppress unwanted current due to GIDL characteristics. .
  • the 18th shows a configuration example of the input buffers 40 and 41 shown in FIG.
  • This configuration is basically the same as the circuit shown in Fig. 16 with the function to change the logic threshold for the input signal by the control signal CTL and the circuit activated by the chip select signal CSB. A function is added to make it happen.
  • the first logic circuit that operates when the high-potential-side power supply V CC is supplied 1 0
  • a p-channel MOS transistor 9 8 whose operation is controlled by the control signal CTL transmitted from the interface controller 45 shown in FIG. 1 is provided, and is connected in series to the p-channel MOS transistor 98.
  • a p-channel MOS transistor 99 is provided.
  • a chip select signal CSB is transmitted to the gate electrode of the n-channel type MOS transistor 100 through the inverter 96.
  • the chip select signal CSB is asserted to a single level by the chip controller 46 shown in FIG. 1, the output logic of the signal terminal 96 is set to a high level, and the n-channel type MOS transistor 100 is turned on. Since it is turned on, the first logic circuit 100 is activated.
  • the chip select signal CSB is negated to a high level by the above-mentioned chip controller 46, the output logic of the inverter 96 is set to the low level, and the n-channel type MOS transistor Since 100 is turned off, the first logic circuit 100 is deactivated.
  • a second logic circuit 102 that is operated by being supplied with the high-potential-side power supply VCC is disposed after the first logic circuit 101.
  • the second logic circuit 102 is a two-input NAND circuit 97.
  • the output signal of the first logic circuit 101 is transmitted to one input terminal of the NAND circuit 97 via a depletion type MOS transistor 85.
  • a depletion type MOS transistor 85 As in the configuration shown in FIG. 13, an undesired current due to the GIDL characteristic flows in the MOS transistor constituting the second logic circuit 102. It is provided to suppress this.
  • the chip select signal CSB is transmitted to the other input terminal of the NAND circuit 97 via the inverter circuit 96.
  • the NAND circuit 97 When the chip select signal CSB is asserted to the mouth level, the NAND circuit 97 is activated and signal output from the output terminal OUT is enabled.
  • High breakdown voltage MOS transistors are used for the circuit elements that operate when the high-potential-side power supply V CC is supplied and the peripheral circuit elements.
  • the MOS transistors 83, 84, 85, 98, 99, 100, and the configuration transistors of the NAND circuit 97 are High breakdown voltage type. Note that the transistor of Inverter 96 does not have to be a high voltage type.
  • the logic threshold value of the first logic circuit 101 is determined by the gate size ratio between the p-channel type MOS transistor 83 and the n-channel type MOS transistor 84.
  • the P-channel type MOS transistor 98 Since the P-channel type MOS transistor 98 is turned on, the p-channel type MO S transistor 99 is connected in parallel to the p-channel type MOS transistor 83, thereby raising the logic threshold of the first logic circuit 101. It is. Thus, by controlling the operation of the p-channel type MOS transistor 98 according to the logic level of the control signal CTL, the logic threshold value for the input signal can be easily switched.
  • FIG. 19 shows a more detailed configuration example of the input buffer 40.
  • the gate size ratio of the MOS transistor is shown.
  • “30 / 0.6” in the vicinity of a p-channel type MOS transistor 98 is the ratio of the gate width (W) to the gate length (L) of the M ⁇ S transistor 98 (W / L) is 30 / 0.6.
  • first logic circuit 101 that is operated by the supply of the high-potential-side power supply V CC and a second logic circuit 102 that is disposed at the subsequent stage and is operated by the supply of the internal power supply VDD I.
  • the first logic circuit 101 and The n-channel MOS transistor 85 as a coupling circuit for coupling the second logic circuit 102 is provided in the same manner as shown in FIG.
  • the second logic circuit 1 0 2 includes a 2-input NAND circuit 9 7 and an inverter 1 1 0 for inverting the output signal of the 2-input can circuit 9 7, and the output of the inverter 1 1 0 Inverter signal 1 1 1 to invert the signal to invert the output signal 1 1 1, Inverter output signal 1 1 0 Inverter signal 1 1 2, Inverter output 1 1 2 Output Inverter 1 1 3 for obtaining inverted output OUTB by inverting the signal.
  • Each of the above-mentioned chambers 1 1 0 to 1 1 3 is connected in series with a p-channel M0 S transistor coupled to the internal power supply VDDI and an n-channel MOS transistor coupled to the ground GND. Made up.
  • the wiring resistance 115 is relatively large. Since the wiring resistance 1 15 is connected in series to the resistance 7 3 included in the electrostatic breakdown protection element 24, it exhibits an electrostatic breakdown protection function in the same manner as the resistance 7 3 described above. For this reason, as the electrostatic breakdown protection element 24, it is possible to adopt a smaller element in consideration of the value of the wiring resistance 1 15.
  • the input buffer 41 can also employ the same configuration as in FIG.
  • FIG. 1 A configuration example of the output driver 42 and the output buffer 43 is shown in FIG.
  • Output driver 4 2 is not particularly limited, but output driver 2 0 1, 2
  • a switching control circuit 204 for switching the rising and falling characteristics of the signal waveform output from the output buffer 43.
  • the output drivers 20 1, 202, 203 and the switching control circuit 204 are activated by a driver activation signal DOC transmitted from the chip controller 46. Then, the output drivers 201, 202, 203 drive the output buffer 43 based on the data DATA input while being activated by the driver activation signal D 0 C.
  • the output buffer 43 is not particularly limited, but includes a first output driver in which a p-channel type MO S transistor 231 and an n-channel type MO S transistor 232 are connected in series, and a p-channel type MO S transistor. And a second output driver in which an n-channel type MOS transistor 234 is connected in series.
  • the source electrodes of the p-channel type MOS transistors 23 1, 233 are coupled to the high potential side power source V CC, and the source electrodes of the n-channel type MOS transistor transistors 232, 234 are coupled to the ground GND.
  • An electrostatic breakdown protection element 26 is disposed between the output driver 42 and the output buffer 43.
  • the electrostatic breakdown protection element 26 includes resistors 22 1, 22 2, 223 and 2 24, although not particularly limited.
  • the output driver 42 and the output buffer 43 are coupled to each other by a metal wiring 52 on the memory cell array 31 as apparent from FIG. It can be used as resistors 2 2 1, 2 2 2, 2 23, 224.
  • the electrostatic breakdown protection element 27 disposed in the vicinity of the pad 17 for signal output includes a diode 2 7 1 coupled to the output signal line of the output buffer 4 3 and the high-potential side power supply VCC, Output buffer 43 output signal line and ground coupled to ground GND Diode 2 72.
  • the output driver circuits 20 1, 202, 203 are basically configured as shown in FIG.
  • the output driver circuits 20 1, 20 2, and 20 03 basically include gate circuits 24 1, 242, 243, 244, p-channel MOS transistors 245, 247, and n-channel MOS transistors 246. , 248 and.
  • the gate circuit 24 1 takes the logic of the input device DAT A and the driver activation signal D 0 C, and the P-channel type MOS transistor 245 is driven according to the logic output.
  • the gate circuit 242 takes the logic of the input device DAT A and the driver activation signal D 0 C, and the n-channel type MOS transistor 246 is driven according to the logic output.
  • the gate circuit 243 takes the logic of the input data DAT A and the driver activation signal D 0 C, and the p-channel type MOS transistor 247 is driven according to the logic output.
  • the gate circuit 244 logics the input data DATA and the driver activation signal D 0 C, and the n-channel type MOS transistor 248 is driven according to the logic output.
  • the source electrodes of the p-channel type MO S transistors 245 and 247 are coupled to the high-potential side power source V CC, and the source electrodes of the n-channel type MO S transistors 246 and 248 are coupled to the ground GND.
  • This output driver circuit has a first output terminal 29 1 and a second output terminal 29 2 for driving the output buffer 43 in the open drain format of the MO S transistor.
  • the p-channel MOS transistor 2 45 and the drain electrode of the n-channel MO S transistor 246 are coupled via the resistor 249, and the p-channel MOS transistor 245 drain electrode and the resistor 249 are connected.
  • the first output terminal 2 9 1 of this output driver circuit is drawn from the node.
  • the above p chine The drain electrode of the n-channel type MO S transistor 247 and the drain electrode of the n-channel type M S transistor 248 are coupled via a resistor 2550, and the drain electrode of the n-channel type MO S transistor 248 and the resistor 2 described above are combined.
  • the second output terminal 2 92 of this output driver circuit is drawn from the connection node with 50.
  • the P-channel type MOS transistor 245 resets the p-channel type MOS transistor by driving the gate electrode of the P-channel type MOS transistor 2 31 or 233 in the output buffer 43 to a high level. In this sense, the p-channel M 0 S transistor 245 is referred to as “p M 0 S reset side circuit 28 1”.
  • the n-channel MOS transistor 246 and the resistor 249 are connected to the n-channel MOS transistor by driving the gate electrode of the p-channel MOS transistor 231 or 233 in the output node 43 to a low level. In this sense, the n-channel MOS transistor 246 and the resistor 249 are referred to as “pMO S set side circuit 282”.
  • the ⁇ channel type MOS transistor 247 and the resistor 250 are connected to the ⁇ channel type MO S by driving the gate electrode of the ⁇ channel type MO S transistor 232 or 2 34 in the output buffer 43 to a high level. In this sense, the ⁇ channel type MOS transistor 247 and the resistor 250 are referred to as an “nMOS set side circuit 283”.
  • nMOS reset side circuit 284 The above-mentioned ⁇ channel type MOS transistor 248 is driven by driving the gate electrode of the ⁇ channel type MO S transistor 2 3 2 or 2 34 in the output buffer 43 to a single level. In this sense, this n-channel type MOS transistor 248 is referred to as “nMOS reset side circuit 284”.
  • the resistors 249 and 250 have a function of delaying driving of the output driver 43. Therefore, the driving capability of the output driver 42 can be switched by properly using a circuit in which such a resistor is interposed and a circuit in which the resistor is not interposed based on the driver activation signal D 0 C. Further, the output buffer drive size can be changed by changing the number of MOS transistors involved in the output operation in the output buffer 43 based on the driver activation signal D 0 C. For example, in order to support LV-CMOS interface or LV-TTL interface,
  • the p M 0 S reset side circuit 281, the pMOS set side circuit 282, and the n M 0 S set in the output driver circuits 201, 202, and 203 It is preferable to use a different side circuit 283 and nMOS reset side circuit 284.
  • the pMO S set side circuit 282 and the nMO S set side circuit 283 in the output driver circuit 201 and all of the output driver circuits 202 and 203 are all connected.
  • the output buffer 43 is driven at high speed by using the set side circuit and the reset side circuit.
  • the first LV-CMOS interface the first
  • the noise margin 131 on the low level side and the noise margin 132 on the high level side are large, so the output signal waveform from the output buffer 43 can be increased by driving the output buffer 43 at high speed.
  • the tr / tf value which is the rising / falling characteristic, can be reduced to shorten the signal transmission time.
  • output P MO S set side circuit 2 82 and nM0 S set side circuit 283 in driver circuit 201, and pMO S reset side circuit 28 1 and nMO S reset side circuit 284 in output driver circuit 202 are used.
  • Other circuits are not involved in driving the output buffer 43.
  • the output current from the output buffer 43 is reduced, thereby reducing noise included in the output waveform.
  • the noise margin 141 on the low level side becomes smaller as the level of the high potential side power supply VCC decreases, and the level of the high potential side power supply V CC This is because the noise margin 142 on the high level side becomes smaller as the value becomes higher, so that it is necessary to suppress the noise included in the output signal by driving the output buffer 43 at a low speed.
  • FIGS. 27 to 29 show more detailed configuration examples of the output driver 42 and the output buffer 43.
  • the switching control circuit 204 includes a first D 0 C driver 262, a second D 0 C driver 261, and a data driver 2 63.
  • Output signals from the first DO C driver 2 62, the second D OC driver 2 61, and the D / D driver 2 63 D 0 C— B— C, D 0 C — T_C, D 0 C_B, D OC— T, D AT A_B, DATA 1 T is transmitted to the output driver circuits 201, 202-1, 202-2; 203-1, 203-2 shown in FIG.
  • the output driver circuits 202-1 and 202-2 in FIG. 28 correspond to the output driver circuit 202 in FIG. 24, and the output driver circuits 203-1: 203-2 in FIG. This corresponds to the output driver circuit 203 in FIG.
  • the output signals of the output driver circuits 2 0 1, 2 0 2-1, 2 0 2— 2, 2 0 3— 1, 2 0 3— 2 are sent to the second 9 9 through the electrostatic breakdown protection element 26. It is transmitted to the output buffer 43 shown in the figure.
  • the electrostatic breakdown protection elements 27-1 and 27-2 are arranged in the front and rear stages of the output buffer 43, respectively. These electrostatic breakdown protection elements 2 7-1 and 2 7-2 correspond to the electrostatic breakdown protection elements 2 7 in FIG.
  • the gate size ratio (W / L) is 1 0 0 / 0.6 or 2 0 0 / 0.6.
  • W / L the gate size ratio
  • a transistor with a larger gate size ratio is adopted compared to other MO S transistors.
  • FIG. 30 shows a truth table of the main parts of the output driver 42 and the output buffer 43 in FIGS. 27 to 29.
  • L indicates low level
  • H indicates high level
  • HZ indicates high impedance state
  • X indicates logic indefinite.
  • FIG. 31 shows a layout example in the case where two systems of the output driver 4 2 and the output buffer 43 in FIG. 27 to FIG. 29 are arranged.
  • the control circuit 299 includes an inverter controller 45 and a chip controller 46, and outputs various control signals.
  • the output drivers 42-1 and 4 2-2 correspond to the output driver 42 shown in FIG.
  • Output pads 17-1 and 17-2 are formed at predetermined intervals on the edge of the semiconductor chip, and output buffers 43-1 and 43-2 between the output pads 177-1 and 17-2. Is placed.
  • the output buffers 43-1 and 43-2 correspond to the output buffer 43 shown in FIG.
  • Electrostatic breakdown protection elements 2 7-1 and 2 7-2 are formed in the area where the output buffers 4 3-1 and 4 3-2 are formed. Since the output dryers 42—1, 42—2 and the output buffers 4 3 — 1, 43—2 are arranged separately, the output buffers 4 3—1, The formation area of 43-2 is relatively small, and is set to be between the output pads 17-1 and 17-2.
  • resistors, capacitors, and diodes in this example can be configured as follows.
  • a resistor 403 can be obtained between the terminals 401 and 402 by using a polysilicon layer formed on a semiconductor substrate such as silicon (Si).
  • the terminals 41 A resistor 414 can be obtained between 1 and 412 and a diode 415 coupled to it can be obtained.
  • Capacitance 423 can be obtained between terminals 421 and 422.
  • the capacitor 433 can be obtained between the terminals 431 and 432, and the diode 435 coupled to the capacitor 433 can be obtained.
  • Figures 7 through 12 show different configurations for bonding options. An example is shown.
  • the first protection circuit ESD 1 shown in FIG. 4 may be adopted for all of the electrostatic discharge protection elements 20, 21, 23, 25.
  • the logic combination of the two control lines 55-1, 55-2 is used to increase the logic threshold of the input buffers 40, 41 and the rise of the output signal waveform of the output driver 42.
  • the falling (tr / t: f) characteristics can be adjusted in 4 steps.
  • pads 18-1 and 18-2 for bonding options are formed at one end of the semiconductor chip 9, and pads 13-1 and 13-2 for bonding options are formed at the other end. It is formed.
  • ESD protection element 201-1 is located near pad 13-1; ESD protection element 25-2 is located on pad 18-2 The electrostatic discharge protection element 20-2 is placed in the vicinity of the pad 1
  • Pads 18-1 and 13-1 for bonding options are connected via control line 55-1, and pads 18-2 and 13-2 for bonding options are connected to control line 55-2. It is combined through. Depending on the bonding option, both control lines 55-1 and 55-2 can be set to high level or mouth level, and either control line 55-1, 55-2 can be set to high level or low level. It is possible to obtain a total of four types of logic combinations. In FIG. 8, the control lines 55-1 and 55-2 may be crossed in the middle of them. In this configuration of the c further shown in FIG. 9, the logic threshold value in the input buffer 40, 41, falling waveform rising edge of the output signal at the output drivers 42 and (tr / tf) characteristic in multiple levels It can be configured to be adjustable.
  • pads 18-1 to 18-8 for bonding options are formed at one end of the semiconductor chip 9, and pads for bonding options 13-3 to 1 3 to the other end. 4 is formed.
  • Electrostatic discharge protection elements 25 1 to 2 5—4 are arranged near the corresponding pads 1 8—1 to 1 8—4.
  • Electrostatic discharge protection elements 2 0— ;! ⁇ 20-4 are arranged in the vicinity of the corresponding pads 13-1 to 1 3-4.
  • Pads for bonding options 1 8— 1 and 1 3— 1 are connected via control line 5 5-1 and pads for bonding options 1 8— 2 and 1 3— 2 Are coupled via control line 55-2.
  • pads 1 8-3 and 1 3-3 for bonding options are connected via control lines 5 5-3 and pads 18-4 and 1 3-4 for bonding options. Are coupled via control lines 5 5-4. Wires with this bonding option 6 1 — 1, 6 1-2, 1 3— 1, 1 3— 2 Depending on which pad is coupled, the logic combination in the control lines 5 5-1-5 5-4 There are 16 ways.
  • semiconductor chip 9 has two ground GND Pads for ground GND 14-1 and 14-2 are formed corresponding to external terminals 1 2— 1 and 1 2-2 for bonding, and pads for bonding options 1 3— 1, 1 3-2 may be formed.
  • control line 5 5-1 level connect external terminals 1 2— 1 and pad 1 3— 1 with the bonding option, and control line 5 5 1 2 to level.
  • the external terminals 1 2—2 and pads 1 3—2 can be connected by bonding options.
  • Fig. 12 corresponds to the four edges of the semiconductor chip 9.
  • External terminals for supplying the high-potential side power supply V CC 1 1 1 1, 1 1 1 1 2, and external terminals 12-1 and 12-2 for supplying the low-potential side power supply (ground GND) If possible, a bonding option can be formed accordingly.
  • the logic threshold in the input buffers 40 and 41 and the waveform rising and falling (tr / tf) characteristics of the output signal in the output driver 42 are divided into 16 levels. Can be adjusted.
  • MOS transistors can also be used.
  • an enhancement type MOS transistor 95 is provided between the first logic circuit 101 and the second logic circuit 102.
  • a p-channel type MOS transistor 94 for feedback is provided. The p-channel MOS transistor 94 is turned on when the output signal of the second logic circuit 102 becomes low level, and lowers the high level potential of the node 8 to the internal power supply VDDI.
  • the control signal CTL may be supplied to the gate electrode of the p-channel type MO transistor transistor 98, and as shown in FIG. 21, the p-channel type MO Supply the input signal IN to the gate electrode of the S transistor 98, and the control signal CTL to the gate electrode of the p-channel type MOS transistor 99.
  • the switching of the logic threshold values in the input buffers 40 and 41 is performed by the p-channel type MOS transistor, but this switching is performed by the n-channel type MOS transistor. You can also. For example, as shown in FIG.
  • a p-channel MOS transistor 98 and an n-channel MOS transistor 124 are connected in series to form a chamber, and the n-channel MOS transistor is configured as described above.
  • CT LB inverted signal of CTL
  • the n-channel type MOS transistor 123 becomes the n-channel type MOS transistor. It is configured to be involved in circuit operation by being connected in parallel at evening 124.
  • the logic threshold can be changed depending on whether or not the n-channel MOS transistor 123 is connected in parallel to the n-channel MOS transistor 124. However, as shown in FIG.
  • switching of the logic threshold values in the input buffers 40 and 41 is done using n-channel MOS transistors. In this case, a large amount of through current I flows, whereas if the logic threshold value switching in the input buffers 40 and 41 is performed with an n-channel MOS transistor, the through current I can be reduced.
  • the bonding option was adopted, but it is also possible to employ a fuse circuit that allows logic setting by blowing a specific fuse.
  • the function selection target is the input threshold value in the input buffer.
  • the operation power supply voltage, package, capacity, bit width, and function can be listed. .
  • the present invention can be applied to a semiconductor integrated circuit including an input buffer and an output buffer, particularly a semiconductor integrated circuit as a semiconductor memory device having a memory cell array for storing information.

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  • Semiconductor Integrated Circuits (AREA)

Abstract

On peut réduire l'échelle d'un circuit de sélection de fonctions en utilisant un contrôleur pouvant modifier à la fois les caractéristiques de monté et de retombée de la forme d'onde d'un signal émis par un tampon, et la valeur logique de seuil d'un tampon d'entrée, en fonction du niveau logique du signal d'un noeud commun facultativement introduit. Un circuit de couplage comporte un premier transistor du type à dépression servant à abaisser le niveau de la tension du signal introduit dans un deuxième circuit, et à réduire le courant indésirable traversant un transistor inclus dans le deuxième circuit à caractéristiques de fuite GIDL. On optimise la disposition du circuit de sortie en reliant le tampon de sortie et le pilote de sortie via les lignes de signaux formées en utilisant une couche supérieure là où est formé un réseau de cellules mémoire.
PCT/JP2002/000742 2002-01-31 2002-01-31 Circuit integre a semi-conducteurs WO2003065455A1 (fr)

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PCT/JP2002/000742 WO2003065455A1 (fr) 2002-01-31 2002-01-31 Circuit integre a semi-conducteurs
JP2003564938A JPWO2003065455A1 (ja) 2002-01-31 2002-01-31 半導体集積回路
TW091105866A TW594973B (en) 2002-01-31 2002-03-26 Semiconductor integrated circuit

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JP2019054370A (ja) 2017-09-14 2019-04-04 東芝メモリ株式会社 半導体記憶装置

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