Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
  • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
  • H01L21/3065—Plasma etching; Reactive-ion etching
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
  • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
  • H01J37/32—Gas-filled discharge tubes
  • H01J37/32431—Constructional details of the reactor
  • H01J37/3266—Magnetic control means
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3105—After-treatment
  • H01L21/311—Etching the insulating layers by chemical or physical means
  • H01L21/31105—Etching inorganic layers
  • H01L21/31111—Etching inorganic layers by chemical means
  • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

Definitions

• This invention relates generally to plasma etching, and more particularly to plasma etching of dielectric materials using fluorochemicals.
• Oxides and nitrides are used widely in the manufacture of microprocessors and other semiconductor devices. Oxides are particularly useful, due to the ability to readily change the conductive properties of these materials from a dielectric state to a semiconducting state through ion implantation or through other commonly used doping methodologies.
• the field oxide layer must be etched down to the nitride layer so that the portion 24 of the nitride layer at the bottom of the gap can be removed and electrical contact can be made with the n-type or p-type well 16 formed in the silicon substrate below.
• the nitride layer over the gate structures is not significantly reduced in thickness, since doing so increases the likelihood of an electrical shortage in the completed device and can seriously degrade its performance.
• the nitride layer on the shoulder of the gate structure is highly prone to thinning or "faceting" during the etching process, both because of its geometry and because of the length of time it is exposed to the etching plasma during the etching process. It is thus important that the etching plasma be highly selective to the corner nitride. It is also important that the etching plasma be selective to the photoresist employed in the etching process so that a hole of the correct dimensions and geometry may be obtained. Moreover, it is very important that the etching process does not extend the hole being etched into the n-type or p-type well 16 positioned below the gap 16, since doing so would again adversely affect the performance of the device. Hence, it is also important that the etching process be capable of exhibiting etch stop behavior on doped oxide, and/or high selectivity to the flat nitride portion extending between the gate structures.
• etching of the substrate depicted in FIG. 1 is achieved through a two-step process.
• C F ⁇ /Ar is used in a main etch that removes the field oxide layer down to the conformal layer of silicon nitride.
• C 4 F 6 /Ar/CH 2 F 2 is used for an over etch, so called because the total oxide etching time is set significantly higher than that required to etch the design thickness of the oxide layer.
• the over etch is required to compensate for the fact that the substrate used in Hung et al. has a wavy surface, which in turn produces an oxide thickness that varies significantly. Hence, the over etch is required to assure penetration of the oxide layer.
• CH 2 F 2 /0 2 /Ar is then used to etch the nitride layer prior to a subsequent metal implantation step.
• the main etch is said to provide a hole with a good vertical profile, while the over etch with the strongly polymerizing CH 2 F 2 causes the deposition of a fiuoropolymer over the corner nitride, thereby providing some protection against faceting.
• the reference advocates the use in the main etch of fluorocarbons having 3 or more carbon atoms and having an F/C ratio of at least 1 but less than 2.
• nitride layer which is about 500 to 700 A thick, or about 100 to 200 A thinner than a comparable device having a gap of 0.35 microns.
• the present invention relates to a method for etching a substrate, such as a semiconducting or dielectric substrate, using a plasma based on a mixture of 0 2 and at least a first gas having the formula C a F and a second gas having the formula C x H y F z .
• the chemical composition of these gases are such that typically at least one, more typically at least two, and most typically all three of the following conditions are satisfied: a/b > 2/3 x z > 1/2; and x/y ⁇ l/3.
• the dissociation of C x H y F z is found to result in unique polymers that adhere well to the sidewalls of the hole being etched, thereby resulting in high selectivity to the comer nitride.
• the resulting plasma may be utilized to etch advanced structures having small feature sizes (e.g., less than about 0.25 microns) without any substantial occlusion of the hole.
• the methodology is well suited to etching SAC structures having gaps between the gate structures of less than about 0.25 microns, less than about 0.18 microns, and indeed even less than about 0.14 microns.
• the present invention relates to a method for etching a substrate which contains an undoped oxide layer and a doped oxide layer.
• the substrate may include, for example, an SAC structure having a gap between the gate structures of less than about 0.25 microns, having a conformal layer of nitride overlying the gate structures, and having a layer of undoped oxide and doped oxide disposed over the conformal layer, with the layer of doped oxide disposed between the layer of undoped oxide and the conformal nitride layer.
• the undoped oxide layer is then etched using a plasma based on a gas stream which includes a first gas having the formula C a F b until the doped oxide layer is reached.
• the point at which the doped oxide is reached may be determined, for example, by spectrographic analysis geared toward detecting the presence of the dopant, or by other suitable means.
• the doped layer is etched using a plasma based on a gas stream which includes a second gas having the formula C x H y F z .
• the chemical composition of these gases are such that typically at least one, more typically at least two, and most typically all three of the following conditions are satisfied: a/b > 2/3 x/z > 1/2; and x/y ⁇ l/3.
• C x H y F z causes the deposition of novel fluoropolymers on the side walls of the hole that protect the underlying nitride from being etched, these gases exhibit better comer nitride selectivity than C a F b .
• the use of C a F b in the main etch is advantageous in that it produces a hole with a better vertical profile than could be achieved with C x H y F z alone.
• C a F b is a nonselective oxide etch, while certain mixtures of C x H y F z (such as C 2 H 2 F with CHF 3 and Ar) exhibit etch stop behavior on undoped oxide.
• the first gas is and the second gas is C 2 H 2 F 4 .
• the present invention relates to a method for etching a substrate, such as a semiconducting or dielectric substrate, using a plasma based on a mixture of C F 6 and C 2 H 2 F 4 .
• the mixture typically further contains 0 2 , and also typically contains Ar or another inert gas as a carrier.
• the present invention relates to a method for etching a substrate, such as a semiconducting or dielectric substrate, comprising the steps of first etching the substrate with a plasma based on G ⁇ , and then etching the substrate with a plasma based on C 2 H 2 F 4 .
• the present invention relates to a method for etching a substrate, comprising the steps of (a) positioning in a chamber a structure comprising a first layer disposed on a substrate, the first layer being selected from the group consisting of dielectric layers and semiconductor layers; (b) supplying a reactive gas mixture to the chamber, the gas mixture comprising a first gas having the formula C a F b and a second gas having the formula C x H y F z , wherein a/b > 2/3 and x/z > 1/2; (c) applying sufficient RF energy to the chamber to establish an etching plasma and an associated electric field perpendicular to the surface of the substrate; (d) applying a magnetic field to the chamber substantially perpendicular to the electric field and substantially parallel to the surface of the substrate; and (e) allowing the plasma to etch at least a portion of the first layer.
• the present invention relates to a method for etching a substrate, comprising the steps of (a) providing a substrate selected from the group consisting of semiconductor and dielectric substrates; and (b) etching the substrate through a magnetically enhanced reactive ion etch process, the process including the addition of a source of hydrogen radicals to a gas mixture in an amount sufficient to increase the value of at least one parameter selected from the group consisting of etch rate and selectivity of the reactive gas mixture for the substrate.
• the gas mixture comprises a first gas having the formula C a F b and a second gas having the formula C x H y F z , wherein ab > 2/3 and x/z > 1/2.
• the present invention relates to an apparatus for etching substrates, comprising a chamber adapted to receive a substrate to be etched and at least one reservoir in open communication with the chamber.
• the at least one reservoir is adapted to supply a gas mixture to the chamber comprising a first gas having the formula C a F b and a second gas having the formula C x H y F z , wherein a/b > 2/3 and x z > 1/2.
• the gas mixture typically also comprises oxygen.
• the present invention relates to a method for etching a substrate, comprising the steps of (a) providing a substrate selected from the group consisting of semiconductor and dielectric substrates; (b) etching the substrate through the use of a plasma based on a gaseous mixture of at least C F 6 , 0 2 , and Ar, thereby forming a modified substrate; and (c) further etching the modified substrate through the use of a plasma based on a gaseous mixture of at least C F 6 , 0 2 , Ar, and C 2 H 2 F 4 .
• the present invention relates to a method for etching a substrate, comprising the steps of (a) providing a substrate comprising (i) a first layer, (ii) a second layer comprising a doped oxide such as boron phosphorosilicate glass, (iii) a fourth layer comprising an antireflective material, and (iv) a third layer, disposed between the second and fourth layer, comprising an undoped oxide such as tetraethylorthosilicate; (b) etching the substrate through the use of a plasma based on a first gaseous mixture comprising C 4 F 6 , 0 2 and Ar so as to form a depression that extends through the fourth layer and at least partially through the third layer, but does not extend substantially into the second layer; and (c) further etching the substrate through the use of a plasma based on a second gaseous mixture comprising C 4 F 6 , 0 2 , C 2 H 2 F 4 , and Ar so as to extend
• the present invention relates to a method for controlling profile and/or Mean Wafer Between Wet Clean (MWBWC) performance in a plasma etching process.
• a gas mixture comprising
• C x H y F z /C a F b /0 2 is used in the etching process.
• the C x H y F z /C a F b /0 2 ratio is manipulated to control the degree of polymerization, which in turn controls the profile and Mean Wafer Between Wet Clean (MWBWC) performance.
• the present invention relates to a substrate equipped with an SAC stracture comprising first and second gate structures disposed on a silicon substrate.
• the gate structures have a gap between them of less than about 0.25 microns, typically less than about 0.18 microns, and most typically less than about 0.14 microns, and are covered by a layer of silicon nitride.
• a layer of undoped oxide is disposed over the layer of silicon nitride, and a layer of doped silicon oxide is disposed between the layer of undoped oxide and the layer of silicon nitride.
• the layer of doped oxide is thick enough to cover the SAC structure.
• the structure may be advantageously employed in plasma etching operations based on gas mixtures comprising C 4 F 6 and C 2 H 2 F 4 (which mixtures may further include 0 2 and/or Ar) or in plasma etching operations involving etching with a first gas stream comprising C 4 F 6 and a second gas stream comprising C 2 H 2 F 4 (these first and second gas streams may also further comprise 0 2 and/or Ar) in that spectrographic methods may be used to determine completion of etching through the undoped oxide layer by detecting an increase in the concentration of dopant from the doped oxide layer in the etching chamber atmosphere. In this way, etching can be controlled reliably even with variations in processing parameters, and faceting of the nitride layer can be avoided.
• FIG. 1 is a schematic drawing of a prior art SAC structure
• FIG. 2 is a schematic drawing of an exemplary etching chamber that may be used in connection with various embodiments of the invention
• FIG. 3 is a schematic drawing of an SAC structure which may be etched using the methodology of the present invention.
• selectivity is used to refer to a) a ratio of etch rates of two or more materials and b) a condition achieved during etch when etch rate of one material is substantially different from another material.
• oxide generally refers to silicon dioxide and to other silicon oxides of the general formula SiO x , as well as to closely related materials such as borophosphosilicate (BPSG) and other oxide glasses.
• BPSG borophosphosilicate
• nitride refers to silicon nitride (Si 3 N ) and to its stoichiometric variants, the later being generally encompassed by the formula SiN x , where x is between 1 and 1.5.
• the present invention utilizes gas streams containing particular fluorocarbon gases to generate plasmas that are suitable for etching substrates.
• the substrates to be etched will typically comprise oxides, nitrides, and/or other semiconducting or dielectric materials of the type employed in the fabrication of semiconductor devices.
• gases may be used in the gas streams of the present invention.
• the particular choice of gases to be used in the gas stream will depend on such factors as the particular substrate or material being etched, the required selectivity of the gas to one or more materials of interest such as a nitride layer or photoresist, the particular point in the etching process, and other such factors.
• the composition of the gas stream may be varied as a function of time or as a function of the progress of the etching operation.
• the preferred gases for use in the present invention are defined by the general formulas C a F and C x H y F z .
• the gas streams utilized will comprise mixtures of a first gas having the formula C a F and a second gas having the formula
• the first and second gases may instead be employed separately in independent processing steps.
• the first gas may be employed in a first etching step (e.g., in a main etch), and the second gas may be employed in a second etching step (e.g., in an over etch).
• the chemical composition of these gases are such that typically at least one, more typically at least two, and most typically all three of the following conditions are satisfied: a/b > 2/3; x/z > 1/2; and x/y > 1/3.
• the first gas is C ⁇ Fg and the second gas is C 2 H 2 F 4 (Freon
• the gas streams used in the present invention will also typically comprise an inert carrier gas.
• Argon is the preferred carrier gas, in part because it is inexpensive and is readily available from various commercial sources.
• other inert gases such as nitrogen, helium or zenon, could also be used in this capacity.
• the gas streams used in the present invention also typically comprise 0 2 .
• 0 2 The addition of 0 2 to the gas streams of the present invention is found to provide a number of advantages.
• many gases such as C 2 H 2 F 4
• gas streams containing 0 2 and C 4 F 6 can be used to etch such structures without substantial occlusion of the hole.
• the use of C 4 Fg/0 2 has been successfully used to etch feature sizes of less than about 0.14 microns.
• similar results may be obtained by substituting ozone or certain partially fluorinated or perfluorinated ethers for 0 2 .
• the gas stream may also contain CO.
• CO is advantageous in that it can be used in some instances to increase the carbon concentration of the plasma so that a high degree of polymerization can be achieved. This can be important, for example, when extremely high photo resist selectivity is required.
• Other additives as are known to the art may also be added to the gas stream for various purposes.
• processing parameters such as C a F b /C x H y F z and C a F b /O 2 gas ratios, the total gas flow, additive gas flow, RF power, chamber pressure, and B -field intensity, a desirable degree of polymerization can be induced on the surfaces of the substrate being etched.
• the high carbon concentration polymers so formed provide excellent performance in a wide range of dielectric etch applications, and help improve comer and flat nitride selectivity, photo resist selectivity, under layer selectivity, and bottom critical dimension uniformity.
• the resulting plasma contains less free F, which in turn makes the etch process less sensitive to the film being etched. Therefore, less tuning is required between doped and undoped dielectric films.
• Mixtures of the first and second gas defined above are especially suitable for use in the present invention and afford a number of advantages.
• plasmas based on C x H y F z gases are often found to be selective to undoped oxide films.
• the addition of sufficient amounts of C a F b to the process gas mixture allows the resulting plasma to etch undoped oxide films to the desired depth without any etch stop.
• the proportion of C a F b in the mixture can also be used as a processing knob when it is desired to etch stop on an undoped oxide layer.
• the amount of C a F b in the gas mixture can be reduced (to zero, if necessary) as the undoped oxide layer is approached to stop etching.
• Spectroscopic techniques or other suitable methods can be employed to detect the approach of doped or undoped oxide layers, typically by monitoring the chamber atmosphere for increases or decreases in dopant concentration.
• Gas mixtures can also be made in accordance with the present invention which provide high nitride selectivity, particularly when these mixtures include oxygen.
• C 4 F6/0 2 /Ar/C 2 H 2 F 4 chemistry is found to provide good passivation on both sidewall nitride and flat nitride in SAC applications.
• C 4 Fg/0 2 /Ar only chemistry does not exhibit as high of a comer nitride selectivity, although it gives good flat nitride selectivity.
• Etching in accordance with the present invention is typically performed through the use of plasmas that are sustained in a low pressure chamber in which the substrate to be etched is mounted.
• the etching devices suitable for use in the present invention are not particularly limited. Rather, the methodology of the present invention can be practiced using a number of known plasma reactors. Such reactors include, for example, the IPS etch reactor, which is available commercially from Applied Materials and which is described in U.S. 6,238,588 (Collins et al.) and in European Patent Publication EP- 840,365-A2, as well as the reactors described in U.S. 6,705,081 and in U.S. 6,174,451 (Hung et al.).
• FIG. 2 is a simplified schematic diagram of a MERIE system 100 suitable for use in the present invention.
• the system 100 includes a processing chamber 101.
• the chamber 101 comprises a set of side-walls 102, a floor 104 and a lid 106, defining an enclosed volume.
• a gas panel 110 supplies reactive gases (an etch chemistry) to the enclosed volume defined by the chamber 101.
• the system 100 further includes an RF power supply 122 and a matching circuit 120 that drives a pedestal assembly 108 such that an electric field is established between the pedestal assembly 108 and the chamber walls 102 and lid 106.
• a set of coils 124 are arranged about the sides 102 of the chamber 101 to facilitate magnetic control of the plasma 124.
• a pedestal assembly 108 comprises a pedestal 114 centrally mounted within the chamber 101 to a cathode 112 and surrounded by a collar 118.
• the pedestal retains a workpiece 116 such as a semiconductor wafer which is to be processed in the chamber 101.
• the plasma reaction chamber 101 employs capacitively coupled RF power to generate and maintain a low energy plasma 124.
• the plasma may be low, medium, or high density, although low to medium density plasmas are preferred in the practice of the present invention.
• RF power is coupled from the RF power supply 122 producing one or more RF frequencies through matching network 120.
• the lid 106 and walls 102 are grounded and serve as a ground reference (anode) for the RF power. With the configuration shown in FIG. 2, plasma density is controlled by the RF power provided by the power supply 122 via the matching circuit 120.
• the cathode 112 is typically fabricated from a conductive material such as aluminum.
• the pedestal 114 is typically fabricated from a polymer such as polyimide or a ceramic material such as aluminum nitride or boron nitride.
• the workpiece 116 i.e., a semiconductor wafer
• the electric field that couples to the plasma passes through both the workpiece and the pedestal. Since the cathode and workpiece are made of diverse materials, these materials have different effects on the plasma. Consequently, there is an abrupt change of plasma parameters, and process uniformity, at the wafer edge 126. To improve process uniformity at the wafer edge, a collar 118 surrounds and partially overlaps the pedestal 114.
• the collar 118 (also known as a process kit) is typically made of a material such as quartz.
• a gas stream is supplied through the gas panel 110 from one or more gas sources.
• these sources will be pressurized tanks containing the various components of the desired etch chemistry, such as Ar, 0 2 , and C 2 H 2 F 4 , which are connected to the gas panel by one or more gas feeds.
• the gas sources will typically be under the control, either directly or indirectly, of a system controller in which is stored the process recipe in magnetic or semiconductor memory, so that the flow of gas from these sources can be independently regulated to control or modify the compositional makeup of the atmosphere in the chamber.
• a vacuum pumping system may be connected to the chamber to maintain the chamber at a preselected pressure.
• an optical fiber which is placed in a hole penetrating the chamber wall to laterally view the plasma area above the wafer.
• An optical detector system may be connected to the other end of the fiber and may include one or more optical filters and processing circuitry that are tuned to the plasma emission spectrum associated with one or more species in the plasma.
• Either the raw detected signals or a trigger signal is electronically supplied to the system controller, which can use the signals to determine that one step of the etch process has been completed as either a new signal appears or an old one decreases. With this determination, the system controller can adjust the process recipe or end the etching step.
• the substrate to be etched can be designed to take advantage of this ability to determine the endpoint.
• comer nitride selectivity is very important. This is due in part to the fact that such smaller feature sizes require the conformal nitride layer disposed over the gate structures to be reduced in thickness (typically to within the range of 500 to 700 angstroms). Since comer nitride is typically prone to faceting anyway, it becomes necessary to compensate for this tendency by further increasing the comer nitride selectivity of the plasma.
• this can be accomplished by depositing an undoped layer of oxide and a doped layer of oxide over the SAC structure, with the doped layer disposed between the undoped layer and the conformal nitride layer.
• the undoped oxide may then be etched in a main etch using a chemistry such as C 4 F 6 which provides a good vertical profile.
• OES can then be used to detect the emergence in the etching chamber atmosphere of the dopant from the doped oxide layer (this will typically be a material such as boron), which marks the endpoint of the main etch.
• the etching chemistry may then be changed to C 2 H 2 F 4 or another material exhibiting heightened comer nitride selectivity.
• the change in chemistry may be characterized by the complete replacement of C F 6 with C 2 H 2 F when the endpoint is reached, or simply by an increase in the concentration of C 2 H 2 F 4 in the gas stream accompanied by a decrease in the concentration of C F 6 .
• the main etch may be readily controlled and stopped when the depth of the hole is in the proximity of the nitride layer, thereby avoiding faceting of the nitride layer.
• the methodologies of the present invention allow for the production of several types of advanced structures.
• An example of such an advanced structure is the self- aligned contact (SAC) structure for two transistors which is illustrated in the cross- sectional view of FIG. 3.
• the SAC structure is disposed on a silicon substrate 202 which may be, for example, silicon oxide or silicon nitride.
• the SAC structure is formed by depositing layers of a gate oxide 203, a polysilicon layer 204 (which may be doped or undoped) and an oxide hard mask 205, and photolithographically forming these layers into two closely spaced gate structures 210 having a gap 212 between them.
• Chemical vapor deposition is then used to deposit onto the wafer a substantially conformal layer 214 of silicon nitride (Si 3 N 4 ) about 100 to 500A in thickness, which coats the top and sides of the gate structures 210 as well as the bottom 215 of the gap 212.
• the nitride acts as an electrical insulator.
• Dopant ions are ion implanted using the gate structures 210 as a mask to form a self-aligned p-type or n-type well 216, which acts as a common source for the two transistors having respective gates 210.
• the drain structures of the transistors are not illustrated.
• the oxide layer typically has a thickness of about 9000A in thickness and may be a single field oxide layer or, as depicted in FIG. 3, may have a two-part construction in which the first 5000A in thickness 7 has the structure TEOS/PET cos/PSG (with BPSG/PSG filling the gap between the gates) and the next 4000A is an undoped oxide 208 layer.
• a photoresist layer 220 of between about 4000 A and about 9000 A is deposited over the oxide layer 218 and is photographically defined into a mask so that a subsequent oxide etching step etches a contact hole 222 through the oxide layer 218 and stops on the portion 224 of the nitride layer 214 underlying the hole 222.
• a post-etch sputter may be used to remove the nitride portion 224 at the bottom 215 of the gap 212.
• the silicon nitride acts as an electrical insulator for the metal, usually aluminum, thereafter filled into the contact hole 222.
• a Birefringent Antireflective Coating (BARC) 223 or other type of material capable of eliminating the adverse effect of standing waves may optionally be applied.
• This material which will typically be less than about 900 A thick, will typically be provided between the oxide layer and the photoresist mask.
• tungsten suicide WSix
• silicon nitride in that order.
• the significance of the selectivity offered by the gas mixtures of the present invention may be understood by considering the advantages afforded by SAC and other advanced structures, as well as the challenges these structures pose. Since nitride acts as an insulator, the SAC structure and process offer the advantage that the contact hole 222, which is typically about 0.14 to about 0.25 ⁇ m in diameter, may be wider than the width of the gap 212 between the gate structures 210. Additionally, the photolithographic registry of the contact hole 222 with the gate structures 210 need not be precise. However, to achieve these beneficial effects, the SAC oxide etch must be highly selective to nitride.
• selectivity is especially critical at the comers 226 of the nitride layer 214 above and next to the gap 212 since the comers 226 are the portion of the nitride exposed the longest to the oxide etch. Furthermore, they have a geometry favorable to fast etching that tends to create facets at the corners 226.
• CMP chemical mechanical polishing
• the required degree of selectivity is reflected in the probability of an electrical short between the gate structures 210 and the metal filled into the contact hole 222.
• the etch must also be selective to photoresist, although photoresist selectivity is not as critical as nitride selectivity here since the photoresist layer 220 may be made much thicker than the nitride layer 214.
• a wafer was provided which consisted of a surface layer of 9% PSG at the center of the wafer disposed on an undoped oxide substrate.
• Three separate holes were etched into the wafer using a MERIE reactor equipped with an eMAX chamber and using a gas stream consisting of C 4 F 6 Freon 134/0 2 /Ar.
• the processing parameters were as follows:
• the duration of the etch was approximately 60 to 90 seconds.
• the plasma readily penetrated the doped oxide surface layer, but exhibited etch stop behavior with respect to the underlying substrate.
• the undoped oxide layer 8 was etched using G F ⁇ /O ⁇ / r chemistry at respective flow rate ratios of 25 : 15 :500 until the BPSG layer was exposed.
• EXAMPLE 3 This example illustrates the poor comer nitride selectivity exhibited by only chemistry.
• This example illustrates the good comer nitride and flat nitride selectivity exhibited by Freon 134/C 4 F 6 /0 2 /Ar chemistry.
• C 4 F 6 /0 2 /Ar/Freon 134A was used in the second etching step to etch through the BPSG layer using flow rates of 27/15/500/4, respectively.
• the plasma again exhibited etch stop behavior with respect to flat nitride.
• comer nitride selectivity was noticeably improved, thus demonstrating the selectivity of C 4 F 6 /0 2 /Ar/Freon 134A to comer nitride.
• This example illustrates the etch stop behavior of Freon 134/C ⁇ e O ⁇ Ar chemistry on undoped oxide.
• the above examples illustrate the ability, by changing the composition of the process gas, to etch both doped and undoped oxide, or to achieve etch stop on undoped oxide.
• the examples also illustrate the improvement in co er nitride selectivity achievable with mixtures of Freon 134 and as compared to the results achieved with either gas alone.

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  • 2002-12-12 JP JP2003553608A patent/JP2006501634A/ja active Pending
  • 2002-12-12 TW TW091136022A patent/TWI301644B/zh not_active IP Right Cessation
  • 2002-12-12 KR KR10-2004-7009233A patent/KR20040066170A/ko not_active Ceased
  • 2002-12-12 WO PCT/US2002/039906 patent/WO2003052808A2/en not_active Ceased

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