WO2003046987A1 - Appareil a semi-conducteurs, procede de fabrication, et appareil a semi-conducteurs de type lamine tridimensionnel - Google Patents

Appareil a semi-conducteurs, procede de fabrication, et appareil a semi-conducteurs de type lamine tridimensionnel Download PDF

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Publication number
WO2003046987A1
WO2003046987A1 PCT/JP2002/012362 JP0212362W WO03046987A1 WO 2003046987 A1 WO2003046987 A1 WO 2003046987A1 JP 0212362 W JP0212362 W JP 0212362W WO 03046987 A1 WO03046987 A1 WO 03046987A1
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WIPO (PCT)
Prior art keywords
semiconductor device
wiring pattern
face
laminated type
unit
Prior art date
Application number
PCT/JP2002/012362
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English (en)
Japanese (ja)
Inventor
Takao Yamazaki
Tadanori Simoto
Sakae Kitajo
Yuzo Simada
Original Assignee
Nec Corporation
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Filing date
Publication date
Application filed by Nec Corporation filed Critical Nec Corporation
Publication of WO2003046987A1 publication Critical patent/WO2003046987A1/fr

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    • H01L2225/1047—Details of electrical connections between containers
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    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/1627—Disposition stacked type assemblies, e.g. stacked multi-cavities
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

L'invention concerne un appareil à semi-conducteurs permettant d'augmenter la capacité de mémoire avec des puces à semi-conducteurs de tailles et/ou types différents, et d'éviter une réduction du rendement due à des dégâts ou similaires d'une puce à semi-conducteurs lors de la manipulation, un appareil à semi-conducteurs de type laminé tridimensionnel pouvant ainsi être fabriqué simplement avec un boîtier de petite taille. L'appareil à semi-conducteurs selon l'invention (14) comporte une puce à semi-conducteurs (11) présentant une électrode de puce, un motif de câblage (16) destiné au montage de l'électrode de puce sur un côté, des résines moulées (12, 17) couvrant entièrement la puce à semi-conducteurs (11) et le motif de câblage (16), ainsi qu'une prise d'interconnexion (18) dont une extrémité met en contact un côté du motif de câblage (16), et l'autre extrémité fait saillie par rapport aux résines moulées, l'autre côté du motif de câblage (16) étant exposé à la surface des résines moulées.
PCT/JP2002/012362 2001-11-27 2002-11-27 Appareil a semi-conducteurs, procede de fabrication, et appareil a semi-conducteurs de type lamine tridimensionnel WO2003046987A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001-361366 2001-11-27
JP2001361366A JP2003163324A (ja) 2001-11-27 2001-11-27 ユニット半導体装置及びその製造方法並びに３次元積層型半導体装置

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WO2003046987A1 true WO2003046987A1 (fr) 2003-06-05

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PCT/JP2002/012362 WO2003046987A1 (fr) 2001-11-27 2002-11-27 Appareil a semi-conducteurs, procede de fabrication, et appareil a semi-conducteurs de type lamine tridimensionnel

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Country Link
JP (1) JP2003163324A (fr)
WO (1) WO2003046987A1 (fr)

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JP4871572B2 (ja) * 2005-11-10 2012-02-08 ローム株式会社 半導体装置及び半導体装置の製造方法
JP4899603B2 (ja) * 2006-04-13 2012-03-21 ソニー株式会社 三次元半導体パッケージ製造方法
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