WO2003013201A1 - Procede de fabrication de tampon de reception de dispositif de carte a circuit imprime multicouche - Google Patents

Procede de fabrication de tampon de reception de dispositif de carte a circuit imprime multicouche Download PDF

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Publication number
WO2003013201A1
WO2003013201A1 PCT/KR2001/001480 KR0101480W WO03013201A1 WO 2003013201 A1 WO2003013201 A1 WO 2003013201A1 KR 0101480 W KR0101480 W KR 0101480W WO 03013201 A1 WO03013201 A1 WO 03013201A1
Authority
WO
WIPO (PCT)
Prior art keywords
forming
conductive layer
landing pad
forming device
via hole
Prior art date
Application number
PCT/KR2001/001480
Other languages
English (en)
Inventor
Seong Heon Lee
Original Assignee
Dap Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dap Corporation filed Critical Dap Corporation
Publication of WO2003013201A1 publication Critical patent/WO2003013201A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0047—Drilling of holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0347—Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H05K2201/09518—Deep blind vias, i.e. blind vias connecting the surface circuit to circuit layers deeper than the first buried circuit layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0094—Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061—Etching masks
    • H05K3/064—Photoresists
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Definitions

  • This invention relates to a method for forming device-landing pad of
  • PCB printed circuit board
  • BGA Grid Array
  • a PCB is a primary based device of electronic components being manufactured in the various fields at present.
  • the multi-layered PCB is a primary based device of electronic components being manufactured in the various fields at present.
  • the multi-layered PCB is a primary based device of electronic components being manufactured in the various fields at present.
  • the conventional method comprises essentially
  • processes a1-a9 the step of forming a via hole by using a laser drill through the processes a10-a18, and forming a exposed conductive pattern for interconnecting through the processes a19-a23.
  • a substrate having multi-layered conductive patterns can be
  • the step of forming the via hole comprises the steps of forming a
  • FIG. 2a is a photograph showing the multi-layered PCB
  • Fig. 2b is an enlarged photo
  • FIG. 3 is an enlarged cross-sectional view of
  • the present invention has been made in an effort to solve the above
  • An object of the present invention is to provide a method for forming
  • PCB printed circuit board
  • Another object of the present invention is to provide a method for forming device-landing pad of multi-layered PCB capable of improving an electric connection reliability of components by enhancing the conductivity of an
  • landing pad of multi-layered PCB including the step of forming at least one via
  • the method comprising the steps of: forming a first external
  • the method for forming device-landing pad according to the present invention further comprises a step of grinding the via for flattening a surface of the via.
  • invention further comprises a step of forming a second external conductive layer over the first external conductive layer and the via.
  • Fig. 1a to Fig. 1g show respective processes for illustrating the method
  • Fig. 2a is a photograph showing the multi-layered PCB manufactured by the prior art
  • Fig. 2b is an enlarged photograph showing a portion A of Fig. 2a.
  • Fig. 3 is a cross-sectional view of the via hole formed on the multi- layered PCB of Fig. 2a
  • Fig. 4a to Fig. 4h show respective processes for illustrating the method
  • Fig. 5a is a photograph showing device-landing pads of the multi-layered
  • Fig. 5b is an enlarged photograph showing a portion B of Fig. 5a.
  • Fig. 6 is a cross-sectional view of device-landing pad formed on the multi-layered PCB of Fig. 5a.
  • layered PCB having the conductive pattern over at least three layers.
  • the present invention discloses the conductive pattern formed with
  • Fig. 4a to Fig. 4h show respective processes for illustrating the method for forming device-landing pad of the multi-layered PCB according to a preferred embodiment of the present invention.
  • pad of the multi-layered PCB comprises the steps of forming a first conductive
  • the via hole 1 13 is formed at the laser point 112 using the
  • the first external conductive layer 114 is formed over the surface
  • the third conductive layer 1 10 is connected to the first or second conductive pattern 103a or 107a at
  • the via hole 1 13 is plugged with conductive material such as silver
  • external conductive layer 121 is formed over the surface of the first external conductive layer 114 and the via 120 by the copper plating again at the process b22.
  • a photoresist film 115 is applied over a surface of the second
  • photoresist film 1 15 so as to forming a masking layer at the process b24.
  • conductive pattern 121a, 1 14a, and 1 10a is formed, and then the photoresist film 1 15 is
  • solder-resist 116 is deposited on the etch back portion of the
  • Fig. 5a is a photograph showing device-landing pads of the multi-layered
  • Fig. 5b is an enlarged photograph
  • Fig. 6 is a cross-sectional view of the
  • the device-landing pad for mounting electronic component is flatten by plugging the via hole. This enlarges the contacting
  • the via hole formed on the multi-layered PCB for interconnecting the conductive patterns is plugged and flatten in the present invention such that the contacting surface of the device-landing pad is enlarged, the soldering can be reliably performed, and it is possible to prevent the sold liquid from being flowed into the neighbor via hole and the printing ink from sputtering during the screen printing process.
  • the via hole is plugged with the conductive material and the device landing pad is reinforced by the second external conductive layer formed by the copper plating, electric connectivity between the device landing pad and the component is enhanced, resulting in improving component performance reliability.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

La présente invention concerne un procédé de fabrication de tampon de réception de dispositif de carte à circuit imprimé (PCB) multicouche, et plus particulièrement un procédé de fabrication de tampon de réception de dispositif d'une PCB multicouche par le colmatage d'un trou d'interconnexion formé par perçage au laser destiné à la réception du dispositif et/ou par la formation d'un trou d'interconnexion et d'une couche conductrice. Pour réaliser les objectifs de cette invention, ce procédé de fabrication de tampon de réception de dispositif de PCB multicouche consiste à former au moins un trou d'interconnexion de façon à interconnecter différents tracés de couche conductrice. Ce procédé consiste: à former une première couche conductrice externe à la surface de la PCB multicouche possédant le trou d'interconnexion, à former une interconnexion par colmatage du trou d'interconnexion, à former une couche de masquage sur une surface de la couche conductrice, à regraver la première couche conductrice externe de façon à former un tracé conducteur et à retirer la couche de masquage.
PCT/KR2001/001480 2001-08-02 2001-08-31 Procede de fabrication de tampon de reception de dispositif de carte a circuit imprime multicouche WO2003013201A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR2001/46850 2001-08-02
KR1020010046850A KR20030011433A (ko) 2001-08-02 2001-08-02 다층 인쇄회로기판의 숨겨진 레이저 비아홀 제조방법

Publications (1)

Publication Number Publication Date
WO2003013201A1 true WO2003013201A1 (fr) 2003-02-13

Family

ID=19712822

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2001/001480 WO2003013201A1 (fr) 2001-08-02 2001-08-31 Procede de fabrication de tampon de reception de dispositif de carte a circuit imprime multicouche

Country Status (2)

Country Link
KR (1) KR20030011433A (fr)
WO (1) WO2003013201A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1545175A2 (fr) * 2003-12-18 2005-06-22 Endicott Interconnect Technologies, Inc. Procédé de fabrication d'un panneau à circuit imprimé avec des trous conducteurs et le panneau ainsi obtenu
CN102026471B (zh) * 2009-09-18 2013-05-08 欣兴电子股份有限公司 线路板及其制造方法
CN103428993A (zh) * 2012-05-18 2013-12-04 揖斐电株式会社 布线板及其制造方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100509201B1 (ko) * 2003-04-22 2005-08-18 주식회사 디에이피 다층 인쇄회로기판의 제조방법
KR100965341B1 (ko) * 2007-12-20 2010-06-22 삼성전기주식회사 인쇄회로기판의 제조방법
CN112566374B (zh) * 2020-11-16 2022-07-12 奥士康科技股份有限公司 一种pcb双面机械背钻孔防焊塞孔的控制方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5627345A (en) * 1991-10-24 1997-05-06 Kawasaki Steel Corporation Multilevel interconnect structure
US6015520A (en) * 1997-05-15 2000-01-18 International Business Machines Corporation Method for filling holes in printed wiring boards
KR20000052162A (ko) * 1999-01-30 2000-08-16 정해원 다층 피씨비 및 그 제조방법
US6190493B1 (en) * 1995-07-05 2001-02-20 Hitachi, Ltd. Thin-film multilayer wiring board and production thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5627345A (en) * 1991-10-24 1997-05-06 Kawasaki Steel Corporation Multilevel interconnect structure
US6190493B1 (en) * 1995-07-05 2001-02-20 Hitachi, Ltd. Thin-film multilayer wiring board and production thereof
US6015520A (en) * 1997-05-15 2000-01-18 International Business Machines Corporation Method for filling holes in printed wiring boards
KR20000052162A (ko) * 1999-01-30 2000-08-16 정해원 다층 피씨비 및 그 제조방법

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1545175A2 (fr) * 2003-12-18 2005-06-22 Endicott Interconnect Technologies, Inc. Procédé de fabrication d'un panneau à circuit imprimé avec des trous conducteurs et le panneau ainsi obtenu
EP1545175A3 (fr) * 2003-12-18 2007-05-30 Endicott Interconnect Technologies, Inc. Procédé de fabrication d'un panneau à circuit imprimé avec des trous conducteurs et le panneau ainsi obtenu
CN102026471B (zh) * 2009-09-18 2013-05-08 欣兴电子股份有限公司 线路板及其制造方法
CN103428993A (zh) * 2012-05-18 2013-12-04 揖斐电株式会社 布线板及其制造方法
US9480157B2 (en) 2012-05-18 2016-10-25 Ibiden Co., Ltd. Wiring board and method for manufacturing the same

Also Published As

Publication number Publication date
KR20030011433A (ko) 2003-02-11

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