Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/93—Batch processes
  • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
  • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
  • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
  • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
  • H01L21/561—Batch processing
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
  • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
  • H01L23/3157—Partial encapsulation or coating
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/10—Bump connectors; Manufacturing methods related thereto
  • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
  • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
  • H01L2224/161—Disposition
  • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
  • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
  • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
  • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
  • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
  • H01L2224/321—Disposition
  • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
  • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
  • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
  • H01L2224/732—Location after the connecting process
  • H01L2224/73201—Location after the connecting process on the same surface
  • H01L2224/73203—Bump and layer connectors
  • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01005—Boron [B]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01006—Carbon [C]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01013—Aluminum [Al]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01015—Phosphorus [P]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01029—Copper [Cu]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01033—Arsenic [As]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01075—Rhenium [Re]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/10—Details of semiconductor or other solid state devices to be connected
  • H01L2924/11—Device type
  • H01L2924/14—Integrated circuits

Definitions

• the present invention relates generally to microelectronic assemblies having an integrated circuit die attached to a substrate by a plurality of solder connections, and more specifically relates to a microelectronic assembly having a bead of polymeric material disposed about the periphery of the integrated circuit die.
• the bead of polymeric material connects the die to the substrate and operates to reduce breakage of the die and electrical connections.
• FCOB assembly an integrated circuit die is provided which includes a plurality of bond pads, with each of the bond pads having deposited thereon a solder bump.
• the die is turned over or flipped and is superimposed over a substrate having a plurality of bond pads, such that each of the solder bumps is aligned with a corresponding one of the bond pads on the substrate.
• the die and the substrate are then reflow-soldered together to form solder connections.
• the gap that remains between the downwardly facing die face and the upwardly facing substrate face is then filled using any one of a number of known underfill materials.
• the underfill material which typically contains silica or other particulates in a resin binder, serves to encapsulate the solder connections and serves to bond the die to the substrate.
• the underfill also increases the reliability of the microelectronic assembly during thermal cycling by enhancing the mechanical connection between the die and the substrate thereby mitigating the effects of thermal expansion problems.
• Semiconductor dies are formed of an inflexible material that does not bend easily or resist multiple bending cycles. When mounted on a circuit board, a die will tend to break most often near the edge of the device when the board is flexed.
• the circuit board of hand-held devices may flex frequently from activation of buttons and rough handling during manufacturing and operation. Since electrical connections between the die and the board are often located near or at the edge of the die, the outermost located connections themselves are particularly vulnerable to failing when subjected to bending loads.
• One prior art method of applying an underfill material has been to simply apply the underfill material to the assembly after the reflow soldering has been completed.
• the underfill material is drawn into the gap between the die and the substrate by capillary action.
• the assembly is then placed in an oven for curing.
• a small radius of underfill material referred to as a fillet, adheres between the substrate and the lower edge portions of the die.
• An alternate example of using an underfill material includes first attaching a die to a substrate, tilting the assembly and allowing underfill material to flow under the die by the force of gravity. In both examples, since the epoxy becomes located for the most part underneath the body of the die, the peripheral edges or portions of the die are left relatively unsupported and vulnerable to stress.
• a different method of bonding a semiconductor chip to a substrate uses a vacuum chamber to evacuate the gap between the chip and the substrate.
• a polymeric underfill material is forced into the gap when air is allowed to re- enter the chamber.
• a technique of producing a die with high resistance to stress is obtained by providing a die within a package that also includes a base plate and cap.
• the die is adhesively attached to the base plate and a cap is affixed to the base plate such that an air gap is formed between the die and the cap.
• the base plate and die assembly is mounted to a substrate, such as a circuit board.
• the base plate tends to absorb stresses preferentially.
• the methods described above do, to some extent, decrease the possibility of die and interconnect breakage due to stress by providing different means to support the die.
• these methods require additional manufacturing steps, materials and equipment.
• encapsulating the die may itself exert stresses on the die, may be disadvantageous to marking techniques and may decrease the effective operating life of the die by reducing the capacity of the die to dissipate heat.
• FIG. 1 is a cross-sectional view of a microelectronic assembly constructed in accordance with the teachings of an embodiment of the present invention
• FIG. 2 is a cross-sectional view of a microelectronic assembly of another embodiment of the present invention.
• FIG. 3 is a side view of a semiconductor wafer positioned on a sheet of adhesive backing material;
• FIG. 4 is a side view of the wafer on the backing material as shown in
• FIG. 3 after the wafer has been separated into individual die
• FIG. 5 is a side view of the dies and backing material of FIG. 4 with enlarged streets;
• FIG. 6 is a side view of the dies and backing material of FIG. 5 with the streets filled with a polymeric precursor material
• FIG. 7 is a side view of dies and backing material as shown in FIG. 6 after being re- separated into individual die with a bead of polymeric material located at the outer edges of each die.
• FIG. 1 illustrates a cross-sectional view of a microelectronic assembly constructed in accordance with the teachings of an embodiment of the present invention.
• the microelectronic assembly 10 includes an integrated circuit die 12 of the type generally well known in the art.
• the die 12 includes a die body 14, a die face 16, and a plurality of lateral edge portions 18.
• the die 12 has circuitry formed thereon (not shown) as is well known, and also includes a plurality of bond pads (not shown) both disposed on the die face 16 with solder bumps 30 formed thereon.
• the die 12 is typically mass produced from a silicon wafer (not shown) which has formed thereon a plurality of integrated circuit dies which are diced, sawn, separated or otherwise singulated into one or more dies 12 as is well known in the art.
• the substrate may be formed of standard substrate materials including ceramic, epoxy board, paper/epoxy/glass laminates, composites, flex, polyimide, polyester, and FEP (Teflon) materials and may include a stiffener layer of copper, aluminum, or an alloy material.
• Pluralities of bond pads (not shown) are spaced about the die attach surface 24. It should be understood that the bond pads on the die and the bond pads on the surface 24 of the substrate 22 are designed to line up or index to each other to provide electrical connection therebetween.
• solder connections are typically formed from solder bumps 30 which are deposited on either each of the bond pads of the die 12 or on each of the bond pads of the substrate 22 - . prior to assembly of the microelectronic assembly 10.
• the solder connections are formed from the solder bumps 30 after the die 12 is positioned over the substrate 22 and properly aligned, typically by using the reflow soldering method as is known.
• a polymeric bead 32 is disposed about the periphery of the outer edges of the die.
• a number of precursor materials are suitable for use in forming the polymeric bead.
• the bead 32 materials may consist of an epoxy prepolymer, which hardens in the presence of heat, i.e. a thermoset.
• the polymeric precursor material may consist of 60-
• a prepolymer typically an epoxy prepolymer
• 20-40% by weight of a hardener 0.1-1.0% by weight of a catalyst, and 0.01-0.10% by weight of an adhesion promoter.
• the material may further include a range of filler between about 25% to about 75% by weight of particulate fillers, typically silica.
• Epoxy formulations typically include a hardener that reacts with the precursor to form the product resin.
• a suitable hardener is an amine- terminated polyether compound, preferably triethyleneglycol diamine.
• the hardener may contain in its molecular structure two or more 2,5-dialkyl substituted furan group or two or more dienophiles (alkynes having electron withdrawing groups attached to both sides of the ethyne moiety e.g. ester and keto groups).
• suitable hardeners are isocyanates, melamines, aziridines, and anhydrides.
• a catalyst is typically added to promote reaction of the constituents during curing.
• a preferred catalyst is 2-phenylimidazole.
• Other suitable catalysts are amines, acids and anhydrides.
• the adhesion promoter is an aminosilane that enhances wetting of the substrate to promote adhesion of the resultant encapsulant.
• a preferred adhesion promoter is gamma-aminopropyltriethoxysilane.
• Other suitable adhesion promoters are fluoropolymers and silicones.
• Such a thermoset material is preferably partially curable to a B stage polymer to form an essentially non-flowing bead 32 (i.e., a bead exhibiting some shear strength).
• the thermoset material is preferably fully curable at - reflow temperatures to form the bead.
• the fully cured material is known as having been C staged.
• the polymer precursor may contain moieties of a 2,5- dialkyl substituted furan instead of epoxy end groups.
• a polymer precursor material is available from Shell®, a more complete description of which may be found in U.S. Patent No. 5,760,337 issued to Iyer and assigned to Shell®.
• the bead 32 includes a thermoplastic polymer, such as a phenoxy resin.
• phenoxy resin is Paphen manufactured by Phenoxy Associates.
• thermoplastic materials which soften in the presence of heat, may be employed as long as such thermoplastics exhibit a softening point below the melting point of the solder material.
• the bead 32 appears to be shown as two elements, the present embodiment preferably contemplates that the bead is in the form of a substantially continuous bead, buttress, skirt or the like which is attached to the outer or peripheral edges of the die 12 and also attached to the surface 24 of the substrate 22.
• the bead 32 may be formed on less than all the outer edges of the die. In this manner, the microelectronic assembly may be used in applications where space is limited or less structural support is needed, for example.
• the bead has a rectangular or square cross-section. Other cross-sections are also contemplated, such as round and oval cross-sections.
• the bead 32 attaches to most, or all, of the edge surface 18 of the die 12 portion of the assembly 10. Attaching the bead 32 to a major portion of the edge surface 18 functions to support the edge of the die 12, and operates to absorb stresses which otherwise would be experienced directly by the die or the interconnect. Further, in the present embodiment, the exposed surface 34 of the bead is substantially coplanar with the die back surface 15.
• FIG. 2 illustrates a cross-sectional view of a microelectronic assembly constructed in accordance with the teachings of another embodiment of the present invention. In FIG.
• the microelectronic assembly 100 has generally the same features as that shown in FIG. 1 with the exception of the bead 42.
• Bead 42 differs from bead 32 (see FIG. 1) in that the bead material also fills gap 28.
• the bead 42 not only surrounds the die 12, but also fills the gap 28 between the die 12 and the substrate 22.
• the assembly 100 includes both bead material about the outer edges 18 of the die 12 and bead material in the gap 28 of the assembly 100.
• FIGS. 3-7 a method of forming the microelectronic assembly of the present invention is illustrated. As shown in FIG.
• a semiconductor wafer 202 formed by standard methods is placed on an adhesive backing material 204.
• the wafer 202 is positioned with the active surface 216 facing outwardly such that the active surface 216 and the bond pads (not shown) formed thereon are in an exposed condition.
• solder bumps 230 are formed on the bond pads on the active surface 216 of the wafer 202 using well-known methods.
• the wafer is separated into a plurality of individual dies 212A, 212B, 212C using known methods.
• a preferred method of dicing the wafer is sawing.
• semiconductor wafers include a number of integrated circuits arranged in rows and columns with the periphery of each integrated circuit or die being rectangular.
• the wafer is sawn or "diced" into rectangular shaped discrete dies along two mutually perpendicular sets of parallel lines or streets 250A lying between each of the rows and columns thereof.
• the separated or singulated integrated circuits are commonly referred to as dice or die.
• the lanes between the die are referred to as streets.
• stretching the backing material 204 expands the streets 250B (see FIG. 5).
• the expanded streets 250B are filled with a polymeric precursor material 232 (see FIG. 6).
• the diced wafer 212A, 212B, 212C, polymeric precursor material 232 and backing are preferably heated to partially cure or B stage the material. If a thermosetting material is used, it is allowed to cool or set up.
• the streets 250C are re-sawn which re-separate the individual die 212A, 212B, 212C (see FIG. 7). The die is selected, scanned for alignment, and superimposed over the substrate.
• the die With each solder bump in alignment with a corresponding bond pad, the die may be then tacked to the substrate using a vaporizable flux having a tacking agent.
• the subassembly is then heated to reflow in an oven (i.e., at least to the liquidus point of the solder material).
• the bumps 230 can be formed on the substrate or on both the substrate and die.
• the solder bumps aided by the fluxing agents form the solder connections.
• the bead flows, droops or expands in the presence of heat to contact and connect to the substrate. Exposure to the reflow temperature causes the bead to form a bond with the die and substrate.
• the reflow temperature also may cause the bead to become C staged or fully cured when the bead material includes a thermoset material.

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• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Wire Bonding (AREA)

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• 2001
  • 2001-03-28 US US09/819,393 patent/US6562663B2/en not_active Expired - Lifetime
• 2002
  • 2002-02-22 WO PCT/US2002/005431 patent/WO2002080229A2/en not_active Ceased
  • 2002-02-22 EP EP02706385A patent/EP1504468A4/en not_active Withdrawn
  • 2002-02-22 JP JP2002578545A patent/JP4422411B2/ja not_active Expired - Fee Related
• 2003
  • 2003-04-02 US US10/405,383 patent/US20040002181A1/en not_active Abandoned

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