WO2002078181A1 - High frequency amplifier - Google Patents

High frequency amplifier Download PDF

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Publication number
WO2002078181A1
WO2002078181A1 PCT/JP2001/004287 JP0104287W WO02078181A1 WO 2002078181 A1 WO2002078181 A1 WO 2002078181A1 JP 0104287 W JP0104287 W JP 0104287W WO 02078181 A1 WO02078181 A1 WO 02078181A1
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WO
WIPO (PCT)
Prior art keywords
amplifier
input signal
peak
average power
power
Prior art date
Application number
PCT/JP2001/004287
Other languages
French (fr)
Japanese (ja)
Inventor
Kenichi Horiguchi
Masatoshi Nakayama
Yukio Ikeda
Osami Ishida
Yuuji Sakai
Kazuyuki Totani
Original Assignee
Mitsubishi Denki Kabushiki Kaisha
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Denki Kabushiki Kaisha filed Critical Mitsubishi Denki Kabushiki Kaisha
Publication of WO2002078181A1 publication Critical patent/WO2002078181A1/en

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Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189High-frequency amplifiers, e.g. radio frequency amplifiers
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03GCONTROL OF AMPLIFICATION
    • H03G3/00Gain control in amplifiers or frequency changers
    • H03G3/20Automatic control
    • H03G3/30Automatic control in amplifiers having semiconductor devices
    • H03G3/3036Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers

Definitions

  • the present invention relates to a high-frequency amplifier for amplifying a high-frequency signal.
  • FIG. 1 is a block diagram showing the configuration of a conventional high-frequency amplifier disclosed in the literature, Stephen A. Maas, "Nonlinear Microwave Circuits,” Artech House, 1988, where 1 denotes a high-frequency input.
  • An amplifier for amplifying the signal 2 is a power supply circuit for supplying a gate voltage Vg and a drain voltage Vd to the amplifier 1, 3 is an input terminal, and 4 is an output terminal.
  • FIG. 2 is a diagram showing a temporal change of input power in an input signal.
  • the input signal input to the input terminal 3 has an input signal M having a peak input power P peak 1 in a certain time zone T 1 with respect to the average input power P ave.
  • the input signal N of the input power Ppeak2 is input.
  • the ratio of the peak output power P peak to the average input power P ave of peak P Peak / P av is the peak-average power ratio Pr
  • the beak-average power ratio Pr changes with the input signals M and N. I do.
  • FIG. 3 is a diagram showing an average output power characteristic and a distortion power characteristic with respect to an average input power of a conventional high-frequency amplifier.
  • 101 is the average power characteristic
  • 210 is the distortion power characteristic when the input signal M is input to the amplifier 1
  • 202 is the distortion power characteristic when the input signal N is input to the amplifier 1.
  • the gate voltage V gl and the drain voltage V dl are supplied to the amplifier 1 from the path 2.
  • the distortion power when the average output power P1 is output from the amplifier 1 is D1 when the input signal M is input to the amplifier 1, and the input signal N is input when the input signal N is input to the amplifier 1. Is D2. That is, when the input signal changes from the input signal M to the input signal N, the peak-average power ratio Pr increases, and the distortion power increases from D1 to D2.
  • the conventional high-frequency amplifier is configured as described above, if the input signal changes and the peak-to-average power ratio Pr changes when amplifier 1 outputs the average output power P a V e, When the power changes and the input signal N having a large peak-to-average power ratio p r is input to the amplifier 1, the distortion power increases.
  • the present invention has been made to solve the above problems, and has as its object to obtain a high-frequency amplifier capable of suppressing a change in output distortion power even when the peak-to-average power ratio Pr changes. And Disclosure of the invention
  • the high-frequency amplifier includes an amplifier that amplifies an input signal, a peak-average power ratio detected by detecting a peak power and an average power of the input signal, and a calculated peak-average power ratio and a predetermined reference value.
  • An input signal discriminating circuit for instructing to control the gate voltage or the drain voltage supplied to the amplifier based on the comparison result, and a peak signal of the input signal based on an instruction from the input signal discriminating circuit.
  • a voltage control circuit that controls a gate voltage or a drain voltage supplied to the amplifier so that the distortion power output from the amplifier does not change even if the average power ratio changes. As a result, even if the peak-to-average power ratio of the input signal changes, there is an effect that a change in distortion power output from the amplifier can be suppressed.
  • the input signal discriminating circuit includes an average power detecting circuit that detects an average power of the input signal, a peak power detecting circuit that detects a beak power of the input signal, and the average power detecting circuit.
  • a power ratio calculating circuit that calculates a peak-to-average power ratio based on the average power of the input signal detected by the above and the peak power detection circuit, based on the beak power of the input signal detected by the peak power detecting circuit;
  • the peak-to-average power ratio calculated by the circuit is compared with a predetermined reference value, and based on the comparison result, the voltage control circuit controls the gate voltage or the drain voltage supplied to the amplifier.
  • a comparison circuit for instructing is provided.
  • the peak-to-average power ratio calculated by the input signal discriminating circuit when the peak-to-average power ratio calculated by the input signal discriminating circuit is higher than a predetermined reference value, the peak-to-average power ratio is set to a predetermined value.
  • the gate voltage supplied to the amplifier is increased as compared with the case where the reference voltage is lower than the reference value.
  • the peak-to-average power ratio is higher than the predetermined reference value.
  • the drain voltage supplied to the amplifier is increased as compared with the case where the voltage is lower.
  • a high-frequency amplifier includes: an amplifier for amplifying an input signal; Detect the peak power and average power of the signal to calculate the peak-to-average power ratio, compare the calculated peak-to-average power ratio with a predetermined reference value, and based on the comparison result, the gate to be supplied to the amplifier.
  • Input signal discriminating circuit that instructs to control the voltage and drain voltage, and distortion power output from the amplifier even if the peak-to-average power ratio of the input signal changes based on the instruction from the input signal discriminating circuit.
  • a voltage control circuit for controlling a gate voltage and a drain voltage supplied to the amplifier so that the voltage does not change.
  • the input signal discriminating circuit includes an average power detecting circuit for detecting an average power of the input signal, a beak power detecting circuit for detecting a beak power of the input signal, and the average power detecting circuit.
  • a power ratio calculating circuit for calculating a peak-to-average power ratio based on the average power of the input signal detected by the input signal and the peak power of the input signal detected by the peak power detecting circuit; The peak-average power ratio calculated by the circuit is compared with a predetermined reference value, and the voltage control circuit is instructed to control the gate voltage and the drain voltage supplied to the amplifier based on the comparison result. And a comparison circuit.
  • the peak-average power ratio is set to a predetermined reference value.
  • the gate voltage supplied to the amplifier is increased, and the drain voltage supplied to the amplifier is increased.
  • the peak-to-average power ratio is higher than the predetermined reference value.
  • the gate voltage supplied to the amplifier is increased, and the drain voltage supplied to the amplifier is reduced.
  • the peak-to-average power ratio when the voltage control circuit determines that the peak-to-average power ratio is higher than the predetermined reference value, the peak-to-average power ratio is higher than the predetermined reference value.
  • the gate voltage supplied to the amplifier is reduced and the drain voltage supplied to the amplifier is increased, as compared with the case where the voltage is lower.
  • a high-frequency amplifier includes: an amplifier that amplifies an input signal; and external instruction information such as a type of an input signal input to the amplifier and a magnitude of an average output power output from the amplifier.
  • This has a voltage control circuit for controlling. Thus, even if the content of the external instruction information changes, it is possible to suppress a change in the distortion power output from the amplifier.
  • FIG. 1 is a block diagram showing a configuration of a conventional high-frequency amplifier.
  • FIG. 2 is a diagram showing a temporal change of input power in an input signal of a conventional high-frequency amplifier.
  • FIG. 3 is a diagram showing an average output power characteristic and a distortion power characteristic with respect to an average input power of a conventional high-frequency amplifier.
  • FIG. 4 is a block diagram showing a configuration of the high-frequency amplifier according to Embodiment 1 of the present invention.
  • FIG. 5 is a diagram showing an average output power characteristic and a distortion power characteristic with respect to an average input power of the high-frequency amplifier according to Embodiment 1 of the present invention.
  • FIG. 6 is a block diagram showing a configuration of a high-frequency amplifier according to Embodiment 2 of the present invention.
  • FIG. 7 is a diagram showing an average output power characteristic and a distortion power characteristic with respect to an average input power of the high-frequency amplifier according to Embodiment 2 of the present invention.
  • FIG. 8 is a block diagram showing a configuration of a high-frequency amplifier according to Embodiment 3 of the present invention.
  • FIG. 9 is a diagram showing average output power characteristics and distortion power characteristics with respect to average input power of the high-frequency amplifier according to Embodiment 3 of the present invention.
  • FIG. 10 is a diagram showing another average output power characteristic with respect to the average input power of the high-frequency amplifier according to Embodiment 3 of the present invention.
  • FIG. 11 is a block diagram showing a configuration of a high-frequency amplifier according to Embodiment 4 of the present invention.
  • FIG. 12 is a block diagram showing a configuration of a high-frequency amplifier according to Embodiment 4 of the present invention.
  • FIG. 13 is a block diagram showing a configuration of a high-frequency amplifier according to Embodiment 4 of the present invention.
  • FIG. 4 is a block diagram showing a configuration of the high-frequency amplifier according to Embodiment 1 of the present invention.
  • 5 is a directional coupler that extracts a part of the input signal
  • 6 is the peak power P peak and the average power P ave of the input signal extracted from the directional coupler 5, and the peak and average power is detected.
  • Calculates the ratio Pr compares the calculated peak-to-average power ratio Pr with a predetermined reference value Ps, and, based on the result of the comparison, instructs to control the gate voltage Vg supplied to the amplifier 1.
  • a signal determination circuit 7 is a gate voltage control circuit (voltage control circuit) that controls a gate voltage Vg supplied from the power supply circuit 2 to the amplifier 1 based on an instruction of the input signal determination circuit 6.
  • 11 is an average power detecting circuit for detecting the average power P a V e of the input signal extracted from the directional coupler 5
  • 12 is the directional coupler 5.
  • the peak power detection circuit 13 detects the peak power P peak of the input signal extracted from the input signal, and 13 denotes the average power P a V e of the input signal detected by the average power detection circuit 11, and the peak power detection circuit 12
  • the peak-to-average power ratio Pr is compared with a predetermined reference value Ps, and the gate voltage Vg supplied to the amplifier 1 is supplied to the gate voltage control circuit 7 based on the comparison result. This is a comparison circuit that instructs to control.
  • Input signals M and N as shown in FIG. 2 are input from the input terminal 3, input to the amplifier 1 via the directional coupler 5, and the amplified signal is output from the output terminal 4.
  • two kinds of gate voltages Vg are supplied from the power supply circuit 2 to the amplifier 1 through the gate voltage control circuit 7, but the amplifier 1 uses the gate voltage Vgl. Is supplied, amplification is performed by Class B operation to increase power supply efficiency, and when the gate voltage Vg2 is supplied, amplification by Class A operation is performed to improve distortion. ing.
  • the input signal extracted from the directional coupler 5 is input to the input signal discrimination circuit 6.
  • the average power detecting circuit 11 detects the average power P ave of the input signal
  • the peak power detecting circuit 12 detects the peak power P peak of the input signal.
  • the comparison circuit 14 compares the peak-to-average power ratio Pr calculated by the power ratio calculation circuit 13 with a predetermined reference value Ps. For example, when the input signal M is input to the input terminal 3, If the peak-to-average power ratio Pr is smaller than the predetermined reference value Ps, the gate voltage control circuit 7 is instructed to supply the amplifier 1 with the predetermined gate voltage Vg1. When the input signal N is input to the input terminal 3 and the peak-to-average power ratio Pr is larger than a predetermined reference value Ps, the amplifier 1 is separated from the gate voltage control circuit 7 by the amplifier 1. To supply the predetermined gate voltage Vg2 of the above.
  • the gate voltage control circuit 7 supplies the gate voltage V g1 or V g 2 to the amplifier 1 based on the instruction from the comparison circuit 14.
  • the amplifier 1 performs amplification processing by class B operation to increase power supply efficiency, and when the gate voltage V g 2 is supplied, the amplifier A class A to improve distortion. Performs amplification by operation.
  • FIG. 5 is a diagram showing an average output power characteristic and a distortion power characteristic with respect to an average input power of the high-frequency amplifier according to Embodiment 1 of the present invention.
  • reference numeral 101 denotes an input signal M input and a gate voltage V Average output power characteristics at gl
  • 201 Distortion power characteristics when input signal M is input to amplifier 1 and gate voltage Vgl
  • 202 Gate when input signal N is input to amplifier 1 This is the distortion power characteristic when the voltage is Vgl
  • the average output power characteristic 101 and the distortion power characteristics 201 and 202 are the same as those in FIG.
  • 102 is the average output power characteristic when the input signal N is input and the gate voltage is Vg2
  • 203 is the average output power characteristic when the input signal N is input to the amplifier 1 and the gate voltage Vg2. It is assumed that the drain voltage Vdl is supplied from the power supply circuit 2 to the amplifier 1.
  • the beak 'average power ratio Pr is smaller than the predetermined reference value Ps, and the gate voltage Vg1 is supplied to the amplifier 1
  • the average output power characteristic is 101
  • the distortion power characteristic is 201
  • the peak-to-average power ratio Pr is larger than the predetermined reference value Ps
  • the gate voltage Vg2 is supplied to the amplifier 1
  • the average output power characteristic becomes In 102
  • the distortion power characteristic is 203
  • the distortion power when the average output power is P1 is D1 as in the case where the input signal M is input. That is, the distortion power D when the gate voltage V 1
  • the distortion power is improved to D 1 from 2.
  • the gate voltage control circuit 7 has a gate voltage V gl for obtaining an average output power characteristic 101 and a distortion power characteristic 210 for an input signal M, and an average output power characteristic for an input signal N.
  • the gate voltage Vg2 is set in advance so as to obtain the power characteristic 102 and the distortion power characteristic 203, and the gate voltage control circuit 7 is set based on the instruction from the comparison circuit 14.
  • the selected gate voltage V g1 or V g2 is supplied to the amplifier 1.
  • the gate voltage V gl when obtaining the average output power characteristic 101 increases the gate voltage V gl when obtaining the average output power characteristic 101 and increase the gate voltage V gl g 2, that is, the drain current of the amplifier 1 is increased, and the gain may be changed in a direction to increase the gain of the amplifier 1.
  • the gate voltage V gl when obtaining the distortion power characteristic 202 is increased to be the gate voltage V g2.
  • the amplifier 1 may be changed from the amplification processing of the class B operation to the amplification processing of the class A operation, and the amplifier 1 performs the amplification processing of the class A operation, so that the distortion power characteristic 200 3 As described above, the distortion power is improved.
  • the gate voltage Vg supplied to the amplifier 1 is controlled.
  • the effect that the change in the distortion power output from the amplifier 1 can be suppressed is obtained.
  • FIG. 6 is a block diagram showing a configuration of a high-frequency amplifier according to Embodiment 2 of the present invention.
  • reference numeral 8 denotes a power supply circuit 2 that supplies power to amplifier 1 based on an instruction from input signal discrimination circuit 6.
  • the drain voltage control circuit (voltage control circuit) controls the drain voltage Vd.
  • Other configurations are embodiments This is equivalent to the configuration in FIG.
  • the configuration of the input signal discrimination circuit 6 is the same as the configuration of FIG. 4 in the first embodiment, but the input signal discrimination circuit 6 has a peak-to-average power ratio Pr and a predetermined reference value Ps. And instructs the drain voltage control circuit 8 to control the drain voltage Vd supplied to the amplifier 1 based on the comparison result.
  • Input signals M and N as shown in FIG. 2 are input from input terminal 3, input to amplifier 1 via directional coupler 5, and the amplified signal is output from output terminal 4.
  • two types of drain voltages V d are supplied from the power supply circuit 2 to the amplifier 1 via the drain voltage control circuit 8, but the amplifier 1 When the drain voltage Vd2 is supplied, the saturation power is set to be higher than when the drain voltage Vd1 is supplied.
  • the input signal extracted from the directional coupler 5 is input to the input signal discriminating circuit 6 and processed in the same manner as in the first embodiment. That is, the average power detection circuit 11 detects the average power P a Ve of the input signal, the peak power detection circuit 12 detects the peak power P peak of the input signal, and the power ratio calculation circuit 13 detects the peak power P peak. ⁇ Calculate the average power ratio Pr.
  • the comparison circuit 14 compares the calculated peak-to-average power ratio Pr with a predetermined reference value Ps.For example, when the input signal M is input to the input terminal 3, the peak-to-average power ratio pr is determined. If it is smaller than the reference value P s, the drain voltage control circuit 8 is instructed to supply a predetermined drain voltage Vd 1 to the amplifier 1. When the input signal N is input to the input terminal 3 and the peak-to-average power ratio pr is larger than a predetermined reference value Ps, another predetermined voltage is supplied to the drain voltage control circuit 8 to the amplifier 1. Drain power Instruct to supply pressure Vd2.
  • the drain voltage control circuit 8 supplies the drain voltage Vd1 or Vd2 to the amplifier 1 based on the instruction from the comparison circuit 14.
  • the saturation power increases when the drain voltage Vd1 is supplied.
  • FIG. 7 is a diagram showing an average output power characteristic and a distortion power characteristic with respect to an average input power of the high-frequency amplifier according to the second embodiment of the present invention.
  • 101 denotes an input signal M input and a drain voltage V Average output power characteristic at dl
  • 210 is distortion power characteristic at the time when the input signal M is input to the amplifier 1 and the drain voltage is Vd1
  • 220 is the input signal N when the input signal N is input to the amplifier 1.
  • the average output power characteristic 101 and the distortion power characteristics 201 and 202 are the same as those in FIG. 5 of the first embodiment.
  • 103 is the average output power characteristic when the input signal N is input and the drain voltage is Vd2
  • 204 is the average output power characteristic when the input signal N is input to the amplifier 1 and the drain voltage is This is the distortion power characteristic at V d 2, and it is assumed that the gate voltage V g 1 is supplied from the power supply circuit 2 to the amplifier 1.
  • the peak-to-average power ratio Pr is smaller than the predetermined reference value Ps, and the drain voltage Vd1 is supplied to the amplifier 1.
  • the average output power characteristic is 101
  • the distortion power characteristic is 201
  • the distortion power when the average output power is P 1 is D 1 ⁇
  • the distortion power D 2 is improved from the distortion power D 2 at the drain voltage V dl to the distortion power D 1.
  • the drain voltage control circuit 8 has a drain voltage V d 1 for obtaining an average output power characteristic 101 and a distortion power characteristic 201 for an input signal M, and a drain voltage V d 1 for an input signal N.
  • the drain voltage Vd2 is set in advance so that the average output power characteristic 103 and the distortion power characteristic 204 can be obtained, and the drain voltage control circuit 8 operates based on the instruction from the comparison circuit 14. Then, the set drain voltage Vd1 or Vd2 is selected and supplied to the amplifier 1.
  • the drain voltage Vd1 when obtaining the average output power characteristic 101 is increased by increasing the drain voltage Vd1.
  • d 2 that is, the direction in which the saturation power of the amplifier 1 increases.
  • the drain voltage Vd1 when the distortion power characteristic 202 is obtained is increased to increase the drain voltage.
  • V d 2 that is, the direction in which the saturation power of the amplifier 1 increases may be changed.
  • FIG. 8 is a block diagram showing a configuration of a high-frequency amplifier according to Embodiment 3 of the present invention.
  • Embodiment 3 is a combination of Embodiments 1 and 2, and has a gate voltage control.
  • Circuit 7 voltage control circuit
  • drain It has an in-voltage control circuit 8 (voltage control circuit). That is, the input signal discrimination circuit 6 compares the peak-average power ratio Pr with a predetermined reference value Ps, and based on the comparison result, provides the gate voltage control circuit 7 and the drain voltage control circuit 8 with: Instructs to control the gate voltage Vg and the drain voltage Vd supplied to the amplifier 1.
  • Input signals M and N as shown in FIG. 2 are input from input terminal 3, input to amplifier 1 via directional coupler 5, and the amplified signal is output from output terminal 4.
  • the amplifier 1 When the gate voltage V g1 is supplied, the amplifier 1 performs amplification processing by class B operation to increase power supply efficiency, and when the gate voltage V g2 is supplied, the amplifier 1 performs A amplification to improve distortion.
  • the saturation power is set to be higher than when the drain voltage V d1 is supplied.
  • the input signal extracted from the directional coupler 5 is input to the input signal discriminating circuit 6 and processed in the same manner as in the first embodiment. That is, the average power detection circuit 11 detects the average power PaVe of the input signal, the beak power detection circuit 12 detects the peak power Ppeak of the input signal, and the power ratio calculation circuit 13 detects the peak power Ppeak. ⁇ Calculate the average power ratio Pr.
  • the comparison circuit 14 compares the calculated peak-to-average power ratio Pr with a predetermined reference value Ps.For example, when the input signal M is input to the input terminal 3 and the peak-to-average power ratio pr is If it is smaller than the reference value P s, a predetermined gate voltage V g 1 is supplied to the amplifier 1 by the gate voltage control circuit 7. The drain voltage control circuit 8 is instructed to supply a predetermined drain voltage V d1 to the amplifier 1. When the input signal N is input to the input terminal 3 and the peak-to-average power ratio Pr is larger than a predetermined reference value Ps, another predetermined gate is supplied to the amplifier 1 with respect to the gate voltage control circuit 7. The voltage Vg2 instructs the drain voltage control circuit 8 to supply another predetermined drain voltage Vd2 to the amplifier 1.
  • the gate voltage control circuit 7 supplies the gate voltage V g1 or V g 2 to the amplifier 1 based on the instruction from the comparison circuit 14.
  • the amplifier 1 performs amplification processing by class B operation to increase power supply efficiency, and when the gate voltage V g 2 is supplied, the amplifier A class A to improve distortion. Performs amplification by operation.
  • the drain voltage control circuit 8 supplies the drain voltage Vd1 or Vd2 to the amplifier 1 based on an instruction from the comparison circuit 14. When the amplifier 1 is supplied with the drain voltage V d2, the saturation power increases whenever the drain voltage V d1 is supplied.
  • FIG. 9 is a diagram showing an average output power characteristic and a distortion power characteristic with respect to an average input power of the high-frequency amplifier according to Embodiment 3 of the present invention.
  • reference numeral 101 denotes a gate when an input signal M is input.
  • Average output power characteristics at voltage V g 1 and drain voltage V d 1, 210 is distortion when input signal M is input to amplifier 1 and gate voltage V gl and drain voltage V d 1
  • the power characteristic, 202 is the distortion power characteristic when the input signal N is input to the amplifier 1 and the gate voltage Vg1 and the drain voltage Vdl, and the average output power characteristic 101, the distortion power characteristic 201 and 202 have the same characteristics as FIG. 5 of the first embodiment.
  • reference numeral 104 denotes an average output power characteristic when the input signal N is input and the gate voltage Vg2 and the drain voltage Vd2, and 205 denotes the input signal N to the amplifier 1.
  • These are the distortion power characteristics when the gate voltage V g 2 and the drain voltage V d 2 are input.
  • the peak-to-average power ratio Pr is smaller than the predetermined reference value Ps, and the gate voltage Vgl and the drain voltage Vd1 are supplied to the amplifier 1.
  • the average output power characteristic is 101
  • the distortion power characteristic is 201
  • the distortion power when the average output power is P1 is D1.
  • the distortion power D2 is improved to the distortion power D1 from the distortion power D2 at the gate voltage Vg1 and the drain voltage Vdl.
  • the gate voltage control circuit 7 and the drain voltage control circuit 8 have a gate voltage V g1 and a drain voltage V such that the average output power characteristic 101 and the distortion power characteristic 201 can be obtained for the input signal M.
  • the gate voltage Vg2 and the drain voltage Vd2 are set so that the average output power characteristic 104 and the distortion power characteristic 205 are obtained when the input signal is N. ing.
  • the gate voltage control circuit 7 and the drain voltage control circuit 8 determine the set gate voltage V g1 or V g2 and the set drain voltage V d1 or V d based on the instruction from the comparison circuit 14. Select 2 and supply to amplifier 1 ⁇
  • the gate voltage Vgl when the average output power characteristic 101 is obtained is increased to obtain the gate voltage Vg2. That is, by increasing the drain current of the amplifier 1 to increase the gain of the amplifier 1 and increasing the drain voltage V d 1 when the average output power characteristic 101 is obtained.
  • the drain voltage may be Vd 2, that is, the drain voltage may be changed so that the saturation power of the amplifier 1 increases.
  • the gate voltage Vg1 when obtaining the distortion power characteristic 202 is increased to increase the gate voltage Vg2. That is, the amplifier 1 is changed from the amplification processing of the class B operation to the amplification processing of the class A operation, and the drain voltage Vd1 when the distortion power characteristic 202 is obtained is increased to increase the drain voltage.
  • the voltage may be Vd2, that is, the voltage may be changed in a direction to increase the saturation power of the amplifier 1.
  • the gate voltage Vg1 is increased to the gate voltage Vg2, and the drain voltage Vd1 is increased to the drain voltage Vd2, so that the amplifier 1 performs the amplification process of the class A operation.
  • the output back-off of the amplifier 1 increases, and the distortion power is improved as indicated by the distortion power characteristic 205.
  • FIG. 10 is a diagram showing another average output power characteristic with respect to the average input power of the high-frequency amplifier according to Embodiment 3 of the present invention.
  • the average output power characteristics 101 and 104 are the same as those in FIG. It has the same characteristics as in Fig. 9.
  • the gate signal Vg1 when the input signal N is input and the average output power characteristic 101 is obtained is increased to the gate voltage Vg2, that is, the drain of the amplifier 1 is increased.
  • the amplifier current is increased to increase the gain of the amplifier 1, and the drain voltage Vdl when the average output power characteristic 101 is obtained is reduced to the drain voltage Vd2 to obtain the amplifier voltage. This was changed so that the saturation power of 1 decreased.
  • reference numeral 106 denotes a gate voltage Vg2 by reducing the gate voltage Vgl when the input signal N is input and obtaining the average output power characteristic 101. That is, by reducing the drain current of the amplifier 1, In addition to changing the gain of the amplifier 1 to decrease, the drain voltage Vd1 when the average output power characteristic 101 is obtained is increased to the drain voltage Vd2, that is, the saturation power of the amplifier 1 Is changed to increase.
  • the gate voltage Vg2 and the drain voltage Vd are set so that even when the input signal N is input, the same distortion power as the distortion power D1 when the input signal M is input is obtained.
  • the same distortion power as the distortion power D1 when the input signal M is input is obtained.
  • Embodiment 4 As described above, according to the third embodiment, even if the peak-to-average power ratio Pr of the input signal changes, the gate voltage Vg and the drain voltage Vd supplied to the amplifier 1 are controlled. However, the effect that the change in the distortion power output from the amplifier 1 can be suppressed is obtained. Embodiment 4.
  • FIGS. 11, 12, and 13 are block diagrams showing the configuration of a high frequency amplifier according to Embodiment 4 of the present invention.
  • reference numeral 9 denotes an external input to input terminal 3. This is a control terminal for inputting external instruction information such as the type of input signal to be input and the average output power of the amplifier 1 output from the output terminal 4.
  • the gate voltage control circuit 7 voltage control circuit
  • the voltage control circuit 8 voltage control circuit
  • the other configurations are the same as the configurations of the same reference numerals in FIGS. 4, 6, and 8 in each of the above embodiments. Next, the operation will be described.
  • Fig. 11 Fig. 12, and Fig. 13
  • external instructions such as the type of input signal input to input terminal 3 and the magnitude of average output power of amplifier 1 output from output terminal 4 Information is input to the control terminal 9 from outside.
  • the type of the input signal is information indicating whether the input signal is the input signal M or the input signal N in each of the above embodiments, and the magnitude of the average output power is the normal average output power or the normal output power. This is information indicating whether the average output power is higher.
  • the gate voltage control circuit 7 and the drain voltage control circuit 8 determine whether the signal input to the control terminal 9 and input to the input terminal 3 is the input signal M
  • the gate voltage V g and the drain voltage V d can be changed by the external instruction information indicating whether the input signal N is input or the input signal N. Is controlled to be the distortion power D1 when the input signal M is input.
  • the gate voltage control circuit 7 and the drain voltage control circuit 8 determine whether the average output power is the normal average output power input to the control terminal 9.
  • the gate voltage V g and the drain voltage V d are determined by the external instruction information indicating whether the average output power is higher than the normal output power. Control is performed so that the distortion power at the time of power becomes D1.
  • the gate voltage V g or the drain voltage V d, or the gate voltage V g and the drain voltage By controlling the voltage Vd, an effect of suppressing a change in the distortion power output from the amplifier 1 can be obtained.
  • the gate voltage Vg and the drain voltage Vd are controlled in two steps, but the input signal and the average output power are three or more types, and the gate voltage Vg and the drain voltage Vd are controlled by three levels. It is also possible to control more than stages.
  • the amplifier 1 is described as a source-grounded amplifier, but may be a gate-grounded or drain-grounded amplifier. Further, in each of the above embodiments, the amplifier 1 is described as a field-effect transistor, but may be a transistor. Industrial applicability
  • the high-frequency amplifier according to the present invention is suitable for suppressing a change in the output distortion power even when the peak-to-average power ratio of the input signal changes.

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Abstract

A high frequency amplifier comprising an amplifier (1) for amplifying an input signal, an input signal discriminating circuit (6) for issuing instructions to detect the peak and average powers of the input signal to calculate the peak-average power ratio, to make a comparison between the calculated peak-average power ratio and a predetermined reference value, and to control a gate voltage to be fed to the amplifier (1) on the basis of the result of the comparison, and a gate voltage control circuit (7) for controlling a gate voltage to be fed to the amplifier (1) on the basis of instructions from the input signal discriminating circuit (6) in such a manner that even if the peak-average power ratio of the input signal varies, the distortion power fed from the amplifier (1) does not vary.

Description

明 細 書 高周波増幅器 技術分野  Description High-frequency amplifier Technical field
この発明は高周波信号を増幅する高周波増幅器に関するものである。 背景技術  The present invention relates to a high-frequency amplifier for amplifying a high-frequency signal. Background art
第 1図は、 文献、 Stephen A. Maas, "Nonlinear Microwave Circuit s," Artech House, 1988 に開示されている従来の高周波増幅器の構 成を示すブロック図であり、 図において、 1は高周波の入力信号を増幅 する増幅器、 2は増幅器 1にゲート電圧 V g、 ドレイ ン電圧 Vdを供給 する電源回路、 3は入力端子、 4は出力端子である。  FIG. 1 is a block diagram showing the configuration of a conventional high-frequency amplifier disclosed in the literature, Stephen A. Maas, "Nonlinear Microwave Circuits," Artech House, 1988, where 1 denotes a high-frequency input. An amplifier for amplifying the signal, 2 is a power supply circuit for supplying a gate voltage Vg and a drain voltage Vd to the amplifier 1, 3 is an input terminal, and 4 is an output terminal.
次に動作について説明する。  Next, the operation will be described.
第 2図は入力信号における入力電力の時間的変化を示す図である。 入 力端子 3に入力される入力信号は、 第 2図に示すように、 平均入力電力 P av eに対して、 ある時間帯 T 1ではピーク入力電力 P p e a k 1の 入力信号 Mが入力され、 別の時間帯 T 2には入力電力 P p e a k 2の入 力信号 Nが入力されるものとする。 ヒの平均入力電力 P a v eに対する ピーク出力電力 P p e a kの比 P p e ak/P av eをピーク · アベレ ージ電力比 P rとすると、 ビーク · アベレージ電力比 P rは入力信号 M , Nにより変化する。  FIG. 2 is a diagram showing a temporal change of input power in an input signal. As shown in FIG. 2, the input signal input to the input terminal 3 has an input signal M having a peak input power P peak 1 in a certain time zone T 1 with respect to the average input power P ave. In another time zone T2, it is assumed that the input signal N of the input power Ppeak2 is input. Assuming that the ratio of the peak output power P peak to the average input power P ave of peak P Peak / P av is the peak-average power ratio Pr, the beak-average power ratio Pr changes with the input signals M and N. I do.
第 3図は従来の高周波増幅器の平均入力電力に対する平均出力電力特 性と歪電力特性を示す図である。 図において、 1 0 1は平均電力特性、 2 0 1は入力信号 Mが増幅器 1に入力されたときの歪電力特性、 2 0 2 は入力信号 Nが増幅器 1に入力されたときの歪電力特性であり、 電源回 路 2からゲー ト電圧 V g l、 ドレイ ン電圧 V d lが増幅器 1 にそれそれ 供給されているものとする。 FIG. 3 is a diagram showing an average output power characteristic and a distortion power characteristic with respect to an average input power of a conventional high-frequency amplifier. In the figure, 101 is the average power characteristic, 210 is the distortion power characteristic when the input signal M is input to the amplifier 1, and 202 is the distortion power characteristic when the input signal N is input to the amplifier 1. And the power times It is assumed that the gate voltage V gl and the drain voltage V dl are supplied to the amplifier 1 from the path 2.
第 3図に示すように、 増幅器 1から平均出力電力 P 1 を出力する際の 歪電力は、 入力信号 Mが増幅器 1 に入力されたときが D 1で、 入力信号 Nが増幅器 1 に入力されたときが D 2である。 すなわち、 入力信号が、 入力信号 Mから入力信号 Nに変化すると、 ピーク · アベレージ電力比 P rが大き くなり、 歪電力が D 1から D 2に増加する。  As shown in Fig. 3, the distortion power when the average output power P1 is output from the amplifier 1 is D1 when the input signal M is input to the amplifier 1, and the input signal N is input when the input signal N is input to the amplifier 1. Is D2. That is, when the input signal changes from the input signal M to the input signal N, the peak-average power ratio Pr increases, and the distortion power increases from D1 to D2.
従来の高周波増幅器は以上のように構成されているので、 増幅器 1 が 平均出力電力 P a V eを出力している際に、 入力信号が変化しビーク · アベレージ電力比 P rが変化すると、 歪電力が変化してしまい、 ピーク • アベレージ電力比 p rの大きな入力信号 Nが増幅器 1 に入力されると 、 歪電力は増加してしまう という課題があった。 Since the conventional high-frequency amplifier is configured as described above, if the input signal changes and the peak-to-average power ratio Pr changes when amplifier 1 outputs the average output power P a V e, When the power changes and the input signal N having a large peak-to-average power ratio p r is input to the amplifier 1, the distortion power increases.
この発明は上記のような課題を解決するためになされたもので、 ピー ク · アベレージ電力比 P rが変化しても、 出力される歪電力の変化を抑 制できる高周波増幅器を得ることを目的とする。 発明の開示  The present invention has been made to solve the above problems, and has as its object to obtain a high-frequency amplifier capable of suppressing a change in output distortion power even when the peak-to-average power ratio Pr changes. And Disclosure of the invention
この発明に係る高周波増幅器は、 入力信号を増幅する増幅器と、 入力 信号のピーク電力と平均電力を検知してビーク · アベレージ電力比を算 出し、 算出したピーク · アベレージ電力比と所定の基準値とを比較し、 比較した結果に基づき、 上記増幅器に供給するゲー ト電圧又は ドレイ ン 電圧を制御するよう指示する入力信号判別回路と、 上記入力信号判別回 路による指示に基づき、 入力信号のピーク · アベレージ電力比が変化し ても、 上記増幅器から出力される歪電力が変化しないように、 上記増幅 器に供給するゲー ト電圧又は ドレイ ン電圧を制御する電圧制御回路とを 備えたものである。 このことによ り、 入力信号.のピーク · アベレージ電力比が変化しても 、 増幅器から出力される歪電力の変化を抑制できるという効果がある。 The high-frequency amplifier according to the present invention includes an amplifier that amplifies an input signal, a peak-average power ratio detected by detecting a peak power and an average power of the input signal, and a calculated peak-average power ratio and a predetermined reference value. An input signal discriminating circuit for instructing to control the gate voltage or the drain voltage supplied to the amplifier based on the comparison result, and a peak signal of the input signal based on an instruction from the input signal discriminating circuit. A voltage control circuit that controls a gate voltage or a drain voltage supplied to the amplifier so that the distortion power output from the amplifier does not change even if the average power ratio changes. As a result, even if the peak-to-average power ratio of the input signal changes, there is an effect that a change in distortion power output from the amplifier can be suppressed.
この発明に係る高周波増幅器は、 入力信号判別回路が、 入力信号の平 均電力を検出する平均電力検出回路と、 入力信号のビーク電力を検出す るピーク電力検出回路と、 上記平均電力検出回路によ り検出された入力 信号の平均電力と、 上記ピーク電力検出回路によ り検出された入力信号 のビーク電力に基づき、 ピーク · アベレージ電力比を算出する電力比算 出回路と、 上記電力比算出回路によ り算出されたピーク · アベレージ電 力比と所定の基準値を比較し、 比較した結果に基づき、 電圧制御回路に 対して、 増幅器に供給するゲー ト電圧又は ドレイ ン電圧を制御するよう 指示する比較回路とを備えたものである。  In the high-frequency amplifier according to the present invention, the input signal discriminating circuit includes an average power detecting circuit that detects an average power of the input signal, a peak power detecting circuit that detects a beak power of the input signal, and the average power detecting circuit. A power ratio calculating circuit that calculates a peak-to-average power ratio based on the average power of the input signal detected by the above and the peak power detection circuit, based on the beak power of the input signal detected by the peak power detecting circuit; The peak-to-average power ratio calculated by the circuit is compared with a predetermined reference value, and based on the comparison result, the voltage control circuit controls the gate voltage or the drain voltage supplied to the amplifier. And a comparison circuit for instructing.
このことによ り、 入力信号のピーク · アベレージ電力比が変化しても 、 増幅器から出力される歪電力の変化を抑制できるという効果がある。  As a result, even if the peak-to-average power ratio of the input signal changes, there is an effect that the change in the distortion power output from the amplifier can be suppressed.
この発明に係る高周波増幅器は、 電圧制御回路が、 入力信号判別回路 によ り算出されたピーク · アベレージ電力比が所定の基準値よ り高い場 合に、 ピ一ク · アベレージ電力比が所定の基準値より低い場合よ りも、 上記増幅器に供給するゲ一 ト電圧を増加させるものである。  In the high-frequency amplifier according to the present invention, when the peak-to-average power ratio calculated by the input signal discriminating circuit is higher than a predetermined reference value, the peak-to-average power ratio is set to a predetermined value. The gate voltage supplied to the amplifier is increased as compared with the case where the reference voltage is lower than the reference value.
このことによ り、 入力信号のピーク · アベレージ電力比が変化しても 、 増幅器から出力される歪電力の変化を抑制できるという効果がある。  As a result, even if the peak-to-average power ratio of the input signal changes, there is an effect that the change in the distortion power output from the amplifier can be suppressed.
この発明に係る高周波増幅器は、 電圧制御回路が、 入力信号判別回路 によ り算出されたピーク · アベレージ電力比が所定の基準値よ り高い場 合に、 ピーク · アベレージ電力比が所定の基準値よ り低い場合よ りも、 上記増幅器に供給する ドレイ ン電圧を増加させるものである。  In the high frequency amplifier according to the present invention, when the voltage control circuit has a peak-to-average power ratio that is higher than a predetermined reference value, the peak-to-average power ratio is higher than the predetermined reference value. The drain voltage supplied to the amplifier is increased as compared with the case where the voltage is lower.
このことによ り、 入力信号のビーク · アベレージ電力比が変化しても 、 増幅器から出力される歪電力の変化を抑制できるという効果がある。  As a result, even if the peak-to-average power ratio of the input signal changes, there is an effect that the change in the distortion power output from the amplifier can be suppressed.
この発明に係る高周波増幅器は、 入力信号を増幅する増幅器と、 入力 信号のピーク電力と平均電力を検知してピーク · アベレージ電力比を算 出し、 算出したピーク · アベレージ電力比と所定の基準値とを比較し、 比較した結果に基づき、 上記増幅器に供給するゲー ト電圧及びドレイ ン 電圧を制御するよう指示する入力信号判別回路と、 上記入力信号判別回 路による指示に基づき、 入力信号のピーク ' アベレージ電力比が変化し ても、 上記増幅器から出力される歪電力が変化しないように、 上記増幅 器に供給するゲート電圧及びドレイ ン電圧を制御する電圧制御回路とを 備えたものである。 A high-frequency amplifier according to the present invention includes: an amplifier for amplifying an input signal; Detect the peak power and average power of the signal to calculate the peak-to-average power ratio, compare the calculated peak-to-average power ratio with a predetermined reference value, and based on the comparison result, the gate to be supplied to the amplifier. Input signal discriminating circuit that instructs to control the voltage and drain voltage, and distortion power output from the amplifier even if the peak-to-average power ratio of the input signal changes based on the instruction from the input signal discriminating circuit. And a voltage control circuit for controlling a gate voltage and a drain voltage supplied to the amplifier so that the voltage does not change.
このことによ り、 入力信号のピーク · アベレージ電力比が変化しても 、 増幅器から出力される歪電力の変化を抑制できるという効果がある。  As a result, even if the peak-to-average power ratio of the input signal changes, there is an effect that the change in the distortion power output from the amplifier can be suppressed.
この発明に係る高周波増幅器は、 入力信号判別回路が、 入力信号の平 均電力を検出する平均電力検出回路と、 入力信号のビーク電力を検出す るビーク電力検出回路と、 上記平均電力検出回路によ り検出された入力 信号の平均電力と、 上記ピーク電力検出回路によ り検出された入力信号 のピーク電力に基づき、 ピーク · アベレージ電力比を算出する電力比算 出回路と、 上記電力比算出回路により算出されたピーク · アベレージ電 力比と所定の基準値を比較し、 比較した結果に基づき、 電圧制御回路に 対して、 増幅器に供給するゲー ト電圧及びドレイ ン電圧を制御するよう 指示する比較回路とを備えたものである。  In the high frequency amplifier according to the present invention, the input signal discriminating circuit includes an average power detecting circuit for detecting an average power of the input signal, a beak power detecting circuit for detecting a beak power of the input signal, and the average power detecting circuit. A power ratio calculating circuit for calculating a peak-to-average power ratio based on the average power of the input signal detected by the input signal and the peak power of the input signal detected by the peak power detecting circuit; The peak-average power ratio calculated by the circuit is compared with a predetermined reference value, and the voltage control circuit is instructed to control the gate voltage and the drain voltage supplied to the amplifier based on the comparison result. And a comparison circuit.
このことによ り、 入力信号のピーク · アベレージ電力比が変化しても 、 増幅器から出力される歪電力の変化を抑制できるという効果がある。  As a result, even if the peak-to-average power ratio of the input signal changes, there is an effect that the change in the distortion power output from the amplifier can be suppressed.
この発明に係る高周波増幅器は、 電圧制御回路が、 入力信号判別回路 によ り算出されたピーク · アベレージ電力比が所定の基準値よ り高い場 合に、 ピーク · アベレージ電力比が所定の基準値よ り低い場合よ り も、 上記増幅器に供給するゲ一 ト電圧を増加させると共に、 上記増幅器に供 給する ドレイ ン電圧を増加させるものである。 このことによ り、 入力信号のピーク · アベレージ電力比が変化しても 、 増幅器から出力される歪電力の変化を抑制できるという効果がある。 In the high-frequency amplifier according to the present invention, when the voltage-control circuit has a peak-average power ratio calculated by the input signal determination circuit that is higher than a predetermined reference value, the peak-average power ratio is set to a predetermined reference value. Compared to a lower case, the gate voltage supplied to the amplifier is increased, and the drain voltage supplied to the amplifier is increased. As a result, even if the peak-to-average power ratio of the input signal changes, there is an effect that the change in the distortion power output from the amplifier can be suppressed.
この発明に係る高周波増幅器は、 電圧制御回路が、 入力信号判別回路 によ り算出されたピーク · アベレージ電力比が所定の基準値よ り高い場 合に、 ピーク · アベレージ電力比が所定の基準値よ り低い場合よ り も、 上記増幅器に供給するゲート電圧を増加させると共に、 上記増幅器に供 給する ドレイ ン電圧を減少させるものである。  In the high frequency amplifier according to the present invention, when the voltage control circuit has a peak-to-average power ratio that is higher than a predetermined reference value, the peak-to-average power ratio is higher than the predetermined reference value. As compared with a lower case, the gate voltage supplied to the amplifier is increased, and the drain voltage supplied to the amplifier is reduced.
このことにより、 入力信号のピーク · アベレージ電力比が変化しても 、 増幅器から出力される歪電力の変化を抑制できるという効果がある。  As a result, even if the peak-to-average power ratio of the input signal changes, it is possible to suppress the change in the distortion power output from the amplifier.
この発明に係る高周波増幅器は、 電圧制御回路が、 入力信号判別回路 によ り算出されたビーク · アベレージ電力比が所定の基準値よ り高い場 合に、 ピーク · アベレージ電力比が所定の基準値よ り低い場合よりも、 上記増幅器に供給するゲート電圧を減少させると共に、 上記増幅器に供 給する ドレイ ン電圧を増加させるものである。  In the high frequency amplifier according to the present invention, when the voltage control circuit determines that the peak-to-average power ratio is higher than the predetermined reference value, the peak-to-average power ratio is higher than the predetermined reference value. In this case, the gate voltage supplied to the amplifier is reduced and the drain voltage supplied to the amplifier is increased, as compared with the case where the voltage is lower.
このことによ り、 入力信号のビーク · アベレージ電力比が変化しても 、 増幅器から出力される歪電力の変化を抑制できるという効果がある。  As a result, even if the peak-to-average power ratio of the input signal changes, there is an effect that the change in the distortion power output from the amplifier can be suppressed.
この発明に係る高周波増幅器は、 入力信号を増幅する増幅器と、 上記 増幅器に入力される入力信号の種類や上記増幅器から出力される平均出 力電力の大きさ等の外部指示情報を入力し、 入力された外部指示情報の 内容が変化しても、 上記増幅器から出力される歪電力が変化しないよう に、 上記増幅器に供給するゲー ト電圧若しくは ドレイ ン電圧、 又はゲ一 ト電圧及びドレイ ン電圧を制御する電圧制御回路とを備えたものである このことによって、 外部指示情報の内容が変化しても、 増幅器から出 力される歪電力の変化を抑制できるという効果がある。 図面の簡単な説明 A high-frequency amplifier according to the present invention includes: an amplifier that amplifies an input signal; and external instruction information such as a type of an input signal input to the amplifier and a magnitude of an average output power output from the amplifier. The gate voltage or drain voltage supplied to the amplifier, or the gate and drain voltages supplied to the amplifier, so that the distortion power output from the amplifier does not change even if the content of the external instruction information changes. This has a voltage control circuit for controlling. Thus, even if the content of the external instruction information changes, it is possible to suppress a change in the distortion power output from the amplifier. BRIEF DESCRIPTION OF THE FIGURES
第 1図は従来の高周波増幅器の構成を示すプロック図である。  FIG. 1 is a block diagram showing a configuration of a conventional high-frequency amplifier.
第 2図は従来の高周波増幅器の入力信号における入力電力の時間的変 化を示す図である。  FIG. 2 is a diagram showing a temporal change of input power in an input signal of a conventional high-frequency amplifier.
第 3図は従来の高周波増幅器の平均入力電力に対する平均出力電力特 性と歪電力特性を示す図である。  FIG. 3 is a diagram showing an average output power characteristic and a distortion power characteristic with respect to an average input power of a conventional high-frequency amplifier.
第 4図はこの発明の実施の形態 1 による高周波増幅器の構成を示すブ 口ック図である。  FIG. 4 is a block diagram showing a configuration of the high-frequency amplifier according to Embodiment 1 of the present invention.
第 5図はこの発明の実施の形態 1による高周波増幅器の平均入力電力 に対する平均出力電力特性と歪電力特性を示す図である。  FIG. 5 is a diagram showing an average output power characteristic and a distortion power characteristic with respect to an average input power of the high-frequency amplifier according to Embodiment 1 of the present invention.
第 6図はこの発明の実施の形態 2による高周波増幅器の構成を示すブ ロック図で.ある。  FIG. 6 is a block diagram showing a configuration of a high-frequency amplifier according to Embodiment 2 of the present invention.
第 7図はこの発明の実施の形態 2による高周波増幅器の平均入力電力 に対する平均出力電力特性と歪電力特性を示す図である。  FIG. 7 is a diagram showing an average output power characteristic and a distortion power characteristic with respect to an average input power of the high-frequency amplifier according to Embodiment 2 of the present invention.
第 8図はこの発明の実施の形態 3による高周波増幅器の構成を示すブ ロック図である。  FIG. 8 is a block diagram showing a configuration of a high-frequency amplifier according to Embodiment 3 of the present invention.
第 9図はこの発明の実施の形態 3による高周波増幅器の平均入力電力 に対する平均出力電力特性と歪電力特性を示す図である。  FIG. 9 is a diagram showing average output power characteristics and distortion power characteristics with respect to average input power of the high-frequency amplifier according to Embodiment 3 of the present invention.
第 1 0図はこの発明の実施の形態 3による高周波増幅器の平均入力電 力に対する他の平均出力電力特性を示す図である。  FIG. 10 is a diagram showing another average output power characteristic with respect to the average input power of the high-frequency amplifier according to Embodiment 3 of the present invention.
第 1 1図はこの発明の実施の形態 4による高周波増幅器の構成を示す ブロック図である。  FIG. 11 is a block diagram showing a configuration of a high-frequency amplifier according to Embodiment 4 of the present invention.
第 1 2図はこの発明の実施の形態 4による高周波増幅器の構成を示す ブロック図である。  FIG. 12 is a block diagram showing a configuration of a high-frequency amplifier according to Embodiment 4 of the present invention.
第 1 3図はこの発明の実施の形態 4による高周波増幅器の構成を示す ブロック図である。 発明を実施するための最良の形態 FIG. 13 is a block diagram showing a configuration of a high-frequency amplifier according to Embodiment 4 of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION
以下、 この発明をより詳細に説明するために、 この発明を実施するた めの最良の形態について、 添付の図面に従って説明する。  Hereinafter, in order to explain this invention in greater detail, the preferred embodiments of the present invention will be described with reference to the accompanying drawings.
実施の形態 1. Embodiment 1.
第 4図はこの発明の実施の形態 1による高周波増幅器の構成を示すブ ロック図である。 図において、 5は入力信号の一部を取り出す方向性結 合器、 6は方向性結合器 5から取り出された入力信号のピーク電力 P p e akと平均電力 P a v eを検知してビーク · アベレージ電力比 P rを 算出し、 算出したビーク · アベレージ電力比 P rと所定の基準値 P sと を比較し、 比較した結果に基づき、 増幅器 1に供給するゲート電圧 V g を制御するよう指示する入力信号判別回路、 7は入力信号判別回路 6の 指示に基づき、 電源回路 2から増幅器 1に供給するゲート電圧 V gを制 御するゲート電圧制御回路 (電圧制御回路) である。  FIG. 4 is a block diagram showing a configuration of the high-frequency amplifier according to Embodiment 1 of the present invention. In the figure, 5 is a directional coupler that extracts a part of the input signal, 6 is the peak power P peak and the average power P ave of the input signal extracted from the directional coupler 5, and the peak and average power is detected. Calculates the ratio Pr, compares the calculated peak-to-average power ratio Pr with a predetermined reference value Ps, and, based on the result of the comparison, instructs to control the gate voltage Vg supplied to the amplifier 1. A signal determination circuit 7 is a gate voltage control circuit (voltage control circuit) that controls a gate voltage Vg supplied from the power supply circuit 2 to the amplifier 1 based on an instruction of the input signal determination circuit 6.
また、 第 4図の入力信号判別回路 6において、 1 1は方向性結合器 5 から取り出された入力信号の平均電力 P a V eを検出する平均電力検出 回路、 1 2は方向性結合器 5から取り出された入力信号のピーク電力 P p e a kを検出するピーク電力検出回路、 1 3は平均電力検出回路 1 1 により検出された入力信号の平均電力 P a V eと、 ピーク電力検出回路 1 2により検出された入力信号のピーク電力 P p e a kに基づき、 ビ一 ク - アベレージ電力比 P r (=P p e a k/P a v e ) を算出する電力 比算出回路、 1 4は電力比算出回路 1 3により算出されたピーク · アベ レ一ジ電力比 P rと所定の基準値 P sとを比較し、 比較した結果に基づ き、 ゲート電圧制御回路 7に対して、 増幅器 1に供給するゲート電圧 V gを制御するよう指示する比較回路である。  In the input signal discriminating circuit 6 shown in FIG. 4, 11 is an average power detecting circuit for detecting the average power P a V e of the input signal extracted from the directional coupler 5, and 12 is the directional coupler 5. The peak power detection circuit 13 detects the peak power P peak of the input signal extracted from the input signal, and 13 denotes the average power P a V e of the input signal detected by the average power detection circuit 11, and the peak power detection circuit 12 A power ratio calculation circuit that calculates the peak-to-average power ratio Pr (= P peak / P ave) based on the detected peak power P peak of the input signal, and 14 is calculated by the power ratio calculation circuit 13 The peak-to-average power ratio Pr is compared with a predetermined reference value Ps, and the gate voltage Vg supplied to the amplifier 1 is supplied to the gate voltage control circuit 7 based on the comparison result. This is a comparison circuit that instructs to control.
第 4図において、 その他の構成は従来の第 1図における構成と同等で ある。 In Fig. 4, other configurations are the same as the conventional configuration in Fig. 1. is there.
次に動作について説明する。  Next, the operation will be described.
入力端子 3から第 2図に示すような入力信号 M, Nが入力され、 方向 性結合器 5を介して増幅器 1に入力され、 増幅された信号は出力端子 4 から出力される。 電源回路 2から増幅器 1に対し、 ド レイ ン電圧 Vd ( =Vd 1 ) が直接供給されている。 また、 電源回路 2から増幅器 1に対 し、 2種類のゲー ト電圧 Vg (二 Vg l又は Vg 2 ) がゲート電圧制御 回路 7を介して供給されるが、 増幅器 1は、 ゲー ト電圧 Vg lが供給さ れると、 電源効率を高めるために B級動作による増幅処理を行い、 ゲー ト電圧 V g 2が供給されると、 歪を改善するために A級動作による増幅 処理を行うよう設定されている。  Input signals M and N as shown in FIG. 2 are input from the input terminal 3, input to the amplifier 1 via the directional coupler 5, and the amplified signal is output from the output terminal 4. The drain voltage Vd (= Vd 1) is directly supplied from the power supply circuit 2 to the amplifier 1. In addition, two kinds of gate voltages Vg (two Vgl or Vg2) are supplied from the power supply circuit 2 to the amplifier 1 through the gate voltage control circuit 7, but the amplifier 1 uses the gate voltage Vgl. Is supplied, amplification is performed by Class B operation to increase power supply efficiency, and when the gate voltage Vg2 is supplied, amplification by Class A operation is performed to improve distortion. ing.
方向性結合器 5から取り出された入力信号は、 入力信号判別回路 6に 入力される。 入力信号判別回路 6では、 平均電力検出回路 1 1が入力信 号の平均電力 P av eを検出し、 ピーク電力検出回路 1 2が入力信号の ピーク電力 P p e a kを検出する。 電力比算出回路 1 3は平均電力検出 回路 1 1によ り検出された入力信号の平均電力 P av eと、 ピーク電力 検出回路 1 2により検出された入力信号のビーク電力 P p e akに基づ き、 ピーク . アベレージ電力比 P r (=P p e ak/P av e) を算出 する。  The input signal extracted from the directional coupler 5 is input to the input signal discrimination circuit 6. In the input signal discriminating circuit 6, the average power detecting circuit 11 detects the average power P ave of the input signal, and the peak power detecting circuit 12 detects the peak power P peak of the input signal. The power ratio calculation circuit 13 is based on the average power P ave of the input signal detected by the average power detection circuit 11 and the beak power P peak of the input signal detected by the peak power detection circuit 12. Then, calculate the peak-to-average power ratio Pr (= P peak / P ave).
比較回路 1 4は電力比算出回路 1 3によ り算出されたピーク · アベレ —ジ電力比 P rと所定の基準値 P sを比較し、 例えば、 入力端子 3に入 力信号 Mが入力され、 ピーク ' アベレージ電力比 P rが所定の基準値 P sよ り小さい場合には、 ゲート電圧制御回路 7に対して、 増幅器 1に所 定のゲー ト電圧 Vg 1を供給するよう指示する。 また、 入力端子 3に入 力信号 Nが入力され、 ピーク ' アベレージ電力比 P rが所定の基準値 P sよ り大きい場合には、 ゲー ト電圧制御回路 7に対して、 増幅器 1に別 の所定のゲート電圧 Vg 2を供給するよう指示する。 The comparison circuit 14 compares the peak-to-average power ratio Pr calculated by the power ratio calculation circuit 13 with a predetermined reference value Ps. For example, when the input signal M is input to the input terminal 3, If the peak-to-average power ratio Pr is smaller than the predetermined reference value Ps, the gate voltage control circuit 7 is instructed to supply the amplifier 1 with the predetermined gate voltage Vg1. When the input signal N is input to the input terminal 3 and the peak-to-average power ratio Pr is larger than a predetermined reference value Ps, the amplifier 1 is separated from the gate voltage control circuit 7 by the amplifier 1. To supply the predetermined gate voltage Vg2 of the above.
ゲート電圧制御回路 7は、 比較回路 1 4からの指示に基づき、 ゲート 電圧 V g 1又は V g 2を増幅器 1に供給する。 増幅器 1は、 ゲート電圧 V g 1が供給されると、 電源効率を高めるために B級動作による増幅処 理を行い、 ゲート電圧 V g 2が供給されると、 歪を改善するために A級 動作による増幅処理を行う。  The gate voltage control circuit 7 supplies the gate voltage V g1 or V g 2 to the amplifier 1 based on the instruction from the comparison circuit 14. When the gate voltage V g 1 is supplied, the amplifier 1 performs amplification processing by class B operation to increase power supply efficiency, and when the gate voltage V g 2 is supplied, the amplifier A class A to improve distortion. Performs amplification by operation.
第 5図はこの発明の実施の形態 1による高周波増幅器の平均入力電力 に対する平均出力電力特性と歪電力特性を示す図であり、 図において、 1 0 1は入力信号 Mが入力されてゲート電圧 V g lのときの平均出力電 力特性、 20 1は入力信号 Mが増幅器 1に入力されてゲート電圧 Vg l のときの歪電力特性、 2 0 2は入力信号 Nが増幅器 1に入力されてゲー ト電圧 Vg lのときの歪電力特性であり、 平均出力電力特性 1 0 1、 歪 電力特性 20 1 , 2 0 2は従来の第 3図と同じ特性である。  FIG. 5 is a diagram showing an average output power characteristic and a distortion power characteristic with respect to an average input power of the high-frequency amplifier according to Embodiment 1 of the present invention. In FIG. 5, reference numeral 101 denotes an input signal M input and a gate voltage V Average output power characteristics at gl, 201: Distortion power characteristics when input signal M is input to amplifier 1 and gate voltage Vgl, 202: Gate when input signal N is input to amplifier 1 This is the distortion power characteristic when the voltage is Vgl, and the average output power characteristic 101 and the distortion power characteristics 201 and 202 are the same as those in FIG.
また、 第 5図において、 1 0 2は入力信号 Nが入力されてゲート電圧 Vg 2のときの平均出力電力特性、 2 0 3は入力信号 Nが増幅器 1に入 力されてゲート電圧 Vg 2のときの歪電力特性であり、 電源回路 2から ドレイン電圧 Vd lが増幅器 1に供給されているものとする。  In FIG. 5, 102 is the average output power characteristic when the input signal N is input and the gate voltage is Vg2, and 203 is the average output power characteristic when the input signal N is input to the amplifier 1 and the gate voltage Vg2. It is assumed that the drain voltage Vdl is supplied from the power supply circuit 2 to the amplifier 1.
第 5図に示すように、 入力信号 Mが入力されて、 ビーク ' アベレージ 電力比 P rが所定の基準値 P sより小さく、 ゲート電圧 V g 1が増幅器 1に供給されている場合には、 平均出力電力特性が 1 0 1で、 歪電力特 性が 2 0 1であり、 平均出力電力が P 1のときの歪電力は D 1となる。 一方、 入力信号 Nが入力されて、 ピーク ' アベレージ電力比 P rが所 定の基準値 P sより大きく、 ゲート電圧 V g 2が増幅器 1に供給されて いる場合には、 平均出力電力特性が 1 0 2で、 歪電力特性が 2 0 3とな り、 平均出力電力が P 1のときの歪電力は、 入力信号 Mが入力された場 合と同様に D 1となる。 すなわち、 ゲート電圧 V 1の.ときの歪電力 D 2 よ り歪電力 D 1 に改善される。 As shown in FIG. 5, when the input signal M is input, the beak 'average power ratio Pr is smaller than the predetermined reference value Ps, and the gate voltage Vg1 is supplied to the amplifier 1, The average output power characteristic is 101, the distortion power characteristic is 201, and the distortion power when the average output power is P1 is D1. On the other hand, when the input signal N is input, the peak-to-average power ratio Pr is larger than the predetermined reference value Ps, and the gate voltage Vg2 is supplied to the amplifier 1, the average output power characteristic becomes In 102, the distortion power characteristic is 203, and the distortion power when the average output power is P1 is D1 as in the case where the input signal M is input. That is, the distortion power D when the gate voltage V 1 The distortion power is improved to D 1 from 2.
ゲート電圧制御回路 7には、 入力信号 Mの場合に、 平均出力電力特性 1 0 1 と歪電力特性 2 0 1が得られるようなゲー ト電圧 V g l と、 入力 信号 Nの場合に、 平均出力電力特性 1 0 2 と歪電力特性 2 0 3が得られ るようなゲー ト電圧 V g 2が予め設定されており、 ゲート電圧制御回路 7は、 比較回路 1 4からの指示に基づき、 設定されているゲー ト電圧 V g 1又は V g 2を選択して増幅器 1 に供給する。  The gate voltage control circuit 7 has a gate voltage V gl for obtaining an average output power characteristic 101 and a distortion power characteristic 210 for an input signal M, and an average output power characteristic for an input signal N. The gate voltage Vg2 is set in advance so as to obtain the power characteristic 102 and the distortion power characteristic 203, and the gate voltage control circuit 7 is set based on the instruction from the comparison circuit 14. The selected gate voltage V g1 or V g2 is supplied to the amplifier 1.
平均出力電力特性 1 0 1 に対して平均出力電力特性 1 0 2を得るため には、 平均出力電力特性 1 0 1 を得ているときのゲー ト電圧 V g l を増 加させてゲー ト電圧 V g 2 とし、 すなわち、 増幅器 1の ドレイ ン電流を 増加させて、 増幅器 1の利得を増加させる方向に変更すれば良い。 また 、 歪電力特性 2 0 2 に対して歪電力特性 2 0 3を得るためには、 歪電力 特性 2 0 2 を得ているときのゲート電圧 V g l を増加させてゲー ト電圧 V g 2 とし、 すなわち、 増幅器 1が B級動作の増幅処理から A級動作の 増幅処理になる方向に変更すれば良く、 増幅器 1 が A級動作の増幅処理 を行うことによ り、 歪電力特性 2 0 3のように歪電力が改善される。 以上のように、 この実施の形態 1 によれば、 入力信号のビーク · アベ レ一ジ電力比 P rが変化しても、 増幅器 1 に供給するゲー ト電圧 V gを 制御することによ り、 増幅器 1 から出力される歪電力の変化を抑制でき るという効果が得られる。 実施の形態 2 .  To obtain the average output power characteristic 102 from the average output power characteristic 101, increase the gate voltage V gl when obtaining the average output power characteristic 101 and increase the gate voltage V gl g 2, that is, the drain current of the amplifier 1 is increased, and the gain may be changed in a direction to increase the gain of the amplifier 1. Further, in order to obtain the distortion power characteristic 203 with respect to the distortion power characteristic 202, the gate voltage V gl when obtaining the distortion power characteristic 202 is increased to be the gate voltage V g2. That is, the amplifier 1 may be changed from the amplification processing of the class B operation to the amplification processing of the class A operation, and the amplifier 1 performs the amplification processing of the class A operation, so that the distortion power characteristic 200 3 As described above, the distortion power is improved. As described above, according to the first embodiment, even if the peak-to-average power ratio Pr of the input signal changes, the gate voltage Vg supplied to the amplifier 1 is controlled. Thus, the effect that the change in the distortion power output from the amplifier 1 can be suppressed is obtained. Embodiment 2
第 6図はこの発明の実施の形態 2 による高周波増幅器の構成を示すブ ロ ック図であ り、 図において、 8は入力信号判別回路 6の指示に基づき 、 電源回路 2から増幅器 1 に供給する ド レイ ン電圧 V dを制御する ド レ イ ン電圧制御回路 (電圧制御回路) である。 その他の構成は実施の形態 1の第 4図における構成と同等である。 また、 入力信号判別回路 6の構 成も、 実施の形態 1 における第 4図の構成と同等であるが、 入力信号判 別回路 6はビーク · アベレージ電力比 P r と所定の基準値 P s とを比較 し、 比較した結果に基づき、 ドレイ ン電圧制御回路 8に対して、 増幅器 1 に供給する ドレイ ン電圧 V dを制御するよう指示する。 FIG. 6 is a block diagram showing a configuration of a high-frequency amplifier according to Embodiment 2 of the present invention. In the drawing, reference numeral 8 denotes a power supply circuit 2 that supplies power to amplifier 1 based on an instruction from input signal discrimination circuit 6. The drain voltage control circuit (voltage control circuit) controls the drain voltage Vd. Other configurations are embodiments This is equivalent to the configuration in FIG. The configuration of the input signal discrimination circuit 6 is the same as the configuration of FIG. 4 in the first embodiment, but the input signal discrimination circuit 6 has a peak-to-average power ratio Pr and a predetermined reference value Ps. And instructs the drain voltage control circuit 8 to control the drain voltage Vd supplied to the amplifier 1 based on the comparison result.
次に動作について説明する。  Next, the operation will be described.
入力端子 3から第 2図に示すような入力信号 M, Nが入力され、 方向 性結合器 5を介して増幅器 1 に入力され、 増幅された信号は出力端子 4 から出力される。 電源回路 2から増幅器 1 に対し、 ゲー ト電圧 V g ( = V g 1 ) が直接供給されている。 また、 電源回路 2から増幅器 1 に対し 、 2種類の ドレイ ン電圧 V d ( = V d l又は V d 2 ) が ドレイ ン電圧制 御回路 8を介して供給されるが、 増幅器 1は、 ド レイ ン電圧 V d 2が供 給されると、 ドレイ ン電圧 V d 1のときよ り も飽和電力が増加するよう に設定されている。  Input signals M and N as shown in FIG. 2 are input from input terminal 3, input to amplifier 1 via directional coupler 5, and the amplified signal is output from output terminal 4. Gate voltage V g (= V g 1) is directly supplied from power supply circuit 2 to amplifier 1. Further, two types of drain voltages V d (= V dl or V d 2) are supplied from the power supply circuit 2 to the amplifier 1 via the drain voltage control circuit 8, but the amplifier 1 When the drain voltage Vd2 is supplied, the saturation power is set to be higher than when the drain voltage Vd1 is supplied.
方向性結合器 5から取り出された入力信号は、 入力信号判別回路 6 に 入力されて、 実施の形態 1 と同様に処理される。 すなわち、 平均電力検 出回路 1 1が入力信号の平均電力 P a V eを検出し、 ピーク電力検出回 路 1 2が入力信号のピーク電力 P p e a kを検出し、 電力比算出回路 1 3はピーク · アベレージ電力比 P rを算出する。  The input signal extracted from the directional coupler 5 is input to the input signal discriminating circuit 6 and processed in the same manner as in the first embodiment. That is, the average power detection circuit 11 detects the average power P a Ve of the input signal, the peak power detection circuit 12 detects the peak power P peak of the input signal, and the power ratio calculation circuit 13 detects the peak power P peak. · Calculate the average power ratio Pr.
比較回路 1 4は算出されたピーク · アベレージ電力比 P rと所定の基 準値 P s を比較し、 例えば、 入力端子 3に入力信号 Mが入力され、 ビ一 ク · アベレージ電力比 p rが所定の基準値 P s よ り小さい場合には、 ド レイ ン電圧制御回路 8 に対して、 増幅器 1 に所定の ドレイ ン電圧 V d 1 を供給するよう指示する。 また、 入力端子 3に入力信号 Nが入力され、 ピーク · アベレージ電力比 p rが所定の基準値 P s よ り大きい場合には 、 ド レイ ン電圧制御回路 8に対して、 増幅器 1 に別の所定の ド レイ ン電 圧 V d 2を供給するよう指示する。 The comparison circuit 14 compares the calculated peak-to-average power ratio Pr with a predetermined reference value Ps.For example, when the input signal M is input to the input terminal 3, the peak-to-average power ratio pr is determined. If it is smaller than the reference value P s, the drain voltage control circuit 8 is instructed to supply a predetermined drain voltage Vd 1 to the amplifier 1. When the input signal N is input to the input terminal 3 and the peak-to-average power ratio pr is larger than a predetermined reference value Ps, another predetermined voltage is supplied to the drain voltage control circuit 8 to the amplifier 1. Drain power Instruct to supply pressure Vd2.
ド レイ ン電圧制御回路 8は、 比較回路 1 4からの指示に基づき、 ドレ イ ン電圧 V d 1又は V d 2を増幅器 1に供給する。 増幅器 1は、 ドレイ ン電圧 V d 2が供給されると、 ド レイ ン電圧 V d lが供給されるときょ りも飽和電力が増加する。  The drain voltage control circuit 8 supplies the drain voltage Vd1 or Vd2 to the amplifier 1 based on the instruction from the comparison circuit 14. When the drain voltage Vd2 is supplied to the amplifier 1, the saturation power increases when the drain voltage Vd1 is supplied.
第 7図はこの発明の実施の形態 2による高周波増幅器の平均入力電力 に対する平均出力電力特性と歪電力特性を示す図であり、 図において、 1 0 1は入力信号 Mが入力されて ドレイン電圧 V d lのときの平均出力 電力特性、 2 0 1は入力信号 Mが増幅器 1に入力されて ド レイ ン電圧 V d 1のときの歪電力特性、 2 0 2は入力信号 Nが増幅器 1に入力されて ドレイン電圧 V d lのときの歪電力特性であり、 平均出力電力特性 1 0 1、 歪電力特性 2 0 1 , 2 0 2は、 実施の形態 1の第 5図と同じ特性で ある。  FIG. 7 is a diagram showing an average output power characteristic and a distortion power characteristic with respect to an average input power of the high-frequency amplifier according to the second embodiment of the present invention. In the figure, 101 denotes an input signal M input and a drain voltage V Average output power characteristic at dl, 210 is distortion power characteristic at the time when the input signal M is input to the amplifier 1 and the drain voltage is Vd1, and 220 is the input signal N when the input signal N is input to the amplifier 1. The average output power characteristic 101 and the distortion power characteristics 201 and 202 are the same as those in FIG. 5 of the first embodiment.
また、 第 7図において、 1 0 3は入力信号 Nが入力されて ド レイ ン電 圧 V d 2のときの平均出力電力特性、 2 0 4は入力信号 Nが増幅器 1 に 入力されて ドレイン電圧 V d 2のときの歪電力特性であり、 電源回路 2 からゲート電圧 V g 1が増幅器 1に供給されているものとする。  In FIG. 7, 103 is the average output power characteristic when the input signal N is input and the drain voltage is Vd2, and 204 is the average output power characteristic when the input signal N is input to the amplifier 1 and the drain voltage is This is the distortion power characteristic at V d 2, and it is assumed that the gate voltage V g 1 is supplied from the power supply circuit 2 to the amplifier 1.
第 7図に示すように、 入力信号 Mが入力されて、 ピーク , アベレージ 電力比 P rが所定の基準値 P sより小さく、 ド レイ ン電圧 V d 1が増幅 器 1に供給されている場合には、 平均出力電力特性が 1 0 1で、 歪電力 特性が 2 0 1であり、 平均出力電力が P 1のときの歪電力は D 1 となる ο  As shown in Fig. 7, when the input signal M is input, the peak-to-average power ratio Pr is smaller than the predetermined reference value Ps, and the drain voltage Vd1 is supplied to the amplifier 1. , The average output power characteristic is 101, the distortion power characteristic is 201, and the distortion power when the average output power is P 1 is D 1 ο
一方、 入力信号 Nが入力されて、 ピーク · アベレージ電力比 P rが所 定の基準値 P sより大きく、 ド レイ ン電圧 V d 2が増幅器 1に供給され ている場合には、 平均出力電力特性が 1 0 3で、 歪電力特性が 2 0 4 と なり、 平均出力電力が P 1のときの歪電力は、 入力信号 Mが入力された 場合と同様に D l となる。 すなわち、 ドレイ ン電圧 V d lのときの歪電 力 D 2 より歪電力 D 1 に改善される。 On the other hand, when the input signal N is input, the peak-to-average power ratio Pr is larger than the predetermined reference value Ps, and the drain voltage Vd2 is supplied to the amplifier 1, the average output power The characteristic is 103, the distortion power characteristic is 204, and the average output power is P1. As in the case, it becomes D l. That is, the distortion power D 2 is improved from the distortion power D 2 at the drain voltage V dl to the distortion power D 1.
ドレイ ン電圧制御回路 8には、 入力信号 Mの場合に、 平均出力電力特 性 1 0 1 と歪電力特性 2 0 1が得られるような ドレイ ン電圧 V d 1 と、 入力信号 Nの場合に、 平均出力電力特性 1 0 3 と歪電力特性 2 0 4が得 られるような ドレイ ン電圧 V d 2が予め設定されており、 ドレイ ン電圧 制御回路 8は、 比較回路 1 4からの指示に基づき、 設定されている ドレ イ ン電圧 V d 1又は V d 2 を選択して増幅器 1 に供給する。  The drain voltage control circuit 8 has a drain voltage V d 1 for obtaining an average output power characteristic 101 and a distortion power characteristic 201 for an input signal M, and a drain voltage V d 1 for an input signal N. The drain voltage Vd2 is set in advance so that the average output power characteristic 103 and the distortion power characteristic 204 can be obtained, and the drain voltage control circuit 8 operates based on the instruction from the comparison circuit 14. Then, the set drain voltage Vd1 or Vd2 is selected and supplied to the amplifier 1.
平均出力電力特性 1 0 1 に対して平均出力電力特性 1 0 3を得るため には、 平均出力電力特性 1 0 1 を得ているときの ドレイ ン電圧 V d 1 を 増加させて ドレイ ン電圧 V d 2 とし、 すなわち、 増幅器 1の飽和電力が 増加する方向に変更すれば良い。 また、 歪電力特性 2 0 2 に対して歪電 力特性 2 0 4を得るためには、 歪電力特性 2 0 2 を得ているときの ドレ ィ ン電圧 V d 1 を増加させて ドレイ ン電圧 V d 2 とし、 すなわち、 増幅 器 1の飽和電力が増加する方向に変更すれば良く、 増幅器 1の飽和電力 が増加すると、 増幅器 1の出力バックオフ (出力電力に対する飽和電力 の比) が大き くなり、 歪電力特性 2 0 4のように歪電力が改善される。 以上のように、 この実施の形態 2 によれば、 入力信号のピーク · アベ レージ電力比 P rが変化しても、 増幅器 1 に供給する ドレイ ン電圧 V d を制御することにより、 増幅器 1から出力される歪電力の変化を抑制で きるという効果が得られる。 実施の形態 3 .  In order to obtain the average output power characteristic 103 with respect to the average output power characteristic 101, the drain voltage Vd1 when obtaining the average output power characteristic 101 is increased by increasing the drain voltage Vd1. d 2, that is, the direction in which the saturation power of the amplifier 1 increases. Also, in order to obtain the strain power characteristic 204 with respect to the strain power characteristic 202, the drain voltage Vd1 when the distortion power characteristic 202 is obtained is increased to increase the drain voltage. V d 2, that is, the direction in which the saturation power of the amplifier 1 increases may be changed. When the saturation power of the amplifier 1 increases, the output back-off (the ratio of the saturation power to the output power) of the amplifier 1 increases. Thus, the distortion power is improved as in the distortion power characteristic 204. As described above, according to the second embodiment, even if the peak-to-average power ratio Pr of the input signal changes, by controlling the drain voltage V d supplied to the amplifier 1, The effect is obtained that the change in the output distortion power can be suppressed. Embodiment 3.
第 8図はこの発明の実施の形態 3による高周波増幅器の構成を示すブ ロック図であり、 この実施の形態 3は、 実施の形態 1 と実施の形態 2 と を組み合わせたもので、 ゲート電圧制御回路 7 (電圧制御回路) と ドレ イ ン電圧制御回路 8 (電圧制御回路) を備えたものである。 すなわち、 入力信号判別回路 6はピーク · アベレージ電力比 P r と所定の基準値 P s とを比較し、 比較した結果に基づき、 ゲー ト電圧制御回路 7 と ドレイ ン電圧制御回路 8に対して、 増幅器 1 に供給するゲー ト電圧 V gと ドレ イ ン電圧 V dを制御するよう指示する。 FIG. 8 is a block diagram showing a configuration of a high-frequency amplifier according to Embodiment 3 of the present invention. Embodiment 3 is a combination of Embodiments 1 and 2, and has a gate voltage control. Circuit 7 (voltage control circuit) and drain It has an in-voltage control circuit 8 (voltage control circuit). That is, the input signal discrimination circuit 6 compares the peak-average power ratio Pr with a predetermined reference value Ps, and based on the comparison result, provides the gate voltage control circuit 7 and the drain voltage control circuit 8 with: Instructs to control the gate voltage Vg and the drain voltage Vd supplied to the amplifier 1.
次に動作について説明する。  Next, the operation will be described.
入力端子 3から第 2図に示すような入力信号 M, Nが入力され、 方向 性結合器 5を介して増幅器 1 に入力され、 増幅された信号は出力端子 4 から出力される。 電源回路 2から増幅器 1 に対し、 2種類のゲー ト電圧 V g ( = V g l又は V g 2 ) がゲート電圧制御回路 7 を介して供給され ると共に、 2種類の ド レイ ン電圧 V d ( = V d l又は V d 2 ) が ド レイ ン電圧制御回路 8を介して供給される。  Input signals M and N as shown in FIG. 2 are input from input terminal 3, input to amplifier 1 via directional coupler 5, and the amplified signal is output from output terminal 4. Two kinds of gate voltages V g (= V gl or V g 2) are supplied from the power supply circuit 2 to the amplifier 1 through the gate voltage control circuit 7 and two kinds of drain voltages V d ( = V dl or V d 2) is supplied through the drain voltage control circuit 8.
増幅器 1は、 ゲート電圧 V g 1が供給されると、 電源効率を高めるた めに B級動作による増幅処理を行い、 ゲー ト電圧 V g 2が供給されると 、 歪を改善するために A級動作による増幅処理を行う よう設定され、 ド レィ ン電圧 V d 2が供給されると、 ドレイ ン電圧 V d 1のときよ り も飽 和電力が増加するように設定されている。  When the gate voltage V g1 is supplied, the amplifier 1 performs amplification processing by class B operation to increase power supply efficiency, and when the gate voltage V g2 is supplied, the amplifier 1 performs A amplification to improve distortion. When the drain voltage V d2 is supplied, the saturation power is set to be higher than when the drain voltage V d1 is supplied.
方向性結合器 5から取り出された入力信号は、 入力信号判別回路 6 に 入力されて、 実施の形態 1 と同様に処理される。 すなわち、 平均電力検 出回路 1 1が入力信号の平均電力 P a V eを検出し、 ビーク電力検出回 路 1 2が入力信号のピーク電力 P p e a kを検出し、 電力比算出回路 1 3はビーク · アベレージ電力比 P rを算出する。  The input signal extracted from the directional coupler 5 is input to the input signal discriminating circuit 6 and processed in the same manner as in the first embodiment. That is, the average power detection circuit 11 detects the average power PaVe of the input signal, the beak power detection circuit 12 detects the peak power Ppeak of the input signal, and the power ratio calculation circuit 13 detects the peak power Ppeak. · Calculate the average power ratio Pr.
比較回路 1 4は算出されたピーク · アベレージ電力比 P rと所定の基 準値 P sを比較し、 例えば、 入力端子 3に入力信号 Mが入力され、 ピー ク · アベレージ電力比 p rが所定の基準値 P sよ り小さい場合には、 ゲ — ト電圧制御回路 7に対して、 増幅器 1 に所定のゲー ト電圧 V g 1 を、 ドレイ ン電圧制御回路 8に対して、 増幅器 1に所定の ドレイン電圧 V d 1を供給するよう指示する。 また、 入力端子 3に入力信号 Nが入力され 、 ピーク · アベレージ電力比 P rが所定の基準値 P sより大きい場合に は、 ゲート電圧制御回路 7に対して、 増幅器 1に別の所定のゲート電圧 V g 2を、 ド レイ ン電圧制御回路 8に対して、 増幅器 1に別の所定の ド レイン電圧 V d 2を供給するよう指示する。 The comparison circuit 14 compares the calculated peak-to-average power ratio Pr with a predetermined reference value Ps.For example, when the input signal M is input to the input terminal 3 and the peak-to-average power ratio pr is If it is smaller than the reference value P s, a predetermined gate voltage V g 1 is supplied to the amplifier 1 by the gate voltage control circuit 7. The drain voltage control circuit 8 is instructed to supply a predetermined drain voltage V d1 to the amplifier 1. When the input signal N is input to the input terminal 3 and the peak-to-average power ratio Pr is larger than a predetermined reference value Ps, another predetermined gate is supplied to the amplifier 1 with respect to the gate voltage control circuit 7. The voltage Vg2 instructs the drain voltage control circuit 8 to supply another predetermined drain voltage Vd2 to the amplifier 1.
ゲート電圧制御回路 7は、 比較回路 1 4からの指示に基づき、 ゲート 電圧 V g 1又は V g 2を増幅器 1に供給する。 増幅器 1は、 ゲート電圧 V g 1が供給されると、 電源効率を高めるために B級動作による増幅処 理を行い、 ゲート電圧 V g 2が供給されると、 歪を改善するために A級 動作による増幅処理を行う。 また、 ドレイン電圧制御回路 8は、 比較回 路 1 4からの指示に基づき、 ド レイ ン電圧 V d 1又は V d 2を増幅器 1 に供給する。 増幅器 1は、 ドレイン電圧 V d 2が供給されると、 ドレイ ン電圧 V d 1が供給されるときょりも飽和電力が増加する。  The gate voltage control circuit 7 supplies the gate voltage V g1 or V g 2 to the amplifier 1 based on the instruction from the comparison circuit 14. When the gate voltage V g 1 is supplied, the amplifier 1 performs amplification processing by class B operation to increase power supply efficiency, and when the gate voltage V g 2 is supplied, the amplifier A class A to improve distortion. Performs amplification by operation. In addition, the drain voltage control circuit 8 supplies the drain voltage Vd1 or Vd2 to the amplifier 1 based on an instruction from the comparison circuit 14. When the amplifier 1 is supplied with the drain voltage V d2, the saturation power increases whenever the drain voltage V d1 is supplied.
第 9図はこの発明の実施の形態 3による高周波増幅器の平均入力電力 に対する平均出力電力特性と歪電力特性を示す図であり、 図において、 1 0 1は入力信号 Mが入力されてゲ一ト電圧 V g 1、 ド レイ ン電圧 V d 1のときの平均出力電力特性、 2 0 1は入力信号 Mが増幅器 1に入力さ れてゲート電圧 V g l、 ドレイ ン電圧 V d 1のときの歪電力特性、 2 0 2は入力信号 Nが増幅器 1に入力されてゲート電圧 V g 1、 ド レイ ン電 圧 V d lのときの歪電力特性であり、 平均出力電力特性 1 0 1、 歪電力 特性 2 0 1 , 2 0 2は、 実施の形態 1の第 5図と同じ特性である。  FIG. 9 is a diagram showing an average output power characteristic and a distortion power characteristic with respect to an average input power of the high-frequency amplifier according to Embodiment 3 of the present invention. In the figure, reference numeral 101 denotes a gate when an input signal M is input. Average output power characteristics at voltage V g 1 and drain voltage V d 1, 210 is distortion when input signal M is input to amplifier 1 and gate voltage V gl and drain voltage V d 1 The power characteristic, 202, is the distortion power characteristic when the input signal N is input to the amplifier 1 and the gate voltage Vg1 and the drain voltage Vdl, and the average output power characteristic 101, the distortion power characteristic 201 and 202 have the same characteristics as FIG. 5 of the first embodiment.
また、 第 9図において、 1 0 4は入力信号 Nが入力されてゲート電圧 V g 2、 ド レイ ン電圧 V d 2のときの平均出力電力特性、 2 0 5は入力 信号 Nが増幅器 1に入力されてゲート電圧 V g 2、 ドレイ ン電圧 V d 2 のときの歪電力特性である。 第 9図に示すように、 入力信号 Mが入力されて、 ピーク ' アベレージ 電力比 P rが所定の基準値 P sより小さく、 ゲート電圧 Vg l、 ドレイ ン電圧 V d 1が増幅器 1に供給されている場合には、 平均出力電力特性 が 1 0 1で、 歪電力特性が 2 0 1であり、 平均出力電力が P 1のときの 歪電力は D 1となる。 In FIG. 9, reference numeral 104 denotes an average output power characteristic when the input signal N is input and the gate voltage Vg2 and the drain voltage Vd2, and 205 denotes the input signal N to the amplifier 1. These are the distortion power characteristics when the gate voltage V g 2 and the drain voltage V d 2 are input. As shown in FIG. 9, when the input signal M is input, the peak-to-average power ratio Pr is smaller than the predetermined reference value Ps, and the gate voltage Vgl and the drain voltage Vd1 are supplied to the amplifier 1. In this case, the average output power characteristic is 101, the distortion power characteristic is 201, and the distortion power when the average output power is P1 is D1.
一方、 入力信号 Nが入力されて、 ピーク ' アベレージ電力比 P rが所 定の基準値 P sより大きく、 ゲート電圧 Vg 2、 ドレイ ン電圧 Vd 2が 増幅器 1に供給されている場合には、 平均出力電力特性が 1 04で、 歪 電力特性が 2 0 5となり、 平均出力電力が P 1のときの歪電力は、 入力 信号 Mが入力された場合と同様に D 1となる。 すなわち、 ゲート電圧 V g 1 ドレイ ン電圧 Vd lのときの歪電力 D 2よ り歪電力 D 1に改善さ れる。  On the other hand, if the input signal N is input, the peak-to-average power ratio Pr is larger than the predetermined reference value Ps, and the gate voltage Vg2 and the drain voltage Vd2 are supplied to the amplifier 1, The average output power characteristic is 104, the distortion power characteristic is 205, and the distortion power when the average output power is P1 is D1 as in the case where the input signal M is input. In other words, the distortion power D2 is improved to the distortion power D1 from the distortion power D2 at the gate voltage Vg1 and the drain voltage Vdl.
ゲート電圧制御回路 7、 ドレイ ン電圧制御回路 8には、 入力信号 Mの 場合に、 平均出力電力特性 1 0 1と歪電力特性 2 0 1が得られるような ゲート電圧 V g 1、 ドレイン電圧 V d 1が予め設定されていると共に、 入力信号 Nの場合に、 平均出力電力特性 1 04と歪電力特性 2 0 5が得 られるようなゲート電圧 Vg 2、 ドレイ ン電圧 V d 2が予め設定されて いる。 そして、 ゲート電圧制御回路 7、 ドレイ ン電圧制御回路 8は、 比 較回路 1 4からの指示に基づき、 設定されているゲート電圧 V g 1又は V g 2、 ドレイ ン電圧 V d 1又は V d 2を選択して増幅器 1に供給する ο  The gate voltage control circuit 7 and the drain voltage control circuit 8 have a gate voltage V g1 and a drain voltage V such that the average output power characteristic 101 and the distortion power characteristic 201 can be obtained for the input signal M. In addition to d1, the gate voltage Vg2 and the drain voltage Vd2 are set so that the average output power characteristic 104 and the distortion power characteristic 205 are obtained when the input signal is N. ing. The gate voltage control circuit 7 and the drain voltage control circuit 8 determine the set gate voltage V g1 or V g2 and the set drain voltage V d1 or V d based on the instruction from the comparison circuit 14. Select 2 and supply to amplifier 1 ο
平均出力電力特性 1 0 1に対して平均出力電力特性 1 04を得るため には、 平均出力電力特性 1 0 1を得ているときのゲート電圧 Vg lを増 加させてゲート電圧 V g 2とし、 すなわち、 増幅器 1の ドレイン電流を 増加させて、 増幅器 1の利得を増加させる方向に変更すると共に、 平均 出力電力特性 1 0 1を得ているときの ドレイン電圧 V d 1を増加させて ドレイ ン電圧 Vd 2とし、 すなわち、 増幅器 1の飽和電力が増加する方 向に変更すれば良い。 In order to obtain the average output power characteristic 104 with respect to the average output power characteristic 101, the gate voltage Vgl when the average output power characteristic 101 is obtained is increased to obtain the gate voltage Vg2. That is, by increasing the drain current of the amplifier 1 to increase the gain of the amplifier 1 and increasing the drain voltage V d 1 when the average output power characteristic 101 is obtained. The drain voltage may be Vd 2, that is, the drain voltage may be changed so that the saturation power of the amplifier 1 increases.
また、 歪電力特性 2 0 2に対して歪電力特性 2 0 5を得るためには、 歪電力特性 2 0 2を得ているときのゲート電圧 Vg 1を増加させてゲ一 ト電圧 V g 2とし、 すなわち、 増幅器 1が B級動作の増幅処理から A級 動作の増幅処理になる方向に変更すると共に、 歪電力特性 20 2を得て いるときの ドレイ ン電圧 Vd lを増加させて ドレイ ン電圧 Vd 2とし、 すなわち、 増幅器 1の飽和電力が増加する方向に変更すれば良い。  Further, in order to obtain the distortion power characteristic 205 with respect to the distortion power characteristic 202, the gate voltage Vg1 when obtaining the distortion power characteristic 202 is increased to increase the gate voltage Vg2. That is, the amplifier 1 is changed from the amplification processing of the class B operation to the amplification processing of the class A operation, and the drain voltage Vd1 when the distortion power characteristic 202 is obtained is increased to increase the drain voltage. The voltage may be Vd2, that is, the voltage may be changed in a direction to increase the saturation power of the amplifier 1.
このように、 ゲー ト電圧 Vg 1をゲート電圧 Vg 2に増加し、 ドレイ ン電圧 V d 1を ドレイ ン電圧 V d 2に増加することによ り、 増幅器 1が A級動作の増幅処理を行う と共に、 増幅器 1の出力バックオフが大き く なり、 歪電力特性 2 0 5のように歪電力が改善される。  As described above, the gate voltage Vg1 is increased to the gate voltage Vg2, and the drain voltage Vd1 is increased to the drain voltage Vd2, so that the amplifier 1 performs the amplification process of the class A operation. At the same time, the output back-off of the amplifier 1 increases, and the distortion power is improved as indicated by the distortion power characteristic 205.
第 1 0図はこの発明の実施の形態 3による高周波増幅器の平均入力電 力に対する他の平均出力電力特性を示す図であ り、 図において、 平均出 力電力特性 1 0 1 , 1 04は第 9図と同じ特性である。 1 0 5は入力信 号 Nが入力されて、 平均出力電力特性 1 0 1を得ているときのゲー ト電 圧 Vg 1を増加させてゲー ト電圧 Vg 2とし、 すなわち、 増幅器 1の ド レイ ン電流を増加させて、 増幅器 1の利得を増加させる方向に変更する と共に、 平均出力電力特性 1 0 1を得ているときの ドレイ ン電圧 Vd l を減少させて ドレイ ン電圧 Vd 2とし、 増幅器 1の飽和電力が減少する 方向に変更したものである。 ここでは、 入力信号 Nが入力されたときも 、 入力信号 Mが入力されたときの歪電力 D, 1と同程度の歪電力が得られ るように、 ゲート電圧 Vg 2、 ドレイ ン電圧 V d 2を設定すれば良い。 また、 第 1 0図において、 1 06は入力信号 Nが入力されて、 平均出 力電力特性 1 0 1を得ているときのゲー ト電圧 V g lを減少させてゲ一 ト電圧 V g 2とし、 すなわち、 増幅器 1の ドレイ ン電流を減少させて、 増幅器 1の利得を減少させる方向に変更すると共に、 平均出力電力特性 1 0 1を得ているときの ドレイ ン電圧 V d 1を増加させて ドレイ ン電圧 Vd 2とし、 すなわち、 増幅器 1の飽和電力が増加する方向に変更した ものである。 ここでは、 入力信号 Nが入力されたときも、 入力信号 Mが 入力されたときの歪電力 D 1と同程度の歪電力が得られるように、 ゲー ト電圧 V g 2、 ドレイ ン電圧 V d 2を設定すれば良い。 FIG. 10 is a diagram showing another average output power characteristic with respect to the average input power of the high-frequency amplifier according to Embodiment 3 of the present invention. In the figure, the average output power characteristics 101 and 104 are the same as those in FIG. It has the same characteristics as in Fig. 9. In 105, the gate signal Vg1 when the input signal N is input and the average output power characteristic 101 is obtained is increased to the gate voltage Vg2, that is, the drain of the amplifier 1 is increased. The amplifier current is increased to increase the gain of the amplifier 1, and the drain voltage Vdl when the average output power characteristic 101 is obtained is reduced to the drain voltage Vd2 to obtain the amplifier voltage. This was changed so that the saturation power of 1 decreased. Here, the gate voltage Vg 2 and the drain voltage V d are set so that even when the input signal N is input, the same distortion power as that obtained when the input signal M is input is obtained. Just set 2. In FIG. 10, reference numeral 106 denotes a gate voltage Vg2 by reducing the gate voltage Vgl when the input signal N is input and obtaining the average output power characteristic 101. That is, by reducing the drain current of the amplifier 1, In addition to changing the gain of the amplifier 1 to decrease, the drain voltage Vd1 when the average output power characteristic 101 is obtained is increased to the drain voltage Vd2, that is, the saturation power of the amplifier 1 Is changed to increase. Here, the gate voltage Vg2 and the drain voltage Vd are set so that even when the input signal N is input, the same distortion power as the distortion power D1 when the input signal M is input is obtained. Just set 2.
ゲート電圧 V g 2、 ドレイ ン電圧 Vd 2を設定する場合、 第 1 0図の 平均出力電力特性 1 04, 1 0 5, 1 0 6のように、 3種類の値が設定 可能であるが、 この 3種類の値の中で、 増幅器 1の電源効率が最も良い ものを選択しても良い。  When setting the gate voltage Vg2 and the drain voltage Vd2, three values can be set, as shown in the average output power characteristics 104, 105, 106 in Fig. 10. Of these three values, the one with the highest power efficiency of the amplifier 1 may be selected.
以上のように、 この実施の形態 3によれば、 入力信号のピーク · アベ レージ電力比 P rが変化しても、 増幅器 1に供給するゲート電圧 Vgと ドレイ ン電圧 V dを制御することにより、 増幅器 1から出力される歪電 力の変化を抑制できるという効果が得られる。 実施の形態 4.  As described above, according to the third embodiment, even if the peak-to-average power ratio Pr of the input signal changes, the gate voltage Vg and the drain voltage Vd supplied to the amplifier 1 are controlled. However, the effect that the change in the distortion power output from the amplifier 1 can be suppressed is obtained. Embodiment 4.
第 1 1図、 第 1 2図、 第 1 3図はこの発明の実施の形態 4による高周 波増幅器の構成を示すブロック図であり、 各図において、 9は外部から 、 入力端子 3に入力される入力信号の種類や、 出力端子 4から出力され る増幅器 1の平均出力電力の大きさ等の外部指示情報を入力する制御端 子であり、 ゲート電圧制御回路 7 (電圧制御回路) 、 ドレイ ン電圧制御 回路 8 (電圧制御回路) は、 制御端子 9に入力された外部指示情報の内 容が変化しても、 増幅器 1から出力される歪電力が変化しないように、 ゲート電圧 Vg、 ドレイン電圧 Vdを制御する。 その他の構成は、 上記 各実施の形態における第 4図、 第 6図、 第 8図における同一符号の構成 と同等である。 次に動作について説明する。 FIGS. 11, 12, and 13 are block diagrams showing the configuration of a high frequency amplifier according to Embodiment 4 of the present invention. In each of the figures, reference numeral 9 denotes an external input to input terminal 3. This is a control terminal for inputting external instruction information such as the type of input signal to be input and the average output power of the amplifier 1 output from the output terminal 4. The gate voltage control circuit 7 (voltage control circuit) and the drain The voltage control circuit 8 (voltage control circuit) controls the gate voltage Vg and drain voltage so that the distortion power output from the amplifier 1 does not change even if the content of the external instruction information input to the control terminal 9 changes. Controls voltage Vd. The other configurations are the same as the configurations of the same reference numerals in FIGS. 4, 6, and 8 in each of the above embodiments. Next, the operation will be described.
第 1 1図、 第 1 2図、 第 1 3図において、 入力端子 3に入力される入 力信号の種類や、 出力端子 4から出力される増幅器 1の平均出力電力の 大きさ等の外部指示情報が、 外部から制御端子 9に入力される。 入力信 号の種類としては、 上記各実施の形態における入力信号 Mか入力信号 N であるかを示す情報であり、 平均出力電力の大きさとしては、 通常の平 均出力電力であるか、 通常より高出力の平均出力電力であるかを示す情 報である。  In Fig. 11, Fig. 12, and Fig. 13, external instructions such as the type of input signal input to input terminal 3 and the magnitude of average output power of amplifier 1 output from output terminal 4 Information is input to the control terminal 9 from outside. The type of the input signal is information indicating whether the input signal is the input signal M or the input signal N in each of the above embodiments, and the magnitude of the average output power is the normal average output power or the normal output power. This is information indicating whether the average output power is higher.
入力信号の種類が制御端子 9に入力された場合は、 ゲート電圧制御回 路 7、 ドレイ ン電圧制御回路 8は、 制御端子 9に入力された、 入力端子 3に入力される信号が入力信号 Mであるか入力信号 Nであるかを示す外 部指示情報により、 上記各実施の形態と同様にして、 ゲート電圧 V g、 ドレイ ン電圧 V dを、 入力信号 Nが入力されたときの歪電力が、 入力信 号 Mが入力されたときの歪電力 D 1になるように制御する。  When the type of input signal is input to the control terminal 9, the gate voltage control circuit 7 and the drain voltage control circuit 8 determine whether the signal input to the control terminal 9 and input to the input terminal 3 is the input signal M The gate voltage V g and the drain voltage V d can be changed by the external instruction information indicating whether the input signal N is input or the input signal N. Is controlled to be the distortion power D1 when the input signal M is input.
平均出力電力の大きさが制御端子 9に入力された場合は、 ゲ一ト電圧 制御回路 7、 ドレイ ン電圧制御回路 8は、 制御端子 9に入力された、 通 常の平均出力電力であるか、 通常より高出力の平均出力電力であるかを 示す外部指示情報により、 ゲート電圧 V g、 ドレイ ン電圧 V dを、 通常 より高出力の平均出力電力のときの歪電力が、 通常の平均出力電力のと きの歪電力 D 1になるように制御する。  When the magnitude of the average output power is input to the control terminal 9, the gate voltage control circuit 7 and the drain voltage control circuit 8 determine whether the average output power is the normal average output power input to the control terminal 9. The gate voltage V g and the drain voltage V d are determined by the external instruction information indicating whether the average output power is higher than the normal output power. Control is performed so that the distortion power at the time of power becomes D1.
以上のように、 この実施の形態 4によれば、 制御端子 9に入力された 外部指示情報の内容が変化しても、 ゲート電圧 V g若しくはドレイン電 圧 V d、 又はゲート電圧 V g及びドレイン電圧 V dを制御することによ り、 増幅器 1から出力される歪電力の変化を抑制できるという効果が得 られる。  As described above, according to the fourth embodiment, even if the content of the external instruction information input to the control terminal 9 changes, the gate voltage V g or the drain voltage V d, or the gate voltage V g and the drain voltage By controlling the voltage Vd, an effect of suppressing a change in the distortion power output from the amplifier 1 can be obtained.
上記各実施の形態では、 2種類の入力信号や 2種類の平均出力電力に よ り、 ゲー ト電圧 V gや ドレイ ン電圧 V dを 2段階に制御しているが、 入力信号や平均出力電力が 3種類以上で、 ゲー ト電圧 V gや ドレイ ン電 圧 V dを 3段階以上に制御することも可能である。 In the above embodiments, two types of input signals and two types of average output power Thus, the gate voltage Vg and the drain voltage Vd are controlled in two steps, but the input signal and the average output power are three or more types, and the gate voltage Vg and the drain voltage Vd are controlled by three levels. It is also possible to control more than stages.
また、 上記各実施の形態では、 増幅器 1 をソース接地の増幅器として 説明しているが、 ゲー ト接地や ドレイ ン接地の増幅器でも良い。 さらに 、 上記各実施の形態では、 増幅器 1 を電界効果トランジスタとして説明 しているが、 トランジスタでも良い。 産業上の利用可能性  In each of the above embodiments, the amplifier 1 is described as a source-grounded amplifier, but may be a gate-grounded or drain-grounded amplifier. Further, in each of the above embodiments, the amplifier 1 is described as a field-effect transistor, but may be a transistor. Industrial applicability
以上のように、 この発明に係る高周波増幅器は、 入力信号のピーク · アベレージ電力比が変化しても、 出力される歪電力の変化を抑制するも のに適している。  As described above, the high-frequency amplifier according to the present invention is suitable for suppressing a change in the output distortion power even when the peak-to-average power ratio of the input signal changes.

Claims

請 求 の 範 囲 The scope of the claims
1 . 入力信号を増幅する増幅器と、 1. An amplifier that amplifies the input signal,
入力信号のビーク電力と平均電力を検知してピーク · アベレージ電力 比を算出し、 算出したビーク · アベレージ電力比と所定の基準値とを比 較し、 比較した結果に基づき、 上記増幅器に供給するゲー ト電圧又は ド レィ ン電圧を制御するよう指示する入力信号判別回路と、  The peak-to-average power ratio is calculated by detecting the beak power and average power of the input signal, and the calculated beak-to-average power ratio is compared with a predetermined reference value. An input signal discriminating circuit for instructing to control a gate voltage or a drain voltage;
上記入力信号判別回路による指示に基づき、 入力信号のピーク · アベ レ一ジ電力比が変化しても、 上記増幅器から出力される歪電力が変化し ないように、 上記増幅器に供給するゲー ト電圧又は ドレイ ン電圧を制御 する電圧制御回路とを  The gate voltage supplied to the amplifier so that the distortion power output from the amplifier does not change even if the peak-to-average power ratio of the input signal changes based on the instruction from the input signal determination circuit. Or a voltage control circuit for controlling the drain voltage.
備えたことを特徴とする高周波増幅器。  A high frequency amplifier, comprising:
2 . 入力信号判別回路が、 2. The input signal discrimination circuit
入力信号の平均電力を検出する平均電力検出回路と、  An average power detection circuit for detecting an average power of the input signal;
入力信号のピーク電力を検出するピーク電力検出回路と、  A peak power detection circuit for detecting a peak power of the input signal,
上記平均電力検出回路によ り検出された入力信号の平均電力と、 上記 ビーク電力検出回路によ り検出された入力信号のピーク電力に基づき、 ピーク · アベレージ電力比を算出する電力比算出回路と、  A power ratio calculation circuit that calculates a peak-to-average power ratio based on the average power of the input signal detected by the average power detection circuit and the peak power of the input signal detected by the beak power detection circuit; ,
上記電力比算出回路により算出されたピーク · アベレージ電力比と所 定の基準値を比較し、 比較した結果に基づき、 電圧制御回路に対して、 増幅器に供給するゲー ト電圧又は ド レイ ン電圧を制御するよう指示する 比較回路とを  The peak-average power ratio calculated by the power ratio calculation circuit is compared with a predetermined reference value, and based on the comparison result, a gate voltage or a drain voltage supplied to the amplifier is supplied to the voltage control circuit. And a comparison circuit that instructs
備えたことを特徴とする請求の範囲第 1項記載の高周波増幅器。  2. The high-frequency amplifier according to claim 1, wherein the high-frequency amplifier is provided.
3 . 電圧制御回路は、 入力信号判別回路によ り算出されたピーク · ァ ベレージ電力比が所定の基準値よ り高い場合に、 ビーク ' アベレージ電 力比が所定の基準値よ り低い場合よ りも、 上記増幅器に供給するゲー ト 電圧を増加させる 3. The voltage control circuit calculates the peak gain calculated by the input signal determination circuit. Increases the gate voltage supplied to the amplifier when the average power ratio is higher than the predetermined reference value, compared to when the average power ratio is lower than the predetermined reference value.
ことを特徴とする請求の範囲第 1項記載の高周波増幅器。  2. The high-frequency amplifier according to claim 1, wherein:
4 - 電圧制御回路は、 入力信号判別回路によ り算出されたピーク · ァ ベレージ電力比が所定の基準値よ り高い場合に、 ピーク · アベレージ電 力比が所定の基準値より低い場合よ りも、 上記増幅器に供給する ドレイ ン電圧を増加させる 4-The voltage control circuit, when the peak-to-average power ratio calculated by the input signal discriminating circuit is higher than a predetermined reference value, than when the peak-to-average power ratio is lower than the predetermined reference value Also increase the drain voltage supplied to the amplifier
ことを特徴とする請求の範囲第 1項記載の高周波増幅器。  2. The high-frequency amplifier according to claim 1, wherein:
5 . 入力信号を増幅する増幅器と、 5. An amplifier that amplifies the input signal,
入力信号のピーク電力と平均電力を検知してピーク · アベレージ電力 比を算出し、 算出したピーク · アベレージ電力比と所定の基準値とを比 較し、 比較した結果に基づき、 上記増幅器に供給するゲー ト電圧及びド レイ ン電圧を制御するよう指示する入力信号判別回路と、  Detects the peak power and average power of the input signal, calculates the peak-to-average power ratio, compares the calculated peak-to-average power ratio with a predetermined reference value, and supplies the amplifier based on the comparison result. An input signal discrimination circuit for instructing to control a gate voltage and a drain voltage,
上記入力信号判別回路による指示に基づき、 入力信号のビーク · アベ レ一ジ電力比が変化しても、 上記増幅器から出力される歪電力が変化し ないように、 上記増幅器に供給するゲー ト電圧及びドレイ ン電圧を制御 する電圧制御回路とを  The gate voltage supplied to the amplifier so that the distortion power output from the amplifier does not change even if the beakage-to-average power ratio of the input signal changes based on the instruction from the input signal determination circuit. And a voltage control circuit for controlling the drain voltage.
備えたことを特徴とする高周波増幅器。  A high frequency amplifier, comprising:
6 . 入力信号判別回路が、 6. The input signal determination circuit
入力信号の平均電力を検出する平均電力検出回路と、  An average power detection circuit for detecting an average power of the input signal;
入力信号のピーク電力を検出するピーク電力検出回路と、  A peak power detection circuit for detecting a peak power of the input signal,
上記平均電力検出回路によ り検出された入力信号の平均電力と、 上記 ピーク電力検出回路によ り検出された入力信号のビーク電力に基づき、 ピーク · アベレージ電力比を算出する電力比算出回路と、 The average power of the input signal detected by the average power detection circuit; A power ratio calculation circuit that calculates a peak-to-average power ratio based on the beak power of the input signal detected by the peak power detection circuit;
上記電力比算出回路によ り算出されたピーク · アベレージ電力比と所 定の基準値を比較し、 比較した結果に基づき、 電圧制御回路に対して、 増幅器に供給するゲー ト電圧及びドレイ ン電圧を制御するよう指示する 比較回路とを  The peak-to-average power ratio calculated by the power ratio calculation circuit is compared with a predetermined reference value. Based on the comparison result, the gate voltage and the drain voltage supplied to the amplifier are supplied to the voltage control circuit. And a comparison circuit that instructs
備えたことを特徴とする請求の範囲第 5項記載の高周波増幅器。  6. The high-frequency amplifier according to claim 5, wherein the high-frequency amplifier is provided.
7 . 電圧制御回路は、 入力信号判別回路によ り算出されたピーク · ァ ペレ一ジ電力比が所定の基準値よ り高い場合に、 ピーク · アベレージ電 力比が所定の基準値よ り低い場合よ り も、 上記増幅器に供給するゲー ト 電圧を増加させると共に、 上記増幅器に供給する ド レイ ン電圧を増加さ せる 7. If the peak-to-average power ratio calculated by the input signal discriminating circuit is higher than the predetermined reference value, the voltage-control circuit sets the peak-to-average power ratio to be lower than the predetermined reference value. If necessary, increase the gate voltage supplied to the amplifier and increase the drain voltage supplied to the amplifier.
ことを特徴とする請求の範囲第 5項記載の高周波増幅器。  6. The high-frequency amplifier according to claim 5, wherein:
8 . 電圧制御回路は、 入力信号判別回路によ り算出されたピーク · ァ ベレージ電力比が所定の基準値よ り高い場合に、 ピーク · アベレージ電 力比が所定の基準値よ り低い場合より も、 上記増幅器に供給するゲー ト 電圧を増加させると共に、 上記増幅器に供給する ド レイ ン電圧を減少さ せる 8. When the peak-to-average power ratio calculated by the input signal discriminating circuit is higher than a predetermined reference value, the voltage control circuit operates when the peak-to-average power ratio is lower than the predetermined reference value. Also increases the gate voltage supplied to the amplifier and decreases the drain voltage supplied to the amplifier.
ことを特徴とする請求の範囲第 5項記載の高周波増幅器。  6. The high-frequency amplifier according to claim 5, wherein:
9 . 電圧制御回路は、 入力信号判別回路によ り算出されたピーク · ァ ベレージ電力比が所定の基準値よ り高い場合に、 ピーク · アベレージ電 力比が所定の基準値よ り低い場合よ り も、 上記増幅器に供給するゲー ト 電圧を減少させると共に、 上記増幅器に供給する ド レイ ン電圧を増加さ せる 9. When the peak-to-average power ratio calculated by the input signal discriminating circuit is higher than a predetermined reference value, the voltage control circuit operates when the peak-to-average power ratio is lower than the predetermined reference value. Furthermore, while reducing the gate voltage supplied to the amplifier, the drain voltage supplied to the amplifier is increased. Let
ことを特徴とする請求の範囲第 5項記載の高周波増幅器。  6. The high-frequency amplifier according to claim 5, wherein:
1 0 . 入力信号を増幅する増幅器と、 10. An amplifier that amplifies the input signal,
上記増幅器に入力される入力信号の種類や上記増幅器から出力される 平均出力電力の大きさ等の外部指示情報を入力し、 入力された外部指示 情報の内容が変化しても、 上記増幅器から出力される歪電力が変化しな いように、 上記増幅器に供給するゲート電圧若しくはドレイン電圧、 又 はゲート電圧及びドレイン電圧を制御する電圧制御回路とを  Input external instruction information such as the type of input signal input to the amplifier and the magnitude of the average output power output from the amplifier, and output from the amplifier even if the content of the input external instruction information changes. A gate voltage or a drain voltage to be supplied to the amplifier or a voltage control circuit for controlling the gate voltage and the drain voltage so that the distortion power does not change.
備えたことを特徴とする高周波増幅器。  A high frequency amplifier, comprising:
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JP3923270B2 (en) 2007-05-30
JP2002290163A (en) 2002-10-04
CN1430809A (en) 2003-07-16
KR20030014237A (en) 2003-02-15
CN1183663C (en) 2005-01-05

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