WO2002074027A1 - Perfectionnement dans la realisation de circuits par metallisation au laser et circuits ainsi realises - Google Patents

Perfectionnement dans la realisation de circuits par metallisation au laser et circuits ainsi realises Download PDF

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Publication number
WO2002074027A1
WO2002074027A1 PCT/SG2001/000030 SG0100030W WO02074027A1 WO 2002074027 A1 WO2002074027 A1 WO 2002074027A1 SG 0100030 W SG0100030 W SG 0100030W WO 02074027 A1 WO02074027 A1 WO 02074027A1
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Prior art keywords
laser
substrate
circuit
layer
wafer
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PCT/SG2001/000030
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English (en)
Inventor
Hongyu Zheng
Xincai Wang
Gnian Cher Lim
Li Kang Cheah
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Agency For Science, Technology And Research
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Priority to PCT/SG2001/000030 priority Critical patent/WO2002074027A1/fr
Publication of WO2002074027A1 publication Critical patent/WO2002074027A1/fr

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/105—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by conversion of non-conductive material on or in the support into conductive material, e.g. by using an energy beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/485—Adaptation of interconnections, e.g. engineering charges, repair techniques
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    • H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
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    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2924/0001—Technical content checked by a classifier

Definitions

  • This invention relates to the formation of circuits through the use of laser metallization, and to circuit structures formed tliereby.
  • Applications of the invention include rapid prototyping of printed wire circuits, wafer level chip scale packaging.
  • a method of forming circuit interconnections on a substrate including: directing a laser beam to trace a predetermined circuit interconnection pattern on a surface of said substrate to thereby effect laser-induced deposition of a seed metal layer in said predetermined circuit interconnection pattern on said substrate surface; and performing electroless metal plating on said seed metal layer to form said circuit interconnections on said substrate.
  • One form of the invention includes applying a metalorganic film to said substrate surface, wherein the laser-induced deposition comprises heating of selected portions of the metalorganic film with said laser beam so as to cause thermal decomposition thereof according to said predetermined circuit interconnection pattern.
  • the remainder of the metalorganic film is removed from the substrate following the laser induced deposition process.
  • the metalorganic film comprises a film of copper formate.
  • Another form of the invention involves laser-catalyzing of selected portions of said substrate surface and application of a metal electrolyte solution to the laser-catalyzed substrate surface.
  • the substrate might comprise a circuit board, for example, or may comprise an integrated circuit wafer.
  • the method of a preferred embodiment can be used to perform water level chip scale packaging (WLCSP).
  • WLCSP water level chip scale packaging
  • a method of forming circuit interconnections on a substrate including: directing a laser beam to trace over selected portions of the substrate to activate a predetermined circuit interconnection pattern on a surface of said substrate; forming a metallic circuit interconnection seed layer on said substrate surface corresponding to said predetermined circuit interconnection pattern; and depositing metal onto said circuit interconnection seed layer in an electroless plating process.
  • the present invention further provides a method of forming I/O contacts on an integrated circuit wafer, the integrated circuit wafer having a passivation layer with apertures formed therein at which contact pads for integrated circuits on the wafer are exposed, the method including: forming a metallic seed layer on the wafer by laser-induced metal deposition, the seed layer being formed in a predetermined circuit connection pattern between respective said contact pads and I/O contact locations; depositing a second metal layer onto said seed layer using an electroless metal plating process; and forming I/O contacts at said I/O contact locations, wherein said seed layer and said second metal layer provide electrical interconnection between the I/O contacts and respective integrated circuit contact pads.
  • the laser-induced metal deposition includes applying a metalorganic precursor film over said wafer passivation layer, effecting thermal decomposition of selected portions of the precursor film according to the predetermined circuit connection pattern using a laser beam, and removing the remainder of the precursor film.
  • the laser-induced deposition comprises applying an organic passivation layer to said wafer, laser-catalyzing selected portions of said organic passivation layer surface and application of a metal electrolyte solution to the laser-catalyzed surface so as to form metal deposits thereon according to said predetermined circuit connection pattern.
  • a preferred implementation includes application of an organic passivation layer to the wafer prior to said laser-induced metal deposition, the organic passivation layer being patterned for exposure of said contact pads.
  • a second passivation layer may be applied said electroless metal plating process, the second organic passivation layer being patterned for exposure of said second metal layer at said I/O contact locations.
  • the said I/O contacts comprise solder bumps formed at said I O contact locations on the wafer.
  • a circuit board including a substrate having a dielectric substrate surface, the circuit board further including a first metallic seed layer on said substrate surface in a predetermined circuit interconnection pattern, the seed layer being formed by laser-induced metal deposition, and a second metal layer deposited on said seed layer by electroless metal plating.
  • Figure 1 is a flowchart diagram illustrating a general circuit formation process according to an embodiment of the present invention
  • Figure 2 is a series of diagrammatic cross-sectional views of circuit element formation on a substrate corresponding to the process steps of Figure 1 ;
  • Figure 3 is a graph of laser transmission through copper formate film of various laser wavelengths
  • Figure 4 is a graph of circuit track width against laser beam scanning speed
  • Figure 5 is a diagrammatic plan view of a fabricated integrated circuit die showing contact pads therefor;
  • Figure 6 is a diagrammatic plan view of the integrated circuit die with a redistribution metal layer formed thereon;
  • Figures 7 to 14 are cross-sectional diagrams illustrating the formation of circuit interconnections on an integrated circuit die for water level chip scale packaging; and Figure 15 is a flow chart diagram of a procedure for water level chip scale packaging according to an embodiment of the present invention.
  • Figure 16 shows an example of a conductive circuit formed in accordance with the present invention.
  • Embodiments of the present invention provide a laser metallisation process that is useful in rapid prototyping of printed wire circuits, circuit repair, mask making and repair, and devices requiring in-mould circuits.
  • the laser metallisation process can also be applied to wafer level chip scale packaging (WLCSP), to produce an improved WLCSP that facilitates standard surface mount technology (SMT) without under fill material between chip and substrate.
  • WLCSP wafer level chip scale packaging
  • SMT standard surface mount technology
  • Figure 1 is a flow chart diagram illustrating a general circuit formation process 10 according to an embodiment of the present invention.
  • Figure 2 illustrates a series of diagrammatic cross-sectional view of circuit element formation on a substrate 30 corresponding to the process steps of Figure 1.
  • the substrate 30 provides a base upon which circuit interconnections are to be formed.
  • the substrate 30 may be of any suitable construction, such as those materials known for use in printed circuit boards, or the passivation layer of an integrated circuit die in the case of implementation for wafer level chip scale packaging.
  • the substrate surface is preferably treated to facilitate adhesion of metal deposits thereto, such as by plasma, chemical and/or ultrasonic rinsing of the substrate surface before application of a precursor film as described below.
  • a precursor film such as copper formate
  • Surface cleaning and pretreatment of the substrate using detergents, chemicals or plasma before applying the solution onto the substrate are found to improve the wettability and thus the film adhesion to the substrate.
  • a liquid precursor film 32 is applied to the surface of the substrate 30, at step 12 in process 10.
  • the liquid precursor comprises a metal organic solution such as copper formate.
  • An appropriate metallorganic solution may be prepared by dissolving 1.25g commercially available copper formate (Cu(HCOO) 2 -2H O, Aldrich Chemical) into 10ml deionised water. (The solubility of copper formate is 12.5 g in 100 ml DI water). A small amount (0.5-lml) of 10% glycerol is then added in the solution to avoid the formation of copper formate crystals in the film (anti-crystallisation). Spin coating, spraying or brushing technique may be used to apply the solution onto the substrate.
  • An amorphous (paste-like or solid) copper formate film 34 is formed on the substrate 30 (step 14) after baking in an oven at 70 - 75°C for about 30 minutes or drying by hot air to partially remove the water.
  • a circuit pattern is written on the film using a computer controlled laser (step 16).
  • the circuit pattern traced by the laser beam may be controlled according to a CAD circuit configuration, for example.
  • the action of the laser beam effects laser thermal decomposition of the copper formate film, leaving a copper track 36.
  • the deposited copper 36 provides a seed layer for the circuit formation on the substrate 30.
  • the laser beam has a wavelength of 532nm. Under the following conditions, the laser beam irradiates on the substrate and heats it up to the decomposition temperature of the copper formate (around 200°C). Copper deposits on the substrate.
  • the laser beam has a wavelength of 1064nm. Under the following conditions, the laser beams irradiates on the substrate and heats it up to the decomposition temperature of the copper formate (around 200°C). Copper deposits on the substrate.
  • Figure 3 is a graph of laser transmission through copper formate film according to various laser wavelengths.
  • the copper formate is fairly transparent to both the laser radiation at 1064 nm and 532 nm. It is seen that the 2 nd harmonic Nd:YAG laser beam at the wavelength of 532 nm transmits about 90% of the beam through the copper formate film, whereas about 80% of the 1064nm beam can be transmitted. Therefore, the absorption coefficient of the substrate controls the temperature rise and distribution, which in turn controls the decomposition process of the copper formate film.
  • the transmission curve also implies that a thick film can be used to produce thick copper deposits with both laser beams.
  • the metal seed circuit layer on the substrate using laser assisted copper deposition from solution.
  • a 532nm pulse-mode Nd:YAG laser can be used instead of CW Ar + laser for the process.
  • the deposition process was initiated by laser-catalyzing of the polymide surface and a photothermal reaction of a tartarate-complex solution of Cu 2+ ions in an alkaline and reducing environment.
  • circuit interconnection tracks are built upon the seed layer 36 using an electroless plating process, depositing copper or nickel, for example.
  • This process step is illustrated at step 20 in Figure 1, and correspondingly the electroless copper plating layer 38 is shown formed on substrate 30 in Figure 2.
  • the copper 36 deposited at step 16 acts as a seeding layer for the further electroless copper or nickel plating, which provides additional interconnection layer thickness and electrical conductivity.
  • the interconnection tracks can be formed having a thickness range from 5 micrometres to 10 micrometers, with electrical conductivity of the order of 5 ⁇ Ohms-cm, that is sufficiently low for practical purposes.
  • CSP is categorised as semiconductor chip structures that have been ruggedized to facilitate the ease of chip handling, testing and chip assembly.
  • the CSP have common attributes of minimal size, no more than 1.2X the area of the original die size, and are direct surface mountable.
  • US Patent 6,138,348 and US Patent 5,776,796 shows the cross section of CSP packages using redistribution and flex interposer from Flip Chip Technologies and Tessera respectively.
  • Array packaging technologies shrink the package to the size of the die itself allows the package to be fabricated on the wafer before dicing.
  • Wafer Level Packaging allows IC components to be shipped directly from the fab fully tested, packaged and ready for mounting by standard surface mount or flip chip bonding technique.
  • a particularly advantageous implementation of the circuit interconnection formation technology of the present invention involves the formation of circuit interconnections for wafer level chip scale packaging (WLSCP).
  • WLSCP wafer level chip scale packaging
  • This enables the production of integrated circuit dies with interconnections for standard surface mount technology without under fill material between the chip and substrate.
  • the improved WLCSP enables reduction of investment cost in fabrication equipment, in that the redistribution layer and interconnections can be deposited without the need of vacuum coating equipment such as evaporator, sputter machine and chemical vapour deposition apparatus.
  • packaging size of the integrated circuit is reduced to the original bare integrated circuit die, which has hitherto been unachievable.
  • Figure 15 is a flow chart diagram of the preferred WLSCP process according to 200, according to an embodiment of the present invention.
  • the process begins at 202 with a fabricated integrated circuit die or wafer having a passivation layer formed thereon to protect the integrated circuit but having apertures formed therein to expose the contact pads.
  • an organic passivation layer is applied over the existing passivation layer of the integrated circuit in order to improve adhesion for the interconnection layer.
  • the organic passivation layer is patterned so as to expose the contact pads.
  • a precursor film, such as a metalorganic film is applied over the organic passivation layer at step 206. Selected portions of the precursor film are caused to undergo thermal decomposition, so as to form copper interconnection tracks according to a desired circuit interconnection pattern. This is performed at 208 of the process 200, according to the laser writing processes described hereinabove.
  • the remainder of the precursor film is then removed, leaving a metal seed layer on the integrated circuit die/wafer according to the desired circuit interconnection pattern (step 210).
  • an electroless metal plating process is utilised (step 212) to deposit an additional thickness of conducting metal onto the seed layer circuit interconnection pattern.
  • Another organic passivation layer is then applied and patterned (214) leaving exposed I/O contact openings to portions of the electroless metal layer.
  • a second electroless metal plating process is employed at 216 to apply additional metal at the exposed I/O contact opening.
  • an immersion gold layer applied at 218 over the electroless metal portions at the I/O contact openings.
  • interconnection pads in the form of solder bumps are applied over the I/O contact metal portions, using the screen printing techniques or the like.
  • Figure 5 illustrates a plan view of a fabricated integrated circuit 50 having a plurality of contact pads 102.
  • the contact pads 102 may be aluminium, aluminium alloys (typically Al/Cu0.5 or Al/Si0.5/Cu0.5) or copper or other suitable materials.
  • the contact pads are typically spaced peripherally along the four sides of the chip 50.
  • the pitch of the contact pads may be of the order of 100 microns.
  • FIG 7 is a cross-sectional view through 7-7 of the chip 50 illustrating an integrated circuit wafer or die 100 having contact pads 102 and a passivation layer 104.
  • a conventional integrated circuit packaging might involve mounting the integrated circuit 50 to a lead frame or the like with gold wires being coupled between respective contact pods and external leads. Then, the integrated circuit and inner portions of the lead frame may be encapsulated in a plastics material, for example, with ends of the leads extending therefrom.
  • the WLCSP construction of the preferred embodiment involves the formation of interconnection pads (e.g. solder bumps) directly on the integrated circuit chip, with connecting tracks coupling respective contact pads and interconnection pads. This arrangement is illustrated in Figure 6, which shows the chip 50 having interconnection pads 122 formed thereon and coupled to the contact pads 102 by interconnection tracks 112.
  • the passivation layer 104 is patterned to expose the pads 102.
  • the passivation layer apertures can be round or square shape.
  • the passivation layer may be silicon nitride or silicon oxide layer, for example, patterned with reactive ion etching or other techniques.
  • An organic passivation layer 106 is formed on the surface of passivation layer 104, as shown in Figure 8.
  • the organic passivation layer is preferable to improve adhesion between the adjacent layers.
  • the organic passivation layer may include Benzocyclobutene (BCB) or polymide or other suitable materials.
  • BCB Benzocyclobutene
  • the passivation layer 106 is patterned to expose the contact pads 102.
  • the organic passivation layer 106 such as BCB and polymide can be prepared by spin coating the liquid photoimageable materials on the passivation layer 104. The liquid photoimageable materials are baked to evaporate the solvent and followed by photolithography process to pattern the apertures on the contact pads. Further curing forms the organic passivation layer.
  • the redistribution of the electrical connections is formed inward from the contact pads 102.
  • a copper formate dry film 108 is formed on the organic passivation layer as described previously and shown in Figure 9.
  • a laser writing process described hereinabove may be used to transform the selected portions of copper formate dry film 108 to a copper seed layer 110.
  • Electroless copper plating process is performed to deposit a copper layer 112 on the seed layer 110 to reach thickness of around 5 micron as shown in Figure 11.
  • the organic passivation layer 114 is then formed on the surface of the die.
  • the organic passivation layer 114 can include BCB or polymide or other suitable materials.
  • apertures 116 are patterned in the passivation layer 114 to expose portions of the electroless metal plate 112 for interconnection pads 122.
  • the passivation layer apertures 116 can be any described shape such as round or square.
  • the organic passivation layer 114 such as BCB and polyimide can be prepared by spin coating the liquid photoimage materials on the passivation layer 114. The liquid photoimageable materials are baked to evaporate the solvent and followed by photolithography process to pattern the apertures 116 for the interconnection pads. Further curing forms the organic passivation layer.
  • the organic passivation layer can be formed with thickness range from 5 to 40 microns, for example.
  • nickel under-bump metallization 118 can then be deposited in an electroless process to provide sufficient adhesion for intercom ection pad solder bumps while protecting the copper redistribution tracks.
  • the electroless nickel portions 118 also serves as a barrier layer to prevent copper diffusion in the solder bumps.
  • Electroless nickel plating is a method that can be selectively deposit onto desired locations by controlling the surface preparation and conditioning by means of an autocatalytic chemical reaction.
  • An immersion gold layer 120 ( Figure 13) is also applied to prevent the electroless nickel 118 from oxidation.
  • the solder bumps 122 comprising the interconnection pads can be formed ( Figure 14) by screen printing of solder paste on the electroless nickel/immersion gold contacting portions.
  • Suitable solder alloys include, but are not limited to eutectic tin-lead alloys, tin- lead alloys contain 95% tin and tin-copper contain 99.3% tin.
  • the solder paste is screen printed and melted with suitable temperature to form the solder bumps.
  • the WLCSP processing steps described hereinbefore can be performed at the semiconductor wafer level or before the wafer is singulated.
  • the semiconductor wafer can then dice to individual chips with conventional dicing methods.
  • the chip is then ready to mount on a conventional printed circuit board or substrate with conventional pick and place or flip-chip mounting method.
  • FIG. 16 An example of a conductive circuit, formed in accordance with the invention, is shown in Figure 16.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemically Coating (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

L'invention concerne un procédé de métallisation induite par laser pour réaliser des connexions de circuit sur un substrat, consistant à diriger un faisceau laser pour marquer une trace sur des parties sélectionnées du substrat et activer un modèle de connexion de circuit prédéterminé sur sa surface. Une couche de germe métallique de connexion de circuit est façonnée sur la surface du substrat, conformément au modèle de connexion de circuit prédéterminé, par décomposition thermique d'un film organométallique ou par catalyse au laser de la surface du substrat, suivie par le dépôt de l'électrolyte métallique. Le substrat est alors soumis à la galvanoplastie autocatalytique de la couche de germe pour réaliser les connexions de circuit. Ce procédé de réalisation de connexions de circuit peut être appliqué pour réaliser des connexions de circuit sur des cartes de circuits imprimés ou similaires, et il s'avère particulièrement utile dans le conditionnement de boîtiers puces au niveau de la tranche.
PCT/SG2001/000030 2001-03-12 2001-03-12 Perfectionnement dans la realisation de circuits par metallisation au laser et circuits ainsi realises WO2002074027A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/SG2001/000030 WO2002074027A1 (fr) 2001-03-12 2001-03-12 Perfectionnement dans la realisation de circuits par metallisation au laser et circuits ainsi realises

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PCT/SG2001/000030 WO2002074027A1 (fr) 2001-03-12 2001-03-12 Perfectionnement dans la realisation de circuits par metallisation au laser et circuits ainsi realises

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WO2002074027A1 true WO2002074027A1 (fr) 2002-09-19

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Cited By (8)

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Publication number Priority date Publication date Assignee Title
DE10258478A1 (de) * 2002-12-10 2004-07-08 Fh Stralsund Package für ein modulares Baukastensystem
WO2005048345A1 (fr) * 2003-11-14 2005-05-26 Fachhochschule Stralsund Systeme de conditionnement d'ensembles modulaires et procede pour fabriquer des systemes de conditionnement
EP1543558A2 (fr) * 2002-08-07 2005-06-22 Avery Dennison Corporation Dispositif et procede d'identification de frequence radio
EP1610597A1 (fr) * 2004-06-22 2005-12-28 Technomedica AG Précipitation du cuivre pour la fabrication des pistes conductrices
WO2007045436A1 (fr) * 2005-10-18 2007-04-26 Uvasol Limited Procédé de préparation d’un dispositif à circuit conducteur
US7656018B2 (en) 2005-06-01 2010-02-02 Infineon Technologies Ag Package for an electronic component and method for its production
US8021919B2 (en) 2009-03-31 2011-09-20 Infineon Technologies Ag Method of manufacturing a semiconductor device
CN111278231A (zh) * 2020-02-17 2020-06-12 清华大学 激光诱导碳基电子元件的柔性转印方法

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US5378508A (en) * 1992-04-01 1995-01-03 Akzo Nobel N.V. Laser direct writing
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US4526807A (en) * 1984-04-27 1985-07-02 General Electric Company Method for deposition of elemental metals and metalloids on substrates
US4869930A (en) * 1987-07-10 1989-09-26 International Business Machines Corporation Method for preparing substrates for deposition of metal seed from an organometallic vapor for subsequent electroless metallization
US4880959A (en) * 1988-10-26 1989-11-14 International Business Machines Corporation Process for interconnecting thin-film electrical circuits
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Publication number Priority date Publication date Assignee Title
EP1543558A2 (fr) * 2002-08-07 2005-06-22 Avery Dennison Corporation Dispositif et procede d'identification de frequence radio
EP1543558A4 (fr) * 2002-08-07 2007-04-18 Avery Dennison Corp Dispositif et procede d'identification de frequence radio
DE10258478A1 (de) * 2002-12-10 2004-07-08 Fh Stralsund Package für ein modulares Baukastensystem
WO2005048345A1 (fr) * 2003-11-14 2005-05-26 Fachhochschule Stralsund Systeme de conditionnement d'ensembles modulaires et procede pour fabriquer des systemes de conditionnement
EP1610597A1 (fr) * 2004-06-22 2005-12-28 Technomedica AG Précipitation du cuivre pour la fabrication des pistes conductrices
WO2005125291A1 (fr) * 2004-06-22 2005-12-29 Technomedica Ag Depot de cuivre pour produire des traces conducteurs
US7656018B2 (en) 2005-06-01 2010-02-02 Infineon Technologies Ag Package for an electronic component and method for its production
WO2007045436A1 (fr) * 2005-10-18 2007-04-26 Uvasol Limited Procédé de préparation d’un dispositif à circuit conducteur
WO2007046694A1 (fr) * 2005-10-18 2007-04-26 Vipem Hackert Gmbh Procede pour preparer une fonction conductrice sur un substrat
US8021919B2 (en) 2009-03-31 2011-09-20 Infineon Technologies Ag Method of manufacturing a semiconductor device
DE102010016229B4 (de) * 2009-03-31 2018-12-20 Infineon Technologies Ag Verfahren zur Herstellung eines Halbleiterbauelements und eines Substrats mit Schaltungsverbindungen
CN111278231A (zh) * 2020-02-17 2020-06-12 清华大学 激光诱导碳基电子元件的柔性转印方法
CN111278231B (zh) * 2020-02-17 2021-03-02 清华大学 激光诱导碳基电子元件的柔性转印方法

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