WO2002067291A3 - Anordnung eines halbleiterchips auf einem substrat - Google Patents

Anordnung eines halbleiterchips auf einem substrat Download PDF

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Publication number
WO2002067291A3
WO2002067291A3 PCT/DE2002/000339 DE0200339W WO02067291A3 WO 2002067291 A3 WO2002067291 A3 WO 2002067291A3 DE 0200339 W DE0200339 W DE 0200339W WO 02067291 A3 WO02067291 A3 WO 02067291A3
Authority
WO
WIPO (PCT)
Prior art keywords
semi
substrate
conductor chip
arrangement
distance
Prior art date
Application number
PCT/DE2002/000339
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English (en)
French (fr)
Other versions
WO2002067291A2 (de
Inventor
Holger Huebner
Original Assignee
Infineon Technologies Ag
Holger Huebner
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Holger Huebner filed Critical Infineon Technologies Ag
Publication of WO2002067291A2 publication Critical patent/WO2002067291A2/de
Publication of WO2002067291A3 publication Critical patent/WO2002067291A3/de

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    • H—ELECTRICITY
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

Die Kontaktflächen (3) des Halbleiterchips (1) und des Substrates sind einander gegenüberliegend angeordnet und elektrisch leitend miteinander verbunden, wobei der Abstand zwischen den Kontaktflächen weniger als 10 ν beträgt. Bei bevorzugten Ausführungsformen ist dieser Abstand nur typisch 2 ν, was mit dem Verfahren der Diffusionslöttechnik (SOLED) hergestellt werden kann. Zur Verbindung von Halbleiterchip und Substrat können weitere Metallflächen (2) vorhanden sein.
PCT/DE2002/000339 2001-02-20 2002-01-31 Anordnung eines halbleiterchips auf einem substrat WO2002067291A2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10108081A DE10108081B4 (de) 2001-02-20 2001-02-20 Anordnung eines Halbleiterchips auf einem Substrat
DE10108081.6 2001-02-20

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WO2002067291A2 WO2002067291A2 (de) 2002-08-29
WO2002067291A3 true WO2002067291A3 (de) 2002-11-14

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PCT/DE2002/000339 WO2002067291A2 (de) 2001-02-20 2002-01-31 Anordnung eines halbleiterchips auf einem substrat

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WO (1) WO2002067291A2 (de)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004046699A1 (de) * 2004-09-24 2006-04-13 Infineon Technologies Ag Anordnung zum Verbinden von Kontaktflächen durch eine sich verfestigende Flüssigkeit
DE102004055677A1 (de) * 2004-11-18 2006-06-01 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Chipträgerverbund und Verfahren zum Herstellen eines Chipträgerverbunds
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