WO2002054491A2 - Cu-pad/bonded/cu-wire with self-passivating cu-alloys - Google Patents

Cu-pad/bonded/cu-wire with self-passivating cu-alloys Download PDF

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Publication number
WO2002054491A2
WO2002054491A2 PCT/US2001/043960 US0143960W WO02054491A2 WO 2002054491 A2 WO2002054491 A2 WO 2002054491A2 US 0143960 W US0143960 W US 0143960W WO 02054491 A2 WO02054491 A2 WO 02054491A2
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WO
WIPO (PCT)
Prior art keywords
pad
alloy
wire
layer
self
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2001/043960
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English (en)
French (fr)
Other versions
WO2002054491A3 (en
Inventor
Hans-Joachim Barth
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Infineon Technologies North America Corp
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Infineon Technologies North America Corp
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Filing date
Publication date
Application filed by Infineon Technologies North America Corp filed Critical Infineon Technologies North America Corp
Priority to JP2002555483A priority Critical patent/JP3737482B2/ja
Priority to EP01987076A priority patent/EP1348235A2/en
Priority to KR1020037008825A priority patent/KR100542120B1/ko
Publication of WO2002054491A2 publication Critical patent/WO2002054491A2/en
Publication of WO2002054491A3 publication Critical patent/WO2002054491A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/015—Manufacture or treatment of bond wires
    • H10W72/01551—Changing the shapes of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/015—Manufacture or treatment of bond wires
    • H10W72/01571—Cleaning, e.g. oxide removal or de-smearing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07511—Treating the bonding area before connecting, e.g. by applying flux or cleaning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/076—Connecting or disconnecting of strap connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/521—Structures or relative sizes of bond wires
    • H10W72/522—Multilayered bond wires, e.g. having a coating concentric around a core
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5524—Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5525—Materials of bond wires comprising metals or metalloids, e.g. silver comprising copper [Cu]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/555—Materials of bond wires of outermost layers of multilayered bond wires, e.g. material of a coating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/925—Bond pads having a filler embedded in a matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/934—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu

Definitions

  • the invention relates to wire bonding of Cu-Pads with Cu- wires using self-passivating Cu-alloys.
  • the self-passivation layer resulting from the dopant rich Cu-alloy protects the Cu from corrosion and oxidation.
  • the exposed Cu layer would be highly susceptible corrosion and oxidation.
  • the common layered surface finish metallurgies for circuit carrier wirebonding applications are of a nickel (Ni) underplating coating covered by a surface overplating coating layer of gold (Au) , palladium (Pd) , or silver (Ag) .
  • These layered surface finish treatments inhibit diffusion of underlying copper (Cu) circuit metallization to the surface of the overplate and prevent subsequent oxidation of the wirebond pad surfaces .
  • Considerable oxidation of pad surfaces prior to wirebonding can otherwise result in both inability to wirebond with high yield and deterioration of wirebond interconnection reliability.
  • Use of these overplating treatments on copper pads has been used to provide both high yield and high reliability wirebond interconnections.
  • US Patent 5,632,438 disclose a direct chip attachment process for aluminum wirebonding on copper circuitization comprising: passing one integrated circuit chip to a carrier; applying to the carrier an attached integrated circuit chip an aqueous cleaning solution containing citric and oxalic acid based additives; applying to the carrier and attached integrated circuit chip a rinse; and wirebonding on copper circuitization carried by the carrier.
  • a method for improving bond ability for deep-submicron integrated circuit packages is disclosed in US Patent 6,110,816.
  • the method comprises: providing a semiconductor substrate having a top electrically conducting layer, and an overlying layer covering the top electrically conducting layer, and a photoresist applied to the overlying layer; patterning the photoresist to form an array of submicron size holes; etching openings through the overlying layer to the top electrically conducting layer, and forming a rough textured surface profile in the top electrically conducting layer through the opening of the overlying layer; and depositing a passivation film over the overlying layer and forming wiring pad windows for wire ball bonding.
  • One object of the present invention is to provide Cu-wire bonded to Cu-pads in a manner so as to provide good bond quality and low resistance, in which the Cu is characterized by self-passivation.
  • Another object of the present invention is to provide Cu- wire bonded on Cu-pads in a manner so as to provide good bond quality and low resistance, whereby the Cu-wire bonded on Cu- pads is resistant to corrosion and oxidation due to use of self-passivating Cu-alloys.
  • a further object of the present invention is to provide Cu-wire bonded on Cu-pads to provide good bond quality and lower resistance, by using Cu-wire and Cu-pads fabricated to 100% out of Cu-alloys, to provide Cu-wire bonded to Cu-pads, where the Cu is resistant to corrosion and oxidation due to use of self-passivating Cu-alloys.
  • a yet further object of the present invention is to provide, Cu-wire bonded to Cu-pads, in which the wire is either a solid Cu-alloy wire or a bi-layer Cu-wire, with an inner core consisting of the Cu-alloy and the outer core being pure Cu, so as to provide good bondability and bond quality upon bonding the copper wire to Cu-pads, to achieve self- passivation from the Cu-alloy.
  • a further object yet still of the present invention is to provide Cu-wire bonded to Cu-pads wherein the Cu-wire is a bi- layer and the Cu-pad is a bi-layer (Cu-alloy seed layer + pure Cu-fill) to achieve self-passivation and therefore resistance to corrosion and oxidation.
  • good bondability and good bond quality coupled with resistance to corrosion and oxidation is obtained when wire bonding of Cu-pads with Cu- wires is performed using Cu-alloys (Cu-Al, Cu-Mg, and Cu-Li) .
  • FIG. 1 shows a Cu-alloy wire prior to bonding with a Cu- pad, in which the Cu pad is surrounded by a Cu-alloy, which is surrounded by a liner, all of which is disposed in a dielectric.
  • FIG. 2 shows a Cu-alloy wire after wirebonding and annealing to a Cu-pad, in which the formed bond is either a ball or wedge, and in which there is a dopant rich interface layer characterized by self-passivation, as shown by the X's.
  • the wirebonding of Cu-pads with Cu-wires using self-passivating Cu-alloys for making a semiconductor device or integrated circuit is prepared by the following process sequence : a) Patterning a (dual-) damascene structure in dielectric to form the wiring and the bond pads; b) Depositing a metallic liner (PVD, CND , electroless, or other art known method (this step may be optional by using the optimum amount of Cu-alloy) ; c) Depositing Cu-alloy as seed-layer for final Cu-fill
  • dielectric cap layer (Cu-diffusion barrier, Si- ⁇ itride, Blok or other art known methods) . It is possible to eliminate this dielectric diffusion barrier totally and continue the processing with Si0 2 deposition or the deposition of other dielectric materials (e.g. low k materials) .
  • dielectric cap layer (Cu diffusion barrier, Si- ⁇ itride, Blok or other art known methods) ; 8) Annealing (temperature range: 250°C-450°C) to form self-passivating dopant rich layer at the Cu-dielectric cap layer interface and at the Cu-liner interface.
  • Post CMP annealing in a temperature range: 250 °C- 400 °C, this temperature is lower when compared to 9) .
  • the post cap layer anneal is approximately 50 °C to form a partially self-passivating dopant rich layer at the Cu-surface and at the Cu-liner interface. It is beneficial to start with a gradual temperature increase to suppress hillock formation. After the initial (partial) formation of a dopant-rich surface layer the hillock formation is significantly reduced;
  • the dielectric cap layer (Cu diffusion barrier, Si-Nitride, Blok or other art known methods) . It is possible to eliminate this dielectric diffusion barrier totally and continue the processing with Si0 2 deposition or the deposition of other dielectric materials (e.g. low k materials) ;
  • Post cap layer annealing (temperature range: 300 °C - 450 °C, approximately 50 °C higher than 7) post CMP anneal, to form the final self-passivation layer on the liner and cap layer interface.
  • This approach with the two anneal steps 7) and 8) is beneficial with respect to hillock formation and adhesion.
  • an additional step may be introduced to form the self-passivating/protective layer on the probed Cu surface. Shortly before bonding, this layer is removed by wet cleans in order to have a clean Cu-pad surface for optimum bond quality.
  • FIG. 1 depicts a Cu-alloy wire 10 prior to bonding with the Cu-pad 11.
  • the Cu-pad is surrounded by a Cu-alloy 12, which in turn is separated from the dielectric 13 by a liner 14.
  • a polyimide 15 may be deposited on top of the dielectric.
  • the passivated dopant rich interface layer 16 and self-passivated Cu-surface 17, both of which are designated by X' s are formed.
  • the self passivation is around the Cu-alloy, around the bond ball or wedge 18, and at the juncture of the pad and wire joinings.
  • This dopant rich self-passivating layer is free from hillock structures and protects the Cu from corrosion, oxidation and out-diffusion of Cu into the surrounding semiconductor device areas .
  • the Cu-alloys may be Cu- Al, Cu-Mg, Cu-Li as well as other well-known Cu-alloys, and the concentration of the non-Cu doping material from the other component of the Cu-alloy will range from about 0.1 to about 5.0% atomic weight percent of the Cu-alloy.
  • Wirebonding of Cu-pads with Cu-wires using self- passivating Cu-alloys is particularly important for improving bondability coupled with protecting the Cu from corrosion and oxidation by virtue of the self-passivation induced by the invention process.
  • the Cu-pads with Cu-wires using self- passivating Cu-alloys provides comparable bond quality and low resistance to pure Cu-wire bonded on pure Cu-pads and also provides the self-passivation effect not obtained with pure Cu-wire bonded on pure Cu-pads.
  • the bi- layer Cu-wire in combination with a bi-layer Cu-pads exhibits optimum characteristics of self-passivation + low resistance and high bond strength.

Landscapes

  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
PCT/US2001/043960 2000-12-28 2001-11-14 Cu-pad/bonded/cu-wire with self-passivating cu-alloys Ceased WO2002054491A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2002555483A JP3737482B2 (ja) 2000-12-28 2001-11-14 自己不動態化Ｃｕ合金を用いて接着されたＣｕパッド／Ｃｕワイヤ
EP01987076A EP1348235A2 (en) 2000-12-28 2001-11-14 Cu-pad bonded to cu-wire with self-passivating cu-alloys
KR1020037008825A KR100542120B1 (ko) 2000-12-28 2001-11-14 집적 회로 구조체와 그 마련 공정

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/751,479 US6515373B2 (en) 2000-12-28 2000-12-28 Cu-pad/bonded/Cu-wire with self-passivating Cu-alloys
US09/751,479 2000-12-28

Publications (2)

Publication Number Publication Date
WO2002054491A2 true WO2002054491A2 (en) 2002-07-11
WO2002054491A3 WO2002054491A3 (en) 2003-06-05

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Country Status (6)

Country Link
US (1) US6515373B2 (https=)
EP (1) EP1348235A2 (https=)
JP (1) JP3737482B2 (https=)
KR (1) KR100542120B1 (https=)
CN (1) CN1296997C (https=)
WO (1) WO2002054491A2 (https=)

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Also Published As

Publication number Publication date
US20020084311A1 (en) 2002-07-04
CN1484857A (zh) 2004-03-24
EP1348235A2 (en) 2003-10-01
US6515373B2 (en) 2003-02-04
WO2002054491A3 (en) 2003-06-05
CN1296997C (zh) 2007-01-24
KR100542120B1 (ko) 2006-01-11
KR20040018248A (ko) 2004-03-02
JP2004517498A (ja) 2004-06-10
JP3737482B2 (ja) 2006-01-18

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