WO2002047134A1

WO2002047134A1 - Stencil mask and manufacturing method thereof

Info

Publication number: WO2002047134A1
Application number: PCT/JP2001/010638
Authority: WO
Inventors: Mitsuhiro Yuasa
Original assignee: Tokyo Electron Limited
Priority date: 2000-12-06
Filing date: 2001-12-05
Publication date: 2002-06-13
Also published as: JP2006173142A; AU2002221058A1

Abstract

A stencil mask is manufactured by using a silicon-on-insulator substrate, which has a silicon base layer and an SOI layer formed on the silicon base layer via an embedded oxide film. A first resist film is formed on said silicon base layer, the first resist film having a desired resist pattern. The silicon base layer is removed by using said first resist film as a mask so as to expose the embedded oxide film and form a cavity part defined by the embedded oxide film and the sidewalls of the silicon base layer. The embedded oxide film is removed, and the first resist film is exfoliated. Then, a filling material is filled in the cavity part. A second resist film is formed on the SOI layer, and the SOI layer is removed by using the second resist film as a mask.

Description

DESCRIPTION

STENCIL MASK AND MZ-NUFACTURING METHOD THEREOF

TECHNICAL FIELD

The present invention generally relates to masks for electron beam reduction projection exposure and manufacturing methods thereof, and, more particularly, to a stencil mask and a membrane mask for electron beam lithography and a manufacturing method thereof.

BACKGROUND ART

The technology, which has realized high integration of semiconductor integrated circuits, is ultra-fine processing technology.

In the ultra-fine processing technology, the lithography technology for forming a pattern on a semiconductor substrate has played a central role. The lithography technology consists of three elemental techniques such as an exposure device for exposure, a mask used as an original plate of a pattern and a resist process technique for forming a pattern. Although the optical lithography technology is currently a mainstream technology for a light source used for exposure, the electron beam lithography, which can process an ultra-fine pattern that cannot be formed by the optical lithography technology, has attracted attention as a future processing method. Especially, in order to enable formation of an ultra-fine pattern, a highly precise stencil mask for electron beam lithography is required in the ultra-fine processing technology using the electron beam lithography to which a pattern of 0.1 μm or less is required as a minimum size. The stencil mask in the present specification refers to a mask which is used for exposure in which, when an electron beam is irradiated onto the mask, the electron beam is transmitted only in an opening part and the transmitted electron beam is irradiated onto a resist on a semiconductor substrate.

A description will be given below, with reference to drawings , of a manufacturing method of a stencil mask.

FIG. 1 shows cross-sectional views of a stencil mask in each manufacturing process step according to a conventional technique. The manufacturing process of the stencil mask will be explained, as shown in FIG. 1- (A) , by referring to an SOI (silicon on insulator) substrate, which has an SOI layer 10 on a silicon base layer 14 via a BOX layer 12 which is an embedded oxidization film. As the BOX layer, Si02 is used in many cases. A well-known resist film 16 is applied to the Si base layer 14 on the back side of the SOI substrate, and a resist film 16 having a desired resist pattern is formed according to a lithography process. Subsequently, as shown in FIG. 1-(B), dry etching of the Si base layer 14 is carried out by anisotropic etching using an etching gas such as a halogen containing gas by using the above-mentioned resist film 16 as a mask so as to expose the BOX layer 12. Then, after carrying out dry etching of the BOX layer 12 using F radicals of CF₄ and the like, the above-mentioned resist film 16 is exfoliated by ashing using oxygen plasma (FIG. 1-(C)). Thereafter, as shown in FIG. 1- (D) , a resist film 18 is applied to the front side of the SOI layer 10 and patterning is performed using electron beam lithography etc. so as to form a resist film 18 having a desired resist pattern. Then, dry-etching of the SOI layer 10 is carried out by anisotropic etching using an etching gas such as a halogen containing gas by using the above- mentioned resist film 18 as a mask. Then, the above- mentioned resist film 18 is caused to exfoliate by ashing using plasma containing oxygen, and the stencil mask is completed (FIG. 1- (E) ) .

The above mentioned is an outline of the manufacturing method of the stencil mask usually performed. However, considering the above-mentioned manufacturing process , there are various large factors that affect accuracy and yield of the manufactured stencil mask.

For example, although a resist film is applied on the silicon substrate after dry-etching the BOX layer, the resist film (the resist film 18 in FIG. 1- (D) ) is usually formed by a spin coat method. As shown in FIG. 2A, in case a spin coat is carried out, the SOI substrate is fixed by vacuum chucking and the resist is applied. In such as case, the SOI layer has a very small thickness of about 2 μm. For this reason, if cavity parts 25 exist between the SOI layer and a vacuum chuck table, there is a high probability that destruction or distortion generates in the SOI layer 20 when an atmospheric pressure is exerted on the SOI layer 20. If the SOI layer 20 is destroyed, subsequent mask manufacture may become difficult and the yield may fall. Moreover, when such distortion occurs, stress is generated in the SOI layer 20. When the stress generated in the above-mentioned SOI layer 20 is relaxed during a subsequent lithography process, the resist pattern deviates from a predetermined pattern and there is a possibility of having an undesired influence on the pattern accuracy of the completed stencil mask.

Moreover, even if the above-pointed destruction or distortion does not occur in the SOI layer 20, the process of etching the SOI layer 20 is performed while fixing usually the SOI substrate by electrostatic chucking. In the fixation by electrostatic chucking, if there are cavity parts existing between the SOI layer 20 and the electrostatic chucking table as shown in FIG. 2B, the attraction force caused by the electrostatic attraction is reduced by a distance equivalent to the height of the cavity parts (the height of the cavity parts is indicated by arrows in FIG. 2B) .

In a dry etching process, if there are cavity part, an abnormal discharge may occur due to concentration of electric charge at a corner of cavity parts. Moreover, if the SOI layer 20 is etched simultaneously and uniformly, the entire SOI layer 20 is removed at the same time. However, there is a possibility that ions and radicals pass through a portion of which etching is completed faster than other portions and the ions and radicals reach the electrostatic chucking table, which may give damage to the electrostatic chucking table (an arrow shown in FIG. 2C illustrates the above-mentioned phenomenon) . Furthermore, FIG. 3A is a cross-sectional view for briefly explaining a mechanism for adjusting a temperature when dry etching is being carried out. A susceptor 30 has cooling gas introducing ports 32 for temperature adjustment and is used for adjusting the temperature etching is performed. If the SOI substrate is placed on the susceptor with the SOI layer facing upward so as to dry-etch the SOI layer 34 of which the Si base layer 38 and the BOX layer 36 are processed, cavity parts exist between the susceptor 30 and the SOI substrate as apparent from FIG. 3A. Although a gas is introduced through the above-mentioned cooling gas introducing ports 32 so as to control a temperature during etching, deviation may arise with the gas flow due to the existence of the cavity parts 35. That is, some of the cooling gas introducing ports 32 in a certain portion are closed; some of the cooling gas introducing ports 32 in another portion are partially closed; and some of the cooling gas introducing port 32 in different portions are not closed. For this reason, is considered that the cooling gas is not used in the dry-etching process. However, is the cooling gas is not used in the dry-etching process, it is difficult to control a temperature when the etching process is performed. Therefore, it is necessary to provide to each of the cavity parts one or more cooling gas introducing port smaller than each cavity part. However, provision of such a cooling gas introducing port causes the susceptor per se being extremely expensive, and a highly accurate positioning of the substrate being required.

FIG. 3B is an illustrative cross-sectional view for explaining movement of heat due to bombardment of ions and the like during ion etching. It is known that an etching process of silicon is usually a process with temperature dependency. Although there is no resist film on the SOI layer 34 in the figure, heat is generated due to bombardment of ions in association with the etching of the silicon substrate 34 since reacting species (ions and the like) collide with the resist film or the silicon substrate 34 in a direction from a top to a bottom in the figure during the etching.

In order to give detailed explanation, an enlarged view of a circled part of FIG. 3B is shown in FIG. 4A in which the SOI substrate of which the Si base layer 46 and the BOX layer 44 were processed is placed on the susceptor 48 with a resist film 40 applied to the SOI layer 42 of the SOI substrate facing upward. The cavity parts 45 are formed between the SOI layer 42 and the susceptor 48. After forming the desired resist pattern 40 on the SOI layer 42, the SOI layer 42 is dry-etched by using the above-mentioned resist pattern 40 as a mask. Although in this case heat is generated sue to bombardment of ions and the like as explained with reference to FIG. 3B, the conductivity of the heat generated at the time of etching on the cavity parts 45 is larger in a horizontal direction than in a vertical direction in the SOI layer 42 This is because it is assumed that the cavity parts 45 provide an insulating effect with respect to the generated heat. In FIG. 4A, arrows illustrate movement of heat. Therefore, a temperature slope arises at the time of etching of the SOI layer 42 on the cavity part 45. FIG. 4B is a graph showing the temperature slope with a horizontal axis representing a position of the SOI substrate of FIG. 4A and a vertical axis representing a temperature. Since etching of silicon has temperature dependency as mentioned above, the temperature slope as shown in FIG. 4B affects etching of the SOI layer 42, and since it is difficult to perform a temperature control which is important at the time of fine processing of silicon, the etching may not progress in the form matching the resist film 40. Especially, the temperature control at the time of etching of an SOI layer is very important for appropriately controlling the temperature at the time of etching since the temperature control gives great influence to a mask manufacturing apparatus and the accuracy of the completed stencil mask.

DISCLOSURE OF INVENTION

It is a general object of the present invention to provide an improved and useful stencil mask and a manufacturing method thereof in which the above-mentioned objects are eliminated.

A more specific object of the present invention is to provide a stencil mask having an improved accuracy of formation as a mask and an improved yield as a mask manufacturing efficiency, and a manufacturing method thereof.

In order to achieve the above-mentioned objects , there is provided according to one aspect of the present invention a manufacturing method of a stencil mask using a silicon-on-insulator substrate, which has a silicon base layer and an SOI layer formed on the silicon base layer via an embedded oxide film, the manufacturing method comprising: a first forming step of forming a first resist base layer on the silicon base layer, the first resist film having a desired resist pattern; a first removing step of removing the base layer by using the first resist film as a mask so as to cause the embedded oxide film to be exposed and form a cavity part defined by the embedded oxide film and the sidewalls of the silicon base layer; a second removing step of removing the embedded oxide film; a first exfoliating step of exfoliating the first resist film; a filling step of filling a filling material in the cavity part; a second forming step of forming a second resist film on the SOI layer, the second resist film having a desired resist pattern; a third removing step of removing the SOI layer by using the second resist film as a mask; and a second exfoliating step of exfoliating the second resist film.

Additionally, there is provided according to another aspect of the present invention a manufacturing method of a stencil mask using a silicon-on-insulator substrate, which has a base layer and an SOI layer formed on the silicon base layer via an embedded oxide film, the manufacturing method comprising: a first forming step of forming a first resist film on the silicon base layer, the first resist film having a desired resist pattern; a first removing step of removing the silicon base layer by using the first resist film as a mask so as to cause the embedded oxide film to be exposed and form a cavity part defined by the embedded oxide film and sidewalls of the silicon base layer; a second removing step of removing the embedded oxide film; a first exfoliating step of exfoliating the first resist film; a second forming step of forming a second resist film on the SOI layer, the second resist film having a desired resist pattern; a filling step of filling a filling material in the cavity part; a third removing step of removing the SOI layer by using the second resist film as a mask; and a second exfoliating step of exfoliating the second resist film.

The manufacturing method of a stencil mask according to the present invention may further comprise a fourth removing step of removing the filling material after the second exfoliating process. The filling step may be carried out by one of a spin coat method and a chemical vapor deposition method. The filling material may be selected from a group consisting of an SOG film, an Si0₂ film, an organic SOG film and an organic resist film. Alternatively, the filling material may be selected from a group consisting of aluminum and solder. When the filling material is an Si02 film, the fourth removing step may be carried out by wet-etching using hydrofluoric acid (HF) or a mixture of hydrofluoric acid (HF) and ammonium fluoride (NH₄F) .

There is provided according to another aspect of the present invention a stencil mask blank formed of a silicon-on-insulator substrate having a silicon base layer, an embedded oxide film provided to the silicon base layer and an SOI layer provided to the oxide film, the stencil mask blank comprising; a filling material filled in a cavity part which is defined by the embedded oxide film and sidewalls of the silicon base layer by removing the silicon base layer so as to expose the embedded oxide film.

In the stencil mask blank according to the present invention, the filing material may be filled by one of a spin coat method and a chemical vapor deposition method. The filling material maybe selected from a group consisting of an SOG film, an Si0₂ film, an organic SOG film and an organic resist film. Alternatively, the filling material may be selected from a group consisting of aluminum and solder. A stencil mask may be formed by removing the filling material.

Additionally, there is provided according to another aspect of the present invention a manufacturing method of a membrane mask using a substrate having a silicon substrate and first and second silicon nitride films formed on the silicon substrate, the manufacturing method comprising: a first forming step of forming a first resist film on the first silicon nitride film, the first resist film having a desired resist pattern; a first removing step of removing the first silicon nitride film by using the first resist film as a mask so as to cause the silicon substrate to be exposed; a first exfoliating step of exfoliating the first resist film; a second forming step of sequentially forming a first Cr film, a W film and a second Cr film on the second silicon nitride film; a second removing step of removing the silicon substrate by using the first silicon nitride film as a mask so as to expose the second silicon nitride film and form a cavity part which is defined by the exposed second silicon nitride film, the first silicon nitride film and sidewalls of the silicon substrate; a second exfoliating step of exfoliating the first Cr film; and a filling step of filling a filling material in the cavity part. The manufacturing method of a membrane mask according to the present inventions may further comprise: a third forming step of forming a second resist film on the W film, the second resist film having a predetermined pattern; a third removing step of removing the W film and the second Cr film by using the second resist film as a mask; a third exfoliating step of exfoliating the second resist film; and a fourth removing step of removing the filling material .

The filling step may be carried out by one of a spin coat method and a chemical vapor deposition method. The filling material may be selected from a group consisting of an SOG film, an Si0₂ film, an organic SOG film and an organic resist film. Alternatively, the filling material may be selected from a group consisting of aluminum and solder. When the filling material is an Si0₂ film, the fourth removing step may be carried out by wet-etching using hydrofluoric acid (HF) or a mixture of hydrofluoric acid (HF) and ammonium fluoride (NH₄F) .

Additionally, there is provided according to another aspect of the present invention a membrane mask blank formed of a substrate having a silicon substrate and first and second silicon nitride films provided to the silicon substrate; the membrane mask blank comprising: a filling material filled in a cavity part defined by the first silicon nitride film and sidewalls of the second silicon nitride films and the silicon substrate by removing the second silicon nitride film and the silicon substrate so as to expose the first silicon nitride film. In the membrane mask blank according to the present invention, the filing material may be filled by one of a spin coat method and a chemical vapor deposition method. The filling material may be selected from a group consisting of an SOG film, an Si0₂ film, an organic SOG film and an organic resist film. Alternatively, the filling material may be selected from a group consisting of aluminum and solder. A membrane mask may be formed by removing the filling material . As mentioned above, according to the present invention, the process of filling the filling material in the cavity part which is produced in the conventional manufacturing process of a stencil mask is provided. Thereby, all the problems generated in the subsequent process, such as a process of forming the resist film, a process of removing the silicon film by etching, etc., can be solved. That is, a mechanical strength of the substrate for the stencil mask is increased by the existence of the filling material.

Moreover, when forming the resist film by a spin coat method, the stencil mask can be produced without destruction or distortion of the substrate, thereby improving the production efficiency. Moreover, according to the existence of the filling material, the stencil mask can be produced without damaging electrostatic chucking table during the etching process of the substrate for the stencil mask, and, thus, a reduction in a production cost can be achieved. Furthermore, an accurate temperature control within the etching chamber can be carried out at the time of etching, and the etching of the silicon film can be carried out uniformly.

Other obj ects , features and advantages of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings .

BRIEF DESCRIPTION OF DRAWINGS FIG. 1 shows cross-sectional views of a stencil mask in each manufacturing process step according to a conventional technique;

FIGS. 2A, 2B and 2C are illustrations for explaining disadvantages in the manufacturing method of the stencil according to the conventional technique;

FIG. 3A is a cross-sectional view for explaining a mechanism for adjusting a temperature when dry etching is being carried out;

FIG. 3B is an illustrative cross-sectional view for explaining movement of heat due to bombardment of ions and the like during ion etching;

FIG. 4A is an enlarged view of a circled part in FIG. 3B;

FIG. 4B is a graph showing a temperature slope in the SOI substrate of FIG. 4A;

FIG. 5 shows cross-sectional views of a stencil mask in each manufacturing process step according to an embodiment of the present invention;

FIG. 6A is a cross-sectional view of the stencil mask in a state in which the filling material is placed on a susceptor;

FIG. 6B is a cross-sectional view of the stencil mask in a state in which the filling material is placed on an electrostatic chucking table;

FIG. 7 shows cross-sectional views for explaining each step of a manufacturing method of a stencil mask according to another embodiment of the present invention;

FIG. 8 shows cross-sectional views for explaining each step of a part of a manufacturing process of a membrane mask according to another embodiment of the present invention; FIG. 9 shows cross-sectional views for explaining each step of a part of the manufacturing process of the membrane mask according to another embodiment of the present invention; and FIG. 10 shows cross-sectional views for explaining each step of a part of the manufacturing process of the membrane mask according to another embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

A description will now be given of an embodiment of the present invention.

FIG. 5- (A) through (G) show cross-sectional views for explaining each step of a manufacturing method of a stencil mask according to the embodiment of the present invention.

A description will now be given, with reference to FIG. 5- (A) , of the manufacturing method according to the present embodiment using an SOI substrate which has an SOI layer 50, a silicon oxide as a BOX layer 52 which is an embedded oxidation film and a silicon base layer 54. A known resist film 56 is formed on a backside of the SOI substrate, of which surfaces are cleaned, by a usual method so that the resist film has a desired pattern. Subsequently, as shown in FIG. 5- (B) , anisotropic dry- etching of the silicon base layer 54 is performed by a halogen gas by using the resist film 56 as a mask so as to expose the BOX layer 52 so that a cavity part 55 is defined by sidewalls of the silicon base layer 54 and the BOX layer 52. As the anisotropic etching gas , a gas consisting of a halogen containing gas, Ar, etc. can be used. Thereafter, in the step shown in FIG. 5- (C) , the silicon oxide film 52 is dry-etched by using F base radicals such as CHF₃, C₄F₈ and CF₄, and the resist film 56 is exfoliated by ashing using oxygen plasma. After carrying out the ashing of the resist film 56, it is also possible, in the process of FIG. 5- (C) , to remove the oxidized silicon film 52 by wet-etching (HF or HF/NH₄F) .

Referring to FIG. 5- (D) , a resist film having a predetermined pattern is formed on the SOI layer on the front side of the SOI substrate. At this time, the formation of the pattern is normally carried out by using an electron beam.

Subsequently, as shown in FIG. 5- (E) , a filling material 59 is filled in the cavity part 55. The process shown in FIG. 5- (E) is preferably performed by a spin coat method or a chemical vapor deposition method. It is desirable that the filling material does not give large influence to the manufacturing process and can be filled at a temperature as low as possible. It is because distortion may occur in the SOI layer due to application of heat if the filling material is filled at a considerably high temperature. Specifically, an SOG film, an Si0₂ film, an organic SOG film and an organic resist film are preferably used. For example, the organic SOG film can be filled in the cavity part 55 by applying by a spin coat method and baking at 150°C for 30 seconds, at 200°C for 20 seconds or 450°C for 10 seconds. As the organic SOG film, there are a SiNCH film, a SiOCH film, etc. , for example. Moreover, as the organic resist film, there are organic resists such as a novolak base, an acrylic base or a styrene base, for example. Furthermore, it is also possible to fill a metal such as aluminum or solder in the cavity part 55.

There is no problem if the height of the filling material 59 is the same as or even higher than the height of the adjacent silicon base layer 54. However, if the height of the filling material 59 is higher, it is preferable that the surface of the filling material 59 is uniform. In FIG. 5- (E) , the meaning of the height of the filling material 59 being higher is that the surface of the filling material 59 is below the surface of the silicon base layer 54 in the drawing.

Subsequently, the SOI substrate shown in FIG. 5- (E) is etched in an etching chamber. A description will be given below of the significance of existence of the filling material 59. Existence of the filling material 59 prevents the damage of the electrostatic chucking table which is one of the problems explained with reference to FIG. 2C. Because, ions or radicals in the etching atmosphere cannot reach the electrostatic chucking table due to the existence of the filling material 59 if the etching does not progress uniformly, that is, for example, the etching progresses faster in a certain portion than other portions.

Moreover, the temperature at the time of etching can be well controlled. Specifically, as shown in FIG. 6A, a cooling gas flows from the cooling gas introducing ports 32 uniformly. Furthermore, referring to FIG. 6B, since the heat in the pattern part of the resist 58 on the cavity part, in the case where the filling material does not exist, flows to the electrostatic chucking table through the filling material 59 , the temperature slope in the pattern part becomes small , which allows a uniform temperature maintained in the pattern part. As mentioned above, since etching of the SOI layer 50 is a process with temperature dependency, when the filling material 59 exists , a temperature controllability is improved due to the existence of the filling part 59 rather than the case in which the empty cavity part is present. Therefore, etching of the SOI layer 50 progresses uniformly.

Because of the existence of the filling material 59, there is an advantage mentioned above. The SOI layer 50 is removed by using the resist film 58 as a mask in the same conditions as dry etching applied to the above- mentioned silicon base layer 54.

Thereafter, by exposing the resist film 58 to oxygen plasma atmosphere, the resist film 58 is made to exfoliate and the SOI substrate shown in FIG. 5-(F) is obtained. Then, the filling material 59 is removed by wet-etching using hydrofluoric acid or a mixture of hydrofluoric acid and ammonium fluoride. The stencil mask can be produced, as shown in FIG. 5- (G) , without damage to the mask manufacturing apparatus as compared to the conventional stencil mask.

FIG. 7- (A) through (E) show cross-sectional views for explaining each step of a manufacturing method of a stencil mask according to another embodiment of the present invention. Referring to FIG. 7, a description will be given of a manufacturing method of a stencil mask using the SOI substrate having an SOI layer 70 on a silicon base layer 74 via an oxidization silicon film 72 which is an embedded oxidization film. The process up to the process shown in FIG. 7- (A) is the same as the process of FIG. 5- (A) through FIG. 5- (C) . Although the resist film is formed on the SOI layer 50 (corresponding to the SOI layer 70 in FIG. 7) in the process shown in FIG. 5 after the cavity part 75 is formed, a filling material 79 is previously filled in the cavity part 75 as shown in FIG. 7- (B) . The illing method and the filing material in this case are the same as that of the process explained with reference to FIG. 5. The SOI substrate obtained by the process of FIG.

7- (B) is used in a subsequent resist film forming process as a mask blank for manufacturing a stencil mask, and the SOI substrate is easy to handle since the SOI substrate has the filling material 79 which increases a mechanical strength. Subsequently, in the process of FIG. 7- (C) , the SOI substrate obtained by the process of FIG. 7- (B) is placed on a vacuum chucking table, and a resist film 78 having a desired pattern is formed on the SOI layer 70 by a spin coat method. Since the filling material 79 is filled in the cavity part 75, even if atmospheric pressure acts on the SOI layer 70 during the spin coat, there is almost no possibility of the SOI layer 70 being destroyed or distorted. In this manufacturing method, since the resist film 78 having a desired pattern is formed in a state where there is no distortion, stress relaxation due to the above-mentioned distortion does not occur in a subsequent manufacturing process. Additionally, since the etching is performed by following the resist pattern, it is considered that there is no influence to the accuracy of the form of the mask.

Then, the SOI layer 70 is etched by the above- mentioned method using the resist film 78 as a mask, and the resist film 78 is exfoliated by ashing. Thus, the SOI layer 70 can be produced with the mask pattern matching the resist film 78.

Finally, the stencil mask is completed by removing the filling material 79 in the same manner as that explained with reference to FIG. 5. As explained with reference to FIG. 6, it is apparent from the existence of the filling material 79 that the temperature control at the time of etching is improved also by the manufacturing method shown in FIG. 7. Furthermore, comparing to the method of FIG. 5, the method explained with reference to FIG. 7 has advantages in respect of the following. That is, when the filling material 79 is filled before the resist film 78 is formed, the problem (refer to FIG. 2A) , which arises in a subsequent resist film applying process, can be solved.

Next, a description will be given below of a case in which the concept of introduction of the filling material mentioned above is applied to manufacture of a membrane mask. FIG. 8 through FIG. 10 are cross-sectional views for explaining each step of a manufacturing method of a membrane mask according to another embodiment of the present invention. Silicon nitride films 81 and 82 are deposited on upper and lower sides of a silicon substrate 80 by a low- pressure chemical vapor deposition method (LPCVD) as shown in FIG. 8- (A) . The thickness of the silicon nitride films is preferably 1000-1500 Angstrom. A resist film 83 having a desired pattern is formed on the silicon nitride film 82 on the backside of the silicon substrate 80 (refer to FIG. 8- (B) ) . In the process shown in FIG. 8- (C) , dry-etching of the silicon nitride film 82 is carried out using a gas containing H such as CHF₃ or CH₂F₂ by using the resist film 83 as a mask. Subsequently, the resist film 83 is exfoliated by ashing using oxygen plasma so that the silicon substrate 80 is exposed and a window of a membrane mask is formed.

In the process of FIG. 8- (D) , a Cr/W/Cr (84/85/86) film is formed by a PVD or plasma-CVD method on the silicon nitride film 81 of the front side of the silicon substrate 80. It is preferred that the thickness of the Cr/W/Cr (84/85/86) film in this case is 50/250/50 Angstrom. Then, the silicon substrate 80 of which backside is exposed is dry-etched using the silicon nitride film as a mask as shown in FIG. 9- (E) by using the silicon nitride film 82 as a mask so as to form a cavity part 90. The dry-etching is preferably performed by anisotropic dry-etching using halogen, containing gas such as SF6. Subsequently, in the process shown in FIG. 9- (F) , the Cr film 84 is removed by an etchant which consists of 13 to 18 weight percent of second cerium ammonium nitride ( (NH₄) ₂Ce₆ (N0₃) ε) , 3 to 5 weight percent of perchloric acid (HCLO₄) and 77 to 84 weight percent of pure water (H0) .

Next, in the process shown in FIG. 9- (G) , a filling material 100, which is a feature of the present invention, is filled in the cavity part 90. The filling process shown in FIG. 9- (G) is preferably performed by a spin coat method or a chemical vapor deposition method, especially, by a spin coat method. It is preferable that the filling material 100 does not influence the manufacturing process and can be filled at a temperature as low as possible. This is because if the filling material is filled at a high temperature, distortion may occur in the membrane mask substrate. Specifically, an SOG film, an Si0₂ film, an organic SOG film and an organic resist film are preferably used. As for the organic SOG film, there are an SiNCH film, an SiOCH film, etc., for example. Moreover, as the organic resist film, there are organic resists of a novolak base, an acrylic base or a styrene base, for example. Furthermore, a metal such as aluminum or solder can be filled in the cavity part 90. With reference to FIG. 10- (H) through FIG. 10-

(J) , a resist film 87 having a desired pattern is formed on the W film 85, which is the front side of the silicon substrate 80 for the membrane mask obtained by the process up to the step of FIG. 9- (G) . Pattern formation in that case is usually performed using electron beam lithography. Subsequently, in the process shown in FIG. 10- (I), a W/Cr (85/86) film is removed by wet-etching using KOH by using the resist film 87 as a mask. At this time, the removal can be done by dry-etching using a halogen gas such as Cl₂. Then, the above-mentioned resist film 87 is exfoliated by ashing using oxygen plasma. Finally, in the process shown in FIG. 10- (j) , the filling material 100 is removed by wet-etching using HF or a mixture of HF and NH₄, and the membrane mask according to the preset invention is completed.

Similar to the manner explained in the manufacturing method of the stencil mask according to the present invention, the problems of the conventional manufacturing method are solved by the existence of the filling material 100 so as to provide the membrane mask, which improves production efficiency such as a yield rate. Moreover, the silicon substrate 80 obtained in the process of the rubidium 9- (G) is used in the subsequent resist film forming process as a mask blank for manufacturing a membrane mask. Furthermore, since mechanical strength also increases by the existence of the filling material 100, the Si substrate can be easily handled for manufacturing a membrane mask, (example)

First, a surface of an SOI substrate having a thickness of about 2 micrometer SOI layer was cleaned. A commercially available photoresist was applied and dried, the desired resist pattern was formed by photo lithography, and a silicon base layer on a reverse side of the SOI substrate is exposed. The exposed silicon base layer was removed by anisotropic dry-etching using SF₆ gas by using the resist pattern as a mask. Subsequently, Si0₂ film, which is a BOX layer, was removed by dry-etching using F radicals of CF₄, exposed to oxygen radical atmosphere, exfoliate the resist film by ashing within a barrel asher usually used, and a cavity part defined by the SOI layer, the sidewalls of the silicon base layer and the BOX layer. Subsequently, oxidization silicon material, which is a filling material, was laid underground by the spin coat method, and the stencil mask blank was obtained. Thereafter, a commercially available resist for electron beam was applied to the front side of the SOI substrate, and the resist was dried. Then, the resist having a desired pattern was formed using an electron beam. The SOI layer was dry-etched using the resist film as a mask, and, subsequently, the resist film was removed by ashing. Finally, the filling material was removed by wet- etching using hydrofluoric acid, and the stencil mask was completed.

The stencil mask blank in a state where the filling material according to the present invention was filled had a mechanical strength larger than that of a stencil mask blank having no filling material. Thereby, it became possible to stock the stencil mask blank. This makes it possible to manufacture a stencil mask suitably, when it is needed, and it contributes also to improvement in the productivity of the stencil mask.

Furthermore, with respect to the time of supplying the filling material, although the filling material was filled before forming the resist pattern on the surface of the SOI substrate in the above-mentioned example, the effect of the present invention can be obtained when the filing material is filled after the resist pattern is formed on the surface of the SOI substrate. The present invention is not limited to the specifically disclosed embodiments, and variations and modifications may be made without departing from the scope of the present invention.

Claims

1. A manufacturing method of a stencil mask using a silicon-on-insulator substrate, which has a silicon base layer and an SOI layer formed on said silicon base layer via an embedded oxide film, the manufacturing method comprising: a first forming step of forming a first resist film on said silicon base layer, the first resist film having a desired resist pattern; a first removing step of removing said silicon base layer by using said first resist film as a mask so as to cause said embedded oxide film to be exposed and form a cavity part defined by said embedded oxide film and said sidewalls of said silicon base layer; a second removing step of removing said embedded oxide film; a first exfoliating step of exfoliating said first resist film; a filling step of filling a filling material in said cavity part; a second forming step of forming a second resist film on said SOI layer, the second resist film having a desired resist pattern; a third removing step of removing said SOI layer by using said second resist film as a mask; and a second exfoliating step of exfoliating said second resist film.

2. A manufacturing method of a stencil mask using a silicon-on-insulator substrate, which has a silicon base layer and an SOI layer formed on the silicon base layer via an embedded oxide film, the manufacturing method comprising: a first forming step of forming a first resist film on said base layer, the first resist film having a desired resist pattern; a first removing step of removing said silicon base layer by using said first resist film as a mask so as to cause said embedded oxide film to be exposed and form a cavity part defined by said embedded oxide film and sidewalls of said silicon base layer; a second removing step of removing said embedded oxide film; a first exfoliating step of exfoliating said first resist film; a second forming step of forming a second resist film on said SOI layer, the second resist film having a desired resist pattern; a filling step of filling a filling material in said cavity part; a third removing step of removing said SOI layer by using said second resist film as a mask; and a second exfoliating step of exfoliating said second resist film.

3. The manufacturing method of a stencil mask as claimed in claim 1 or 2 , further comprising a fourth removing step of removing said filling material after said second exfoliating process.

4. The manufacturing method of a stencil mask as claimed in claim 1 or 2, wherein said filling step is carried out by one of a spin coat method and a chemical vapor deposition method.

5. The manufacturing method of a stencil mask as claimed in claim 1 or 2 , wherein said filling material is selected from a group consisting of an SOG film, an Si0₂ film, an organic SOG film and an organic resist film.

6. The manufacturing method of a stencil mask as claimed in claim 1 or 2 , wherein said filling material is selected from a group consisting of aluminum and solder.

7. The manufacturing method of a stencil mask as claimed in claim 3 , wherein when said filling material is an Si02 film, said fourth removing step is carried out by wet-etching using hydrofluoric acid (HF) or a mixture of hydrofluoric acid (HF) and ammonium fluoride (NH₄F) .

8. A stencil mask blank formed of a silicon-on- insulator substrate having a silicon base layer, an embedded oxide film provided to said silicon base layer and an SOI layer provided to said oxide film, said stencil mask blank comprising: a filling material filled in a cavity part which is defined by said SOI layer and sidewalls of said embedded oxide film and said silicon base layer by removing said silicon base layer and said embedded oxide film so as to expose said embedded oxide film.

9. The stencil mask blank as claimed in claim 8 , wherein said filing material is filled by one of a spin coat method and a chemical vapor deposition method.

10. The stencil mask blank as claimed in claim 8, wherein said filling material is selected from a group consisting of an SOG film, an Si0₂ film, an organic SOG film and an organic resist film.

11. The stencil mask blank as claimed in claim 8 , wherein said filling material is selected from a group consisting of aluminum and solder.

12. The stencil mask blank as claimed in claim 8 , wherein a stencil mask is formed by removing said filling material.

13. A manufacturing method of a membrane mask using a substrate having a silicon substrate and first and second silicon nitride films formed on said silicon substrate, the manufacturing method comprising: a first forming step of forming a first resist film on said first silicon nitride film, the first resist film having a desired resist pattern; a first removing step of removing said first silicon nitride film by using said first resist film as a mask so as to cause said silicon substrate to be exposed; a first exfoliating step of exfoliating said first resist film; a second forming step of sequentially forming a first Cr film, a W film and a second Cr film on said second^' silicon nitride film; a second removing step of removing said silicon substrate by using said first silicon nitride film as a mask so as to expose said second silicon nitride film and form a cavity part which is defined by the exposed second silicon nitride film, sidewalls of said first silicon nitride film and sidewalls of said silicon substrate; a second exfoliating step of exfoliating said first Cr film; and a filling step of filling a filling material in said cavity part.

14. The manufacturing method of a membrane mask as claimed in claim 13, further comprising: a third forming step of forming a second resist film on said W film, the second resist film having a predetermined pattern; a third removing step of removing said W film and said second Cr film by using said second resist film as a mask; a third exfoliating step of exfoliating said second resist film; and a fourth removing' step of removing said filling material .

15. The manufacturing method of a membrane mask as claimed in claim 13, wherein said filling step is carried out by one of a spin coat method and a chemical vapor deposition method.

16. The manufacturing method of a membrane mask as claimed in claim 13 , wherein said filling material is selected from a group consisting of an SOG film, an Si0₂ film, an organic SOG film and an organic resist film.

17. The manufacturing method of a membrane mask as claimed in claim 13 , wherein said filling material is selected from a group consisting of aluminum and solder.

18. The manufacturing method of a membrane mask as claimed in claim 13 , wherein when said filling material is an Si0₂ film, said fourth removing step is carried out by wet-etching using hydrofluoric acid (HF) or a mixture of hydrofluoric acid (HF) and ammonium fluoride (NH₄F) .

19. A membrane mask blank formed of a substrate having a silicon substrate and first and second silicon nitride films provided to said silicon substrate; said membrane mask blank comprising: a filling material filled in a cavity part defined by said first silicon nitride film and sidewalls of said second silicon nitride films and said silicon substrate by removing said second silicon nitride film and said silicon substrate so as to expose said first silicon nitride film.

20. The membrane mask blank as claimed in claim

19, wherein said filing material is filled by one of a spin coat method and a chemical vapor deposition method.

21. The membrane mask blank as claimed in claim 19, wherein said filling material is selected from a group consisting of an SOG film, an Si0₂ film, an organic SOG film and an organic resist film.

22. The membrane mask blank as claimed in claim 19, wherein said filling material is selected from a group consisting of aluminum and solder.

23. The membrane mask blank as claimed in claim 19, wherein a membrane mask is formed by removing said filling material.