JP4649780B2 - Stencil mask, manufacturing method thereof and exposure method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a stencil mask used for exposure of charged particle beams such as an electron beam and an ion beam, a manufacturing method thereof, and an exposure method.
[0002]
[Prior art]
In recent years, miniaturization of semiconductor elements has been progressing rapidly. Various exposure techniques have been developed as a technique for manufacturing an element having such a fine pattern. For example, there are exposure methods using electron beams such as partial exposure of electron beams and electron stepper exposure, exposure methods using ions, exposure methods using light in the vacuum ultraviolet region, exposure methods using light in the extreme ultraviolet region, etc. .
[0003]
Among these, as an exposure method using an electron beam, a method of performing equal magnification exposure using an electron beam is proposed in Japanese Patent No. 2951947. This method has a feature that the acceleration voltage of an electron beam is 1/20 as compared with a conventional exposure method using an electron beam.
[0004]
In the stencil mask used for the same magnification exposure, the processing accuracy of the mask pattern is important. In particular, the aspect ratio, which is the ratio between the mask film thickness and the mask pattern line width (electron beam transmission hole diameter), is a problem. The mask pattern is processed by dry etching, but the aspect ratio is usually about 10. Therefore, for example, in order to form a pattern with a line width of 100 nm, the thickness of the mask is limited to about 1 μm.
[0005]
Therefore, the above-mentioned Japanese Patent No. 2951947 discloses that a stencil mask made of single crystal silicon has a thickness of 0.2 μm to 1.0 μm. However, this patent publication does not describe any method for manufacturing such a stencil mask made of single crystal silicon.
[0006]
Usually, when single crystal silicon is used as the material of the thin film constituting the stencil mask, a substrate is required to support the thin film and maintain the flatness of the mask. As this substrate, single crystal silicon is used from the viewpoint of processability and availability. Then, in order to perform microfabrication of the thin film by etching, an SOI (Silicon On Insulator) substrate having a structure in which a silicon oxide film is sandwiched between two single crystal silicon substrates is used, and the mask pattern is obtained by polishing one single crystal silicon substrate. Thus, the film thickness is made to a predetermined thickness and then patterned. At this time, the silicon oxide film that is an intermediate layer of the SOI substrate functions as an etching stopper when the mask pattern is processed.
[0007]
However, with such a method, it is extremely difficult to polish the single crystal silicon substrate to the above-mentioned thin film of 0.2 μm to 1.0 μm. Further, with such a film thickness, there is a problem that a thin single crystal silicon substrate is cracked by the stress of the silicon oxide film in the manufacturing process of the stencil mask.
[0008]
For this reason, a stress adjustment process is required for the single crystal silicon thin film formed on the silicon oxide film. In such a case, however, the manufacturing process is increased, resulting in a problem that the tact time is increased.
[0009]
[Problems to be solved by the invention]
An object of the present invention is to provide a stencil mask which is made under such circumstances, can be easily formed into a thin film, can perform stress control, and has excellent electron beam irradiation characteristics.
[0010]
It is another object of the present invention to provide a method for manufacturing such a stencil mask.
[0011]
Still another object of the present invention is to provide a charged particle beam exposure method using such a stencil mask.
[0012]
[Means for Solving the Problems]
In order to solve the above-mentioned problems, the present invention comprises a base and a mask base supported by the base, and the mask base has a transmission hole pattern through which a charged particle beam passes, and has a thickness of 0.1 μm or more. A stencil mask comprising an amorphous silicon thin film having a thickness of 5 μm or less, wherein the amorphous silicon thin film is an amorphous silicon carbide film or an amorphous silicon sulfide film is provided.
[0013]
According to the present invention, since the mask base is composed of a non-single crystal silicon thin film, it can be easily formed by CVD or the like, has excellent workability, and forms a pattern with a desired aspect ratio with high accuracy. Therefore, it is possible to obtain a stencil mask that is easy to design and control the process and has excellent charged particle beam irradiation characteristics.
[0014]
In the stencil mask of the present invention, the non-single crystal silicon-based thin film has a thickness of 0.1 μm or more and 5 μm or less . A film thickness in this range can be easily obtained by CVD or the like.
[0017]
Further, the non-single crystal silicon thin film is an amorphous silicon carbide film or an amorphous silicon sulfide film.
By using these thin films, a wider range of stresses can be controlled, and the stress acting on the thin films can be further reduced. That is, although a compressive stress or a tensile stress acts on the thin film in relation to the base on which the thin film is formed, it is possible to control the stress and relieve the stress.
[0019]
Furthermore, the non-single-crystal silicon-based thin film is selected from the group consisting of an amorphous silicon thin film , a hydrogenated amorphous silicon thin film, an amorphous silicon carbide film, an amorphous silicon nitride film, and an amorphous silicon sulfide film. Two or more kinds of laminated films selected from the group consisting of a selected thin film and a silicon nitride film can be obtained.
[0020]
By using these thin films, a wider range of stresses can be controlled, and the stress acting on the thin films can be further reduced.
[0022]
Further, the present invention has, on a substrate, silane or disilane, and methane, ethylene or acetylene, or a raw material gas containing hydrogen sulphide, by plasma CVD using a dilution gas comprising hydrogen, the amorphous silicon carbide film or non Provided is a method for producing a stencil mask comprising a step of forming a thin film which is a crystalline silicon sulfide film , and a step of patterning the thin film.
[0026]
According to this manufacturing method , it is possible to easily obtain a stencil mask having excellent charged particle beam irradiation characteristics with high accuracy without causing cracks and peeling due to stress.
[0027]
Furthermore, the present invention provides a charged particle beam exposure method comprising a step of irradiating the above stencil mask with a charged particle beam and shaping the charged particle beam into the shape of a transfer pattern.
According to such an exposure method, it is possible to perform pattern exposure with high accuracy on the resist formed on the sample substrate. As a result, it is possible to manufacture a pattern of a semiconductor or the like with a high yield.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a stencil mask according to one embodiment of the present invention will be described with reference to the drawings.
[0029]
FIG. 1 is a cross-sectional view illustrating a stencil mask according to one embodiment of the present invention. In FIG. 1, a stencil mask 1 has a mask base 4 made of a non-single crystal silicon-based thin film having a predetermined transmission hole pattern on a single crystal silicon wafer 2 having an opening formed through a silicon oxide film 3. It is comprised by forming.
[0030]
For the supporting substrate, a semiconductor material such as gallium-arsenic or indium-phosphorus can be used in addition to single crystal silicon.
[0031]
The silicon oxide film 3 functions as an etching stopper when forming the mask matrix. However, instead of the silicon oxide film, a metal such as chromium, tungsten, tantalum, titanium, nickel, aluminum, an alloy containing these metals, or these metals can be used as long as the etching selectivity with the mask base material can be taken. A metal compound of metal or alloy and oxygen, nitrogen, carbon, or the like, or a film containing carbon as a main component can be preferably used.
[0032]
Examples of the non-single crystal silicon thin film constituting the mask base 4 include an amorphous silicon thin film, a polycrystalline silicon thin film, an amorphous silicon carbide film, an amorphous silicon nitride film, and an amorphous silicon sulfide film.
[0033]
The non-single-crystal silicon thin film is a hydrogenated non-single-crystal silicon thin film and may contain boron or phosphorus. By containing these impurities, the resistance of the thin film can be reduced.
[0034]
The film thickness of the non-single crystal silicon thin film is preferably 0.1 μm or more and 5 μm or less. If the film thickness is too thin, the non-single-crystal silicon thin film 4 may be dissolved if the current value is increased to increase the throughput. If it is too thick, the mask pattern processing accuracy can be increased. Absent.
[0035]
In the stencil mask according to the present embodiment configured as described above, a non-single-crystal silicon thin film is used as the mask matrix instead of the conventionally used single-crystal silicon thin film. Therefore, it is possible to form a thin film with a small film thickness, so that a pattern with a desired aspect ratio can be formed with high accuracy.
[0036]
Next, the manufacturing process of the stencil mask described above will be described with reference to FIGS.
[0037]
First, as shown in FIG. 2, a silicon oxide film 12 is formed on a single crystal silicon substrate 11 by thermal oxidation or CVD. Next, a non-single-crystal silicon thin film, for example, an amorphous silicon thin film 13 is formed on the silicon oxide film 12 by a CVD method.
[0038]
Next, as shown in FIG. 3, the amorphous silicon thin film 13 is patterned to form a mask base 14 having a predetermined transmission hole pattern. This perforation pattern forming process includes a step of forming a resist pattern on the amorphous silicon thin film 13, a step of dry etching the amorphous silicon thin film 13 using the resist pattern as a mask, and a step of peeling the resist pattern. It goes through in order.
[0039]
As the exposure for forming the resist pattern, electron beam direct drawing using an electron beam resist, stepper exposure using a photoresist, or the like can be suitably used.
[0040]
Further, when the amorphous silicon thin film 13 is dry-etched, if the resist has insufficient etching resistance, an inorganic compound such as a silicon oxide film, a silicon nitride film, or a silicon carbide film, chromium, tungsten, tantalum, or titanium Metals such as nickel and aluminum, alloys containing these metals, or metal compounds of these metals or alloys and oxygen, nitrogen, carbon, or the like can be appropriately selected and used as an etching mask. These etching masks can be formed by various thin film forming methods. For example, there are forming methods such as sputtering, CVD, and vapor deposition.
[0041]
For dry etching, the dry etching method and etching conditions are not particularly limited. Examples of the gas used for etching include a mixed gas mainly containing a fluorine-based gas such as SF ₆ gas and CF ₄ gas, a mixed gas mainly containing a chlorine-based gas such as Cl ₂ gas and SiCl ₄ gas, and a bromine such as HBr gas. Examples thereof include a mixed gas mainly composed of a system gas. Examples of the dry etching apparatus include a dry etching apparatus using a discharge method such as RIE, magnetron RIE, ECR, ICP, microwave, helicon wave, and NLD.
[0042]
Thereafter, an opening 15 is formed in the single crystal silicon substrate 11 as shown in FIG. In this step, dry etching, wet etching, ultrasonic processing, sandblasting, or the like can be suitably used. Note that either the patterning step of the amorphous silicon thin film 13 or the step of forming the opening in the single crystal silicon substrate 11 may be performed first.
[0043]
Finally, the silicon oxide film in the opening is removed with hydrofluoric acid or the like, and the stencil mask is completed as shown in FIG.
[0044]
As described above, the opening in the single crystal silicon substrate 11 can be formed before the patterning of the amorphous silicon thin film 13. At this time, the silicon oxide film exposed in the opening of the single crystal silicon substrate 11 can be removed before the patterning of the amorphous silicon thin film 13. In such a process, when the amorphous silicon thin film 13 is patterned, since there is no silicon oxide film in the portion, the stencil mask is cracked or destroyed by the stress generated in the silicon oxide film. There is nothing to do.
[0045]
【Example】
Hereinafter, specific embodiments of the present invention will be described in detail with reference to the drawings.
[0046]
Example 1
With reference to FIGS. 2-4, the manufacturing process of the stencil mask which concerns on one Example of this invention is demonstrated.
A silicon oxide film 12 having a thickness of 1 μm was formed on the single crystal silicon substrate 11 having a thickness of 525 μm by thermal oxidation. Next, a hydrogenated amorphous silicon film 13 doped with boron or phosphorus was formed on the silicon oxide film 12 by plasma CVD.
[0047]
The conditions for plasma CVD are as follows.
Source gas: SiH ₄ 30 sccm
Dilution gas: H ₂ 270-560 sccm
Dope gas: B ₂ H ₆ 500 ppm to 1%
Or _PH 3 _500ppm~1%
Reaction pressure: 0.5 to 1.5 Torr
High frequency power: 60W
Film thickness: 500 nm.
[0048]
An electron beam resist (not shown) is applied to the boron or phosphorus-doped hydrogenated amorphous silicon film 13 formed as described above to a thickness of 0.5 μm, and electron beam drawing with an acceleration voltage of 20 kV is applied thereto. Drawing was performed using a machine, and then development was performed using a dedicated alkali developer to form a resist pattern.
[0049]
Next, using the resist pattern as a mask, using a plasma etching apparatus and using SF ₆ as an etchant, the hydrogenated amorphous silicon film 13 is dry-etched to a depth reaching the silicon oxide film 12, and FIG. As shown in FIG.
[0050]
Next, the resist pattern is peeled off, a protective film (not shown) made of a silicon nitride film is formed on the entire surface using a plasma CVD (Chemical Vapor Deposition) apparatus, and then the opening of the single crystal silicon substrate 11 is formed by dry etching. The protective film on the part formation region was removed.
[0051]
Next, it is stored in an etching solution of a KOH aqueous solution heated to about 90 ° C., and the single crystal silicon substrate 11 is anisotropically oriented along the plane direction up to the silicon oxide film 12 serving as an etching stopper, using the protective film as a mask. Etching was performed to form openings. Next, after the protective film was removed by etching with hot phosphoric acid at about 170 ° C., the exposed portion of the silicon oxide film 12 was removed by etching with hydrofluoric acid to complete a stencil mask as shown in FIG.
[0052]
In the stencil mask manufactured as described above, the hydrogenated amorphous silicon film 13 has a very thin film thickness of 500 nm and has low stress, so that peeling and cracking do not occur and resistance is low. There is no need to provide a separate metal film. Further, the obtained stencil mask had high pattern accuracy and excellent charged particle beam irradiation characteristics.
[0053]
Example 2
A stencil mask was manufactured in the same manner as in Example 1 except that a hydrogenated amorphous silicon carbide film doped with boron or phosphorus was formed by plasma CVD under the following conditions.
[0054]
Source gas: CH ₄ 30sccm
Dilution gas: H ₂ 270sccm
Dope gas: B ₂ H ₆ 500 ppm to 1%
Or _PH 3 _500ppm~1%
Reaction pressure: 0.5 to 1.5 Torr
High frequency power: 60W
Film thickness: 500 nm.
[0055]
Also in this example, the same effect as in Example 1 was obtained.
[0056]
Example 3
A stencil mask was manufactured in the same manner as in Example 1 except that a hydrogenated amorphous silicon nitride film doped with boron or phosphorus was formed by plasma CVD under the following conditions.
[0057]
The raw material _gas: NH 3 _1~30sccm
Dilution gas: H ₂ 270sccm
Dope gas: B ₂ H ₆ 500 ppm to 1%
Or _PH 3 _500ppm~1%
Reaction pressure: 0.5 to 1.5 Torr
High frequency power: 60W
Film thickness: 500 nm.
[0058]
Also in this example, the same effect as in Example 1 was obtained.
[0059]
Example 4
A stencil mask was manufactured in the same manner as in Example 1 except that a hydrogenated amorphous silicon sulfide film doped with boron or phosphorus was formed by plasma CVD under the following conditions.
[0060]
The raw material _gas: H 2 S _1~30sccm
Dilution gas: H ₂ 270sccm
Dope gas: B ₂ H ₆ 500 ppm to 1%
Or _PH 3 _500ppm~1%
Reaction pressure: 0.5 to 1.5 Torr
High frequency power: 60W
Film thickness: 500 nm.
[0061]
Also in this example, the same effect as in Example 1 was obtained.
[0062]
Example 5
A stencil mask was manufactured in the same manner as in Example 1 except that an amorphous silicon film was formed by sputtering under the following conditions.
[0063]
Sputter target: Undoped single crystal silicon 99.999%
Sputtering gas: Argon 33sccm
Reaction pressure: 0.7 Pa
High frequency power: 300W
Film thickness: 500 nm.
[0064]
Also in this example, the same effect as in Example 1 was obtained.
[0065]
Example 6
A stencil mask was manufactured in the same manner as in Example 1 except that an amorphous silicon carbide film was formed by sputtering under the following conditions.
[0066]
Sputter target: Undoped single crystal silicon 99.999%
Sputtering gas: Argon 33sccm
Additive gas: Methane 1-33sccm
Reaction pressure: 0.7 Pa
High frequency power: 300W
Film thickness: 500 nm.
[0067]
Also in this example, the same effect as in Example 1 was obtained.
[0068]
Example 7
A stencil mask was manufactured in the same manner as in Example 1 except that an amorphous silicon nitride film was formed by sputtering under the following conditions.
[0069]
Sputter target: Undoped single crystal silicon 99.999%
Sputtering gas: Argon 33sccm
Addition gas: Nitrogen 1-33sccm
Reaction pressure: 0.7 Pa
High frequency power: 300W
Film thickness: 500 nm.
[0070]
Also in this example, the same effect as in Example 1 was obtained.
[0071]
Example 8
A stencil mask was manufactured in the same manner as in Example 1 except that a silicon nitride film was formed by LPCVD under the following conditions.
[0072]
Source gas: SiH ₂ Cl ₂ + NH ₃ (10-50 sccm)
Reaction pressure: 30-60 Pa
Film thickness: 500 nm.
[0073]
Also in this example, the same effect as in Example 1 was obtained.
[0074]
【The invention's effect】
As described above in detail, according to the present invention, since the mask base is composed of a non-single crystal silicon thin film, it can be easily formed by CVD or the like, and the design and control of the processing process is easy. Thus, a stencil mask having excellent processability, a pattern having a desired aspect ratio can be formed with high accuracy, and excellent charged particle beam irradiation characteristics can be obtained.
[0075]
Moreover, according to the manufacturing method of the present invention, it is possible to easily obtain a stencil mask having excellent charged particle beam irradiation characteristics with high accuracy without causing cracks and peeling due to stress.
[0076]
Furthermore, according to the exposure method of the present invention, it is possible to perform pattern exposure with high accuracy on the resist formed on the sample substrate. As a result, it is possible to manufacture a pattern of a semiconductor or the like with a high yield.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating a stencil mask according to one embodiment of the present invention.
FIG. 2 is a cross-sectional view illustrating a manufacturing process of a stencil mask according to one embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating a manufacturing process of a stencil mask according to one embodiment of the present invention.
FIG. 4 is a cross-sectional view illustrating a manufacturing process of a stencil mask according to one embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Stencil mask 2, 11 ... Single crystal silicon substrate 3, 12 ... Silicon oxide film 4, 14 ... Mask mother body 13 ... Amorphous silicon thin film 15 ... Opening

Claims (3)

An amorphous silicon thin film having a base and a mask base supported by the base, the mask base having a transmission hole pattern through which a charged particle beam passes and having a thickness of 0.1 μm or more and 5 μm or less The stencil mask , wherein the amorphous silicon thin film is an amorphous silicon carbide film or an amorphous silicon sulfide film . On a substrate, silane or disilane, and methane, ethylene or acetylene, or a raw material gas containing hydrogen sulphide, by plasma CVD using a diluent gas consisting of hydrogen, an amorphous silicon carbide film or an amorphous silicon sulfide film, A method for producing a stencil mask, comprising: forming a thin film; and patterning the thin film. A charged particle beam exposure method comprising a step of irradiating the stencil mask according to claim 1 with a charged particle beam and shaping the charged particle beam into a shape of a transfer pattern.

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