JP4729875B2 - Stencil mask and pattern transfer method - Google Patents

Description

  The present invention relates to a stencil mask used for charged particle beam exposure such as an electron beam or an ion beam, a manufacturing method thereof, and a pattern transfer method thereof.

  In recent years, miniaturization of semiconductor elements has been progressing rapidly. Various exposure techniques have been developed as manufacturing techniques for elements having such fine patterns. For example, there are exposure methods using electron beams such as partial exposure of electron beams and electron stepper exposure, exposure methods using ions, exposure methods using light in the vacuum ultraviolet region, exposure methods using light in the extreme ultraviolet region, etc. .

  Among these, as one of exposure methods using an electron beam, a method of reducing exposure using an electron beam stepper has been proposed (for example, see Non-Patent Document 1). In this method, high-speed electrons accelerated by an accelerating voltage of about 20 to 100 kV are usually reduced and exposed to 1/4 using an electron beam mask and an electron lens to form a desired pattern such as a semiconductor circuit. As an electron beam mask used here, a membrane mask and a stencil mask have been proposed.

  The membrane mask is composed of a thin film made of a light element that easily transmits an electron beam (hereinafter referred to as a membrane thin film) and a scattering layer pattern formed thereon and made of a heavy metal that easily scatters an electron beam. For example, a silicon nitride film is used as the membrane thin film material, and a tungsten thin film is used as the scattering layer material.

  In the membrane mask, since the membrane thin film is interposed in the electron beam exposure portion, the ratio of non-scattered electrons is small even if a light element is used as the material of the membrane thin film and the film thickness is reduced. Furthermore, most of the electrons whose angles are changed by elastic scattering are cut by the limiting aperture, so that the loss of the beam current is large. In addition, electrons that transmit through the limiting aperture and contribute to exposure partly lose energy due to inelastic scattering such as plasmon excitation. As a result, the energy dispersion of exposure electrons increases, that is, the resolution decreases due to chromatic aberration. In order to reduce this chromatic aberration, it is effective to reduce the convergence angle, but on the other hand, the Coulomb effect is increased and the beam current is also limited.

  On the other hand, the stencil mask does not have a membrane thin film, and a through-hole is provided in the exposed portion. As the scattering layer, single crystal silicon is usually used, and its thickness is usually about 2 μm.

  In such a stencil mask, a through-hole through which an electron beam can pass is provided in the mask itself, and exposure electrons can freely pass through the opening, so that there is no energy loss of the electron beam. Therefore, compared with the membrane mask, there is no reduction in resolution due to chromatic aberration.

  However, since the portion through which the electron beam passes completely penetrates, if the opening pattern is closed, the mask member inside thereof is lost. In order to avoid this, it is necessary to divide the pattern into two or more complementary masks. For example, in the case of a donut-shaped pattern, the pattern can be completed on the wafer by dividing it into two semicircles, dividing it into complementary masks, placing them on the complementary masks, and exposing twice.

  Moreover, it is necessary to divide the mask member even for a pattern having a problem in mechanical strength such as a large mask member supported by a small support portion. As described above, in the stencil mask, the number of exposures is doubled by dividing the mask, so that throughput is sacrificed.

Recently, LEEPL (Low energy electron-beam proximity), which uses a stencil mask and carries out equal magnification exposure using a low energy electron beam
The projection lithography method is disclosed in Patent Document 1. This method has a feature that the acceleration voltage of the electron beam is as low as 2 kV, that is, a low-energy electron beam is used, compared to the conventional exposure method using an electron beam. In such a method, since the lens system and the beam current are small, it is not affected by the proximity effect, and the Coulomb effect is also small, so that the resolution is hardly lowered. In addition, the exposure apparatus using such a low energy electron beam has a feature that the apparatus cost is low and a high-throughput semiconductor exposure apparatus can be realized.

  In LEEPL, a stencil mask in which transmission holes are formed for pattern formation is used. A small gap of about 40 μm is maintained between the stencil mask and the wafer to be transferred, and the electron beam is exposed by proximity transfer that does not have the influence of the Coulomb effect. Since the stencil mask needs to be close to the wafer, in LEEPL, the electron beam is exposed from the mask substrate side. In a stencil mask used for LEEPL, the mask pattern processing accuracy is particularly important. In particular, the aspect ratio, which is the ratio between the mask film thickness and the mask pattern line width (electron beam transmission hole diameter), is a problem. The mask pattern is processed by dry etching, but the aspect ratio is usually about 10. Therefore, for example, in order to form a pattern with a line width of 100 nm, the thickness of the mask is limited to about 1 μm.

  Therefore, Patent Document 1 described above discloses that a stencil mask made of single crystal silicon has a thickness of 0.2 μm to 1.0 μm. However, this patent publication does not describe any method for manufacturing such a stencil mask made of single crystal silicon.

  Usually, when single crystal silicon is used as the material of the thin film constituting the stencil mask, a substrate is required to support the thin film and maintain the flatness of the mask. As this substrate, single crystal silicon is used from the viewpoint of processability and availability. As the mask blank, an SOI (Silicon On Insulator) substrate having a structure in which a silicon oxide film is sandwiched between two single crystal silicon substrates, which is suitable for performing fine processing of a thin film by etching, is used. At this time, the silicon oxide film which is an intermediate layer of the SOI substrate functions as an etching stopper layer when the mask pattern is processed.

  However, with such a method, it is extremely difficult to polish the single crystal silicon substrate to the above-mentioned thin film of 0.2 μm to 1.0 μm. Further, with such a film thickness, there is a problem that in the manufacturing process of the stencil mask, the thin single crystal silicon substrate is cracked due to the strong compressive stress of the silicon oxide film that is the intermediate layer.

  For this reason, a stress adjustment process is required for the single crystal silicon thin film formed on the silicon oxide film, but in such a case, a manufacturing process such as ion doping increases, which causes a problem that the tact time becomes long. .

  Further, as described above, in LEEPL, an electron beam is necessarily exposed from the substrate side in order to bring the mask and wafer close to each other during exposure. When an SOI substrate is used as a stencil mask blank as in the prior art, a silicon thin film irradiated with an electron beam and a substrate are electrically insulated via an intermediate oxide film. For this reason, charge-up on the mask matrix is a big problem.

  Next, a general method for manufacturing the conventional stencil mask as described above will be described with reference to FIGS.

  First, an electron beam resist is applied on the silicon thin film on the surface of the SOI substrate 5A as shown in FIG. 5A, that is, the SOI layer 53 ′, and patterned by electron beam lithography to form a mask base 53 (FIG. 5 ( b)).

  Next, as shown in FIG. 5C, the base silicon layer, that is, the silicon support substrate 51 ′ is processed by photolithography to form the base body 51. At this time, wet etching using an alkaline aqueous solution such as potassium hydroxide or dry etching using an etching gas mainly containing a halogen-based source gas such as fluorine or chlorine is used for the etching. Subsequently, after the intermediate oxide film 52 of the SOI substrate 5A is peeled off to produce an intermediate oxide film remaining layer 52 ', a stencil mask is completed (FIG. 5D).

  According to such a conventional manufacturing method, the SOI substrate used has a structure in which the single crystal silicon substrate and the single crystal silicon thin film have an intermediate oxide film that has a strong compressive stress and cannot be stress-adjusted. For this reason, after processing the silicon layer of the thin film that becomes the mask base first, the silicon substrate is processed to obtain the base. A decrease in accuracy is inevitable.

  Next, another example of the conventional method for manufacturing a stencil mask as described above will be described with reference to FIGS.

  First, the base silicon layer, that is, the silicon support substrate 61 ′ of the SOI substrate 6 </ b> A as shown in FIG. 6A is processed by photolithography to form the base body 61. (FIG. 6B) At this time, when the substrate 61 'is etched, the intermediate oxide film 62 is used as an etching stopper layer. For the etching, wet etching using an alkaline aqueous solution such as potassium hydroxide, or dry etching using an etching gas mainly containing a halogen-based source gas such as fluorine or chlorine is used.

  Next, as shown in FIG. 6C, the intermediate oxide film 62 of the SOI substrate 6A is peeled off to form an intermediate oxide film remaining layer 62 ′, and then an electron beam resist is formed on the silicon thin film on the surface, that is, the SOI layer 63 ′. Is applied and patterned by electron beam lithography to form a mask base 63 having a mask pattern, thereby completing a stencil mask (FIG. 6D).

  According to such a conventional manufacturing method, in order to improve the pattern position accuracy of the stencil mask, the back side silicon support substrate is first etched to form a membrane (hereinafter referred to as a thin film layer), and then mask processing is performed. However, because the mask pattern is formed in the thin film layer state, the process in the thin film layer state is long. It becomes indispensable and a decrease in yield is inevitable. The membrane used here (hereinafter referred to as a thin film layer) refers to the SOI layer 63 '.

The known literature is described below.
S. D. Berger et. al. , Applied Physics Letters, 57, 153 (1990). Japanese Patent No. 2951947

  The present invention has been made under such circumstances, and is suitable for obtaining a stencil mask for electron beam exposure having excellent electron beam irradiation resistance, as well as being capable of thinning and stress adjustment, and a simple manufacturing process. An object of the present invention is to provide a stencil mask with high yield and high pattern position accuracy, a manufacturing method thereof, and an exposure method thereof.

The invention according to claim 1 of the present invention includes a substrate,
It is supported by the base, and the mask matrix having a transmission hole pattern, on at least a portion of the base side of the mask matrix, and a mask matrix underlayer, the mask matrix is a metal, silicon, or oxide thereof, nitride The mask base layer is a diamond film containing sulfur or a diamond-like carbon film containing sulfur, and the mask base layer is formed only on the base portion. It is the stencil mask characterized by being.

  According to such an invention, since the conductive film, ie, the mask base layer is interposed at the interface between the base and the mask base, the electron beam is irradiated from the base when the mask base is conductive. Even in this case, electrons can flow to the substrate through the mask base layer, so that no charge-up occurs.

  Furthermore, when there is a conductive mask base underlayer over the entire base of the mask base, even when the mask base does not have conductivity, electrons escape to the base through the mask base base, Does not charge up.

The diamond film is a single crystal, polycrystal or nanocrystal film composed of chemical bonds mainly composed of sp ³ hybrid orbitals of carbon atoms. On the other hand, the diamond-like carbon film is mainly composed of sp ³ hybrid orbitals of carbon atoms, but the structure is amorphous. However, it is a film characterized by exhibiting various physical properties comparable to a diamond film. Therefore, since these diamond films and diamond-like carbon films have unparalleled high hardness, Young's modulus, and thermal conductivity, they are excellent in mechanical and thermal properties in the state of a thin film layer. As a result, it is possible to reinforce the characteristics of the mask base material and improve the mechanical characteristics and thermal characteristics.

  By such impurity doping, the diamond thin film exhibits impurity conductivity or hopping conductivity due to defects, and can impart conductivity. That is, when applied as a stencil mask, charge-up due to electron beam irradiation can be avoided.

  The invention according to claim 2 of the present invention further comprises an etching stopper layer exhibiting halogen-based plasma resistance between the substrate and the mask base layer. It is a mask.

  According to such an invention, by interposing an etching stopper layer that functions as a stopper when etching the substrate between the base and the mask base underlayer, the stopper characteristics as a material for the mask base underlayer are: It becomes unnecessary and a wider range of materials can be used.

  According to such an invention, in order to process a mask base material layer directly on a substrate, that is, to form a mask pattern for forming a mask base, compared with the case of forming on a conventional membrane thin film, in the resist coating process It is possible to form a mask pattern with a high yield in the same manner as in a normal resist process, without causing a membrane (hereinafter referred to as a thin film layer) to be destroyed during handling or stress after resist application. The mask base layer can be used as a mask for forming the mask base and as an etching stopper layer for forming the base.

  By producing the mask base material layer by physical vapor deposition or chemical vapor deposition, a desired low-stress film can be easily obtained by controlling the deposition conditions.

  According to such an invention, since the mask base layer made of an inorganic material is formed directly on the substrate by vapor deposition, the mask base layer is formed by forming an etching mask for mask base formation, that is, a hard mask. In addition, it has high conductivity made of various metals and compounds thereof, and a high etching selectivity can be obtained with a thin film thickness.

  As described above, by providing the etching stopper layer, it can be used for a wide range of the mask base layer and the mask base regardless of the etching stop function at the time of substrate formation, and the controllability of etching can be improved. .

  In such an invention, as a material for the mask base layer, metal, silicon, carbon film, amorphous carbon film, diamond film, diamond-like carbon film, or metal, silicon oxide, nitride, You can choose from a wide range of materials such as carbides.

  As described above, according to the present invention, by forming the mask base layer, it is easy to reduce the thickness and adjust the stress, prevent charge-up, and have high mechanical strength and thermal conductivity. That is, the stencil mask for electron beam exposure excellent in electron beam irradiation tolerance can be provided.

  Furthermore, the present invention can improve the resist coating property, etching accuracy and reproducibility at the time of patterning when forming the mask base layer, and has higher definition, higher accuracy, higher yield and lower cost. Making possible.

  Further, a resist made of an organic material such as a photoresist or an electron beam resist is applied as a mask base layer by spin coating, etc., and after patterning, a conductive carbonized film is formed by baking in a vacuum or an inert atmosphere. Thus, it is possible to use a vacuum or a high temperature process in the production of the mask base material layer.

  Furthermore, by using a resist made of an organic material in this way, it is easy to apply and pattern on a substrate, and a stencil mask can be formed by a simple process without the need to newly provide a hard mask (etching mask) or etching stopper layer. It can be manufactured.

  By fabricating the mask base material layer and the mask base material phase by physical vapor deposition or chemical vapor deposition, the desired low-stress film can be easily obtained by controlling the respective deposition conditions. Can do.

  The invention according to claim 3 of the present invention is a pattern transfer characterized by irradiating the stencil mask according to claim 1 or 2 with a charged particle beam to shape the charged particle beam into the shape of the transfer pattern. Is the method.

  According to such an exposure method, it is possible to transfer a pattern with high accuracy to a resist formed on a semiconductor device substrate. As a result, a pattern for a semiconductor device can be manufactured with high accuracy and high yield. .

  In the stencil mask of the present invention, since a conductive mask base layer is provided at the interface between the base and the mask base, a highly resistant mask can be obtained without charging up even with electron beam irradiation.

  In the stencil mask of the present invention, the conductive mask base underlayer is formed of any one of a carbon film, an amorphous carbon film, a diamond film, and a diamond-like carbon film at the interface between the base and the mask base. A thin film can be formed with high controllability by the phase growth method, and stress adjustment by film thickness control and particle size control can be easily performed. Furthermore, especially when a diamond film or diamond-like carbon film is used as the mask base material layer, high hardness, high Young's modulus, and high thermal conductivity can be obtained, so that the mask pattern can be easily miniaturized and the pattern design is free. The degree can be increased.

In the method for manufacturing a stencil mask of the present invention, a mask base layer serving as a hard etching mask is first formed on a substrate, and the mask base is processed by etching from the substrate surface. Therefore, a resist pattern is formed on the thin film layer. Since it does not need to be formed, conventional electron beam lithography can be applied, the mask base processing process is facilitated, and a decrease in yield due to the destruction of the thin film layer in the manufacturing process can be prevented. Furthermore, even when a high-quality polycrystalline diamond film is used as the mask base, high-precision processing is possible regardless of the surface irregularities.

  Therefore, according to the manufacturing method of the present invention, it is possible to obtain a stencil mask excellent in charged particle beam irradiation characteristics with high accuracy, without cracking and peeling due to stress, easily and at a high yield. is there.

  Furthermore, according to the exposure method of the present invention, it is possible to perform pattern exposure with high accuracy on a resist formed on a substrate for a semiconductor device, and as a result, it is possible to manufacture a pattern for a semiconductor device with a high yield. .

  Embodiments according to one embodiment of the present invention are described below with reference to the drawings.

  1A and 1B are side cross-sectional views illustrating a stencil mask according to one embodiment of the present invention.

  In FIG. 1A, a stencil mask includes a base 11, a mask base underlayer 12 a on the base 11, and a mask base 13 having a transmission hole pattern through which a charged particle beam passes on the mask base underlayer 12 a. It is made up of.

  As a substrate serving as a base, in addition to single crystal silicon, a semiconductor substrate such as GaAs, a metal substrate, a quartz substrate, a ceramic substrate, or a glass substrate can be used.

  The mask base layer 12a is present at the interface between the base 11 and the mask base 13, and is composed of a carbon film, an amorphous carbon film, a diamond film, a diamond-like carbon film, or a film made of metal, silicon, and a compound thereof. can do. These films are preferably conductive from the viewpoint of preventing charge-up.

  The mask base layer 12a can be formed of a thin film material that can be formed by applying a resist made of an organic material and baking it, or by depositing an inorganic material by a method such as sputtering, chemical vapor deposition, or ion plating. .

  Here, as the material of the mask base layer 12a, any one or two or more of carbon film, amorphous carbon film, diamond film, diamond-like carbon film, metal, silicon or oxide, nitride, and carbide thereof are used. It is desirable that Here, examples of the mask base layer include a carbonized film obtained by baking a resist made of an organic material, a diamond film, and a diamond-like carbon film. Further, when the film is a diamond film or a diamond-like carbon film, a film doped with at least one of impurities such as boron, sulfur, nitrogen, phosphorus, or silicon can be used.

  The metal can be selected from refractory metals such as tungsten, molybdenum, tantalum, and niobium, or chromium, titanium and oxides, nitrides, carbides, and indium tin oxide thereof. Alternatively, it can be selected from silicon, silicon oxide, silicon nitride, and silicon carbide.

  As the mask base 13, any of metal, silicon, or an oxide, nitride, or carbide thereof can be used.

The film thickness of the mask base 13 is preferably 0.05 μm or more and 3 μm or less. If the film thickness is too thin, the strength of the mask base 13 may decrease when the current value is increased to increase the throughput of mask pattern processing. If it is too thick, the mask pattern processing accuracy will be increased. I can't.

  In FIG. 1B, the stencil mask is composed of a base body 11, a mask base layer 12b on the base body 11, and a mask base body 13 on the mask base base layer 12b.

  The mask base layer 12 b is present on the entire surface or a part of the base of the base 11 and the mask base 13. The mask base layer 12b may be a material thin film that can improve the adhesion thereof, but it is further desirable to have conductivity. In addition, the same manufacturing method, material, and film thickness as those of the mask base layer 12a in FIG. 1A described above can be used.

  2A and 2B are side cross-sectional views illustrating another stencil mask according to one embodiment of the present invention.

  In FIG. 2A, the stencil mask includes a base 21, an etching stopper layer 24 on the base 21, a mask base layer 22a formed on the etching stopper layer 24, and a mask base base layer 22a. And a mask base 23.

  Here, the base 21, the mask base layer 22a, and the mask base 23 can each be composed of the same structure and materials as described above with reference to FIG. The etching stopper layer 24 functions as a stopper layer when the substrate is removed by etching when a stencil mask is manufactured. The material of the etching stopper layer 24 can be selected from materials resistant to the etchant used when etching the substrate.

  In FIG. 2 (b), the stencil mask is charged on the base 21, the etching stopper layer 24 on the base 21, the mask base underlayer 22b on the etching stopper layer 24, and the mask base underlayer 22b. The mask matrix 23 has a transmission hole pattern through which particle beams pass.

  The mask base layer 22b exists on the entire surface or a part of the base of the mask base between the etching stopper layer 24 and the mask base. The mask base layer 22b may be a material thin film that can improve the adhesion thereof, but it is further desirable to have conductivity. In addition, as the manufacturing method, material, and film thickness, the same material as the mask base layer 22a in FIG. 2A described above can be used.

  Next, the manufacturing method of the stencil mask of this invention demonstrated above is demonstrated with reference to Fig.3 (a)-(f).

  FIG. 3 is a cross-sectional side view illustrating a manufacturing process of a stencil mask according to an aspect of the present invention.

  First, as shown in FIG. 3A, a mask base material layer 32 ′ is formed on a substrate 31 ′ by spin coating, sputtering, vapor deposition, ion plating, or chemical vapor deposition. Film. Here, as a material of the mask base material layer 32 ′, any material that is resistant to etching of the substrate material and the mask base material may be used. A carbon film, an amorphous carbon film, a diamond film, a diamond-like carbon film, a metal, It can be selected from silicon or oxides, nitrides and carbides thereof. The compound can be formed by reactive film formation in which oxygen, nitrogen, or carbon is added with oxygen, nitrous oxide, nitrogen, ammonia, or a hydrocarbon gas.

  Next, as shown in FIG. 3B, the mask base material layer 32 ′ is processed by, for example, a lithography method using an electron beam resist to form the mask base material layer 32. Here, a dry etching method or a wet etching method can be used for processing the pattern of the mask base layer 32 of the hard etching mask. Alternatively, after patterning a resist made of an organic material, it may be baked in a vacuum or an inert atmosphere and used as the mask base layer 32 of the hard etching mask.

  Subsequently, as shown in FIG. 3C, a mask base material layer 33 ′ is formed on the patterned mask base base layer 32 by physical vapor deposition or chemical vapor deposition. Here, as the physical vapor deposition method, sputtering, vapor deposition, and ion plating are used, and as the chemical vapor deposition method, microwave, ECR, high-frequency plasma chemical vapor deposition, or hot filament chemical vapor deposition is used. Phase growth can be used.

  Next, as shown in FIG. 3D, an opening is formed in the substrate 31 ′ to form a base 31. In this step, dry etching, wet etching, ultrasonic processing, sandblasting, or the like can be suitably used.

  Thereafter, as shown in FIG. 3E, a mask base body 33 having a predetermined transmission hole pattern is formed from the base 31 side using the mask base base layer 32 as an etching mask. The process of forming the transmission hole pattern is performed by sequentially performing a process of forming a mask base material 33 having a transmission port by dry etching the mask base material layer 33 ′ using the mask base layer 32 having a transmission port as an etching mask. Is called.

  Here, examples of the dry etching apparatus include apparatuses using discharge methods such as RIE, magnetron RIE, ECR, ICP, microwave, helicon wave, and NLD.

  A stencil mask is completed through the above steps. Furthermore, as shown in FIG. 3F, the mask base substrate underlying layer 32 exposed on the base of the mask base member 33 may be etched to form a mask base substrate residual layer 32a.

  Then, another example of the manufacturing method of the stencil mask of this invention is demonstrated with reference to Fig.4 (a)-(f).

  FIG. 4 is a side cross-sectional view showing a process for manufacturing a stencil mask according to another aspect of the present invention.

  First, as shown in FIG. 4A, an etching stopper layer 44 is formed on a substrate 41 ′, and then spin coating, sputtering, vapor deposition, ion plating, or chemical vapor deposition is used. Then, a mask base material layer 42 ′ is formed. Here, as the material of the mask base material layer 42 ′, the material having the physical properties and the manufacturing method described with reference to FIG. 3A can be used.

  Next, as shown in FIG. 4B, the mask base material layer 42 ′ is processed by, for example, a lithography method using an electron beam resist to form the mask base material layer 42. Here, a dry etching method or a wet etching method can be used for processing the mask pattern of the mask base layer 42 of the hard etching mask. Alternatively, after patterning a resist made of an organic material, it may be baked in a vacuum or an inert atmosphere and used as a mask.

  Subsequently, as shown in FIG. 4C, a mask base material layer 43 ′ is formed on the patterned mask base base layer 42 by physical vapor deposition or chemical vapor deposition. Here, as the physical vapor deposition method, sputtering, vapor deposition, and ion plating are used, and as the chemical vapor deposition method, microwave, ECR, high-frequency plasma chemical vapor deposition, or hot filament chemical vapor deposition is used. Phase growth can be used.

  Next, as shown in FIG. 4D, an opening is formed in the substrate 41 ′ to form a base body 41. In this step, dry etching, wet etching, ultrasonic processing, sandblasting, or the like can be suitably used. Etching is performed until the etching stopper layer 44 is exposed.

  Thereafter, as shown in FIG. 4E, the etching stopper layer 44 is etched away except for the portion in contact with the base 41 to form an etching stopper layer 44a. Then, a predetermined amount is used from the base 41 side using the mask base layer 42 as an etching mask. A mask base body 43 having a transmission hole pattern is formed. The process of forming the transmission hole pattern is performed by sequentially performing a process of forming a mask base 53 having a transmission port by dry etching the mask base material layer 43 ′ using the mask base layer 42 having a transmission port as an etching mask. Is called.

  Here, examples of the dry etching apparatus include apparatuses using discharge methods such as RIE, magnetron RIE, ECR, ICP, microwave, helicon wave, and NLD.

  A stencil mask is completed through the above steps. Further, as shown in FIG. 5 (f), the mask base base layer 42 exposed on the base of the mask base 43 may be etched to form a mask base base residual layer 52 a.

  With reference to FIGS. 3A to 3F, another stencil mask manufacturing process according to an embodiment of the present invention will be described.

  As shown in FIG. 3A, a chromium nitride film was formed as a mask base material layer 32 ′ on a single crystal silicon substrate as a substrate 31 ′ having a thickness of 525 μm by using a reactive sputtering method.

反応性スパッタの条件は上記の通りである。

The conditions for reactive sputtering are as described above.

  Next, an electron beam resist (not shown) is applied to a thickness of 0.5 μm on the mask base material layer 32 ′ made of a chromium nitride film, and an electron beam drawing machine with an acceleration voltage of 20 kV is applied thereto. Drawing was performed, and then development was performed using a dedicated alkali developer to form a resist pattern.

  Subsequently, as shown in FIG. 3B, a mask base material made of a chromium nitride film using a resist pattern as an etching mask, using a plasma etching apparatus, and using a mixed gas of chlorine and oxygen as an etching gas. The layer 32 ′ was dry-etched to a depth reaching the substrate 31 ′ to form a mask base substrate layer 32 having a transmission port, and then the resist was removed by ashing with oxygen plasma.

  Subsequently, as shown in FIG. 3C, a silicon film was formed as a mask base material layer 33 ′ on the substrate 31 ′ and the mask base base layer 32 by using a sputtering method.

上記シリコン膜作製の際のスパッタの条件は上記の通りである。

The sputtering conditions for producing the silicon film are as described above.

  Next, as shown in FIG. 3D, the substrate 31 ′ was processed by a photolithography method and dry etching to obtain a base 31. Here, carbon tetrafluoride was used as an etching gas.

  Subsequently, as shown in FIG. 3 (e), the mask base material layer 32 made of a chromium nitride film is used as an etching mask, the mask base material layer 33 ′ made of a silicon film, the mixed gas of SF6 and oxygen is used as an etching gas. Etching was performed with the ICP used as a mask matrix 33 having a transmission port.

  Further, as shown in FIG. 3F, the mask base substrate layer 32 other than the portion in contact with the substrate 31 is removed by wet etching using a cerium ammonium nitrate solution to form a mask base substrate residual layer 32a, and a stencil is formed. The mask is complete.

  A manufacturing process of a stencil mask according to an embodiment of the present invention will be described with reference to FIGS.

  As shown in FIG. 3 (a), an electron beam resist (ZEP520, manufactured by Nippon Zeon Co., Ltd.) is applied to a thickness of 0.2 μm on a single crystal silicon substrate as a substrate 31 ′ having a thickness of 525 μm, and an acceleration voltage of 20 kV is applied thereto. Then, the resist pattern was formed using an electron beam drawing machine and developed using a special alkaline developer. Thereafter, it was baked in a vacuum of 10 −4 Pa or less using a lamp annealing furnace for 1 hour to carbonize the resist, and a carbonized film was obtained as the mask base layer 32 (FIG. 3B).

  Next, as shown in FIG. 3C, an indium tin oxide film was formed as a mask base material layer 33 ′ on the substrate 31 ′ and the mask base base layer 32 by using a reactive sputtering method.

反応性スパッタの条件は上記の通りである。

The conditions for reactive sputtering are as described above.

  Next, as shown in FIG. 3D, the substrate 31 ′ was processed by a photolithography method and dry etching to obtain a base 31. Here, carbon tetrafluoride was used as an etching gas. The etching was stopped when the mask base layer 32 and the mask base material layer 33 'were exposed.

  Subsequently, as shown in FIG. 3E, an ICP using a mask base material layer 32 made of a carbonized film as an etching mask, a mask base material layer 33 ′ made of an indium tin oxide film, and HBr as an etching gas. Etching was performed to form a mask matrix 33 having a transmission port.

  Further, as shown in FIG. 3 (f), the mask base layer 32 made of a carbonized film other than the portion in contact with the base 31 is removed by ashing using oxygen gas to form a mask base base layer 32a, and a stencil is formed. The mask is complete.

  With reference to FIGS. 3A to 3F, another stencil mask manufacturing process according to an embodiment of the present invention will be described.

  As shown in FIG. 3A, a diamond-like carbon film is used as a mask base material layer 32 ′ using a parallel plate type plasma CVD apparatus on a single crystal silicon substrate as a substrate 31 ′ having a thickness of 525 μm. Was deposited.

プラズマＣＶＤの条件は上記の通りである。

The conditions for plasma CVD are as described above.

  Next, an electron beam resist (not shown) is applied to a thickness of 0.5 μm on the mask base material layer 32 ′ made of a diamond-like carbon film, and an electron beam drawing machine with an acceleration voltage of 20 kV is used for this. Then, development was performed using a dedicated alkali developer to form a resist pattern.

  Subsequently, as shown in FIG. 3B, a mask base material layer 32 ′ made of a diamond-like carbon film using a resist pattern as an etching mask, a plasma etching apparatus, and an oxygen gas as an etching gas. Was dry-etched to a depth reaching the substrate 31 ′ to form a mask base layer 32 having a transmission port, and then the resist was removed using a stripping solution.

  Next, as shown in FIG. 3C, an indium tin oxide film was formed as a mask base material layer 33 ′ on the substrate 31 ′ and the mask base base layer 32 by using a reactive sputtering method.

反応性スパッタの条件は上記の通りである。

The conditions for reactive sputtering are as described above.

  Next, as shown in FIG. 3D, the substrate 31 ′ was processed by a photolithography method and dry etching to obtain a base 31. Here, carbon tetrafluoride was used as an etching gas. The etching was stopped when the mask base layer 32 and the mask base material layer 33 'were exposed.

  Subsequently, as shown in FIG. 3E, the mask base material layer 32 made of a diamond-like carbon film is used as an etching mask, and the mask base material layer 33 ′ made of an indium tin oxide film is used as an etching gas. A mask matrix 33 having a transmission port was formed by etching using the ICP, and a stencil mask was completed. Here, in order to use the physical properties of the diamond-like carbon film as a mask material, the removal of the mask base layer 32 made of the diamond-like carbon film other than the portion in contact with the base 31 shown in FIG. Left behind.

  With reference to FIGS. 3A to 3F, another stencil mask manufacturing process according to an embodiment of the present invention will be described.

  As shown in FIG. 3A, a chromium nitride film was formed as a mask base material layer 32 ′ on a single crystal silicon substrate as a substrate 31 ′ having a thickness of 525 μm by using a reactive sputtering method.

反応性スパッタの条件は上記の通りである。

The conditions for reactive sputtering are as described above.

Next, an electron beam resist (not shown) is applied to a thickness of 0.5 μm on the mask base material layer 32 ′ made of a chromium nitride film, and an electron beam drawing machine with an acceleration voltage of 20 kV is applied thereto. Drawing was performed, and then development was performed using a dedicated alkali developer to form a resist pattern.

  Subsequently, as shown in FIG. 3B, a mask base material layer made of a chromium nitride film using a resist pattern as a mask, using a plasma etching apparatus, and using a mixed gas of chlorine and oxygen as an etching gas. 32 ′ was dry-etched to a depth reaching the substrate 31 ′ to form a mask base layer 32 having a transmission port, and then the resist was removed by ashing with oxygen plasma.

  Subsequently, as shown in FIG. 3C, an indium tin oxide film was formed as a mask base material layer 33 ′ on the substrate 31 ′ and the mask base base layer 32 by using a reactive sputtering method.

反応性スパッタの条件は上記の通りである。

The conditions for reactive sputtering are as described above.

  Next, as shown in FIG. 3D, the substrate 31 ′ was processed by a photolithography method and dry etching to obtain a base 31. Here, carbon tetrafluoride was used as an etching gas. The etching was stopped when the mask base layer 32 and the mask base material layer 33 'were exposed.

  Subsequently, as shown in FIG. 3E, an ICP using a mask base material layer 32 made of a chromium nitride film as an etching mask, a mask base material layer 33 ′ made of an indium tin oxide film, and HBr as an etching gas. Etching was performed to form a mask matrix 33 having a transmission port.

  Further, as shown in FIG. 3F, the mask base substrate layer 32 other than the portion in contact with the substrate 31 is removed by wet etching using a cerium ammonium nitrate solution to form a mask base substrate residual layer 32a, and a stencil is formed. The mask is complete.

  With reference to FIGS. 4A to 4F, another stencil mask manufacturing process according to an embodiment of the present invention will be described.

  As shown in FIG. 4 (a), an aluminum film is formed by sputtering as an etching stopper layer 44 on a single crystal silicon substrate as substrate ′ having a thickness of 525 μm, and then a mask base substrate is formed by reactive sputtering. A chromium nitride film was formed as the material layer 42 ′.

上記アルミニウム膜作製の際のスパッタの条件は上記の通りである。

The sputtering conditions for producing the aluminum film are as described above.

また、上記窒化クロム膜作製の際の反応性スパッタの条件は上記の通りである。

The reactive sputtering conditions for producing the chromium nitride film are as described above.

  Next, an electron beam resist (not shown) is applied to a thickness of 0.5 μm on the mask base material layer 42 ′ made of a chromium nitride film, and an electron beam drawing machine with an acceleration voltage of 20 kV is applied thereto. Drawing was performed, and then development was performed using a dedicated alkali developer to form a resist pattern.

Subsequently, as shown in FIG. 4B, a mask base material made of a chromium nitride film using a resist pattern as an etching mask, using a plasma etching apparatus, and using a mixed gas of chlorine and oxygen as an etching gas. The layer 42 ′ was dry etched to a depth reaching the etching stopper layer 44 to form a mask base substrate layer 42 having a transmission hole, and then the resist was removed by ashing with oxygen plasma.

  Further, as shown in FIG. 4C, a mask base material layer 43 ′ made of a silicon film is formed on the etching stopper layer 44 and the mask base base layer 42 by sputtering.

上記シリコン膜作製の際のスパッタの条件は上記の通りである。

The sputtering conditions for producing the silicon film are as described above.

  Next, as shown in FIG. 4D, the substrate 41 ′ was processed by a photolithography method and dry etching to obtain a base body 41. Here, carbon tetrafluoride was used as an etching gas. The etching was stopped when the etching stopper layer 44 was exposed.

  Subsequently, as shown in FIG. 4E, the etching stopper layer 44 made of an aluminum film is immersed in an aqueous solution of phosphoric acid, nitric acid, and acetic acid, and the portions other than the portion in contact with the base body 41 are removed by etching, thereby etching stopper base portion 44a. Then, the mask base material layer 43 ′ made of a silicon film is etched by ICP using SF 6 and oxygen as an etching gas and the mask base layer 42 ′ made of a silicon nitride is used as an etching mask. A mother body 43 was formed.

  Further, as shown in FIG. 4 (f), the mask base layer 42 other than the portion in contact with the etching stopper base 44a is removed by wet etching using a cerium ammonium nitrate solution to form a mask base base residual layer 42a. The stencil mask was completed.

  In the stencil mask manufactured as described above, the mask base has a very thin film thickness of 500 nm and the stress is low, so that no peeling or cracking occurs. In addition, the mask base layer was formed of a conductive film, and no charge-up due to electron beam irradiation occurred. Further, since the obtained stencil mask has a mask pattern previously patterned on a silicon substrate, there is no decrease in yield due to cracking of the thin film layer, and the pattern accuracy is high, and the thermal conductivity is also high. The irradiation characteristics were excellent.

1 is a side cross-sectional view illustrating a stencil mask according to one embodiment of the present invention. The side sectional view showing other examples of the stencil concerning one mode of the present invention. The sectional side view which shows the manufacturing method of the stencil mask which concerns on 1 aspect of this invention. The sectional side view which shows the other example of the manufacturing method of the stencil mask which concerns on 1 aspect of this invention. The sectional side view which shows the manufacturing method of the stencil mask which concerns on the one aspect | mode of the past. The sectional side view which shows the other example of the manufacturing method of the stencil mask which concerns on the one aspect | mode of the past.

Explanation of symbols

31 ', 41' ... Substrate 11, 21, 31, 41, 51, 61 ... Bases 12a, 12b, 22a, 22b ... Mask base layer 24, 44 ... Etching stopper layer 44a ... Etching stopper layer base 32 ', 42 '... mask base material layer 32, 42 ... mask base base layer 32a, 42a ... mask base base residual layer 33', 43 '... mask base material layer 13, 23, 33, 43, 53, 63 ... mask base 51' , 61 '... silicon support substrate 52', 62 '... intermediate oxide film 52, 62 ... intermediate oxide film remaining layer 53', 63 '... SOI layers 5A, 6A ... SOI substrate

Claims (3)

A substrate;
The supported on a substrate, the mask matrix having a transmission hole pattern, on at least a portion of the base side of the mask matrix, and a mask matrix underlayer,
The mask matrix is made of any of metal, silicon or oxides, nitrides and carbides thereof, and
The mask matrix underlayer diamond film containing sulfur, or a diamond-like carbon film containing sulfur, and,
A stencil mask, wherein the mask base layer is formed only on a base portion. Furthermore,
The stencil mask according to claim 1, further comprising an etching stopper layer exhibiting halogen-based plasma resistance between the base and the mask base layer. A pattern transfer method, comprising: irradiating the stencil mask according to claim 1 with a charged particle beam to shape the charged particle beam into a transfer pattern shape.

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