WO2002032030A1 - Dispositif et procede de reception - Google Patents
Dispositif et procede de reception Download PDFInfo
- Publication number
- WO2002032030A1 WO2002032030A1 PCT/JP2001/008841 JP0108841W WO0232030A1 WO 2002032030 A1 WO2002032030 A1 WO 2002032030A1 JP 0108841 W JP0108841 W JP 0108841W WO 0232030 A1 WO0232030 A1 WO 0232030A1
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- phase
- channel estimation
- value
- component
- estimation value
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/76—Pilot transmitters or receivers for control of transmission or for equalising
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0202—Channel estimation
- H04L25/0224—Channel estimation using sounding signals
- H04L25/0228—Channel estimation using sounding signals with direct estimation from sounding signals
- H04L25/023—Channel estimation using sounding signals with direct estimation from sounding signals with extension to other symbols
- H04L25/0232—Channel estimation using sounding signals with direct estimation from sounding signals with extension to other symbols by interpolation between sounding signals
- H04L25/0234—Channel estimation using sounding signals with direct estimation from sounding signals with extension to other symbols by interpolation between sounding signals by non-linear interpolation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0202—Channel estimation
- H04L25/0224—Channel estimation using sounding signals
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B2201/00—Indexing scheme relating to details of transmission systems not covered by a single group of H04B3/00 - H04B13/00
- H04B2201/69—Orthogonal indexing scheme relating to spread spectrum techniques in general
- H04B2201/707—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation
- H04B2201/70701—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation featuring pilot assisted reception
Definitions
- the present invention relates to a receiving apparatus for performing channel estimation using a pilot signal (known signal) used in a digital wireless / wired communication system.
- a pilot signal known signal
- FIG. 1 is a schematic diagram conceptually showing channel estimation by a conventional receiving apparatus.
- an information signal includes an Np symbol pilot signal (known signal). ) are periodically inserted (that is, a frame configuration in which a pilot signal of Np symbols is inserted in each slot). Estimate the propagation path that fluctuates due to leaf aging Note that the pilot signal of N p symbols is called a “pilot block”.
- pilot block in the n-th slot that is, the n-th pilot block (pilot block 11 in FIG. 1).
- in-phase addition of a plurality of pilot symbols in pilot block 11 is performed to obtain a channel estimation value in the n-th pilot block.
- This channel estimation value is expressed by the following equation.
- p is a pilot symbol for in-phase addition
- C n is the n-th pilot block.
- the channel estimation values of the K pilot slots before and after the n-th slot 21 are weighted and added to obtain the channel estimation value of the n-th slot 21.
- This channel estimation value is expressed by the following equation.
- W n is the weight coefficient of the n-th slot.
- FIG. 2 is a block diagram showing a configuration of a conventional receiving apparatus.
- FIG. 3 is a block diagram showing a configuration of a channel estimation circuit in a conventional receiving apparatus.
- a received signal is AZD-converted by an AZD converter 31 and sent to a despreading circuit 32.
- the despreading circuit 32 the pilot signal and the data signal (information signal) are despread using the AZD-converted received signal.
- the despread pilot signal is sent to channel estimation circuit 33, and the despread data signal is sent to synchronous detection circuit 34.
- channel estimation circuit 33 channel estimation is performed using the despread pilot signal, and a channel estimation value for synchronous detection is obtained.
- the despread pilot signal that is, the pilot symbol in the n-th pilot block
- the in-phase addition circuit 41 is in-phase-added by the in-phase addition circuit 41 as shown in FIG.
- This in-phase addition corresponds to that described in the above equation (1).
- the channel estimation value obtained by the in-phase addition by the in-phase addition circuit 41 is multiplied by the weight coefficient by the multiplier 42. For example, if the nth pilot block is In the case of the pilot block 11 (see FIG. 1), the channel estimation value in the pilot block 11 is multiplied by the weight coefficient W2. This multiplication corresponds to that described in the above equation (2).
- the channel estimation value multiplied by the weight coefficient is sent to the vector addition circuit 43.
- vector addition is performed on the channel estimation value multiplied by the weight coefficient by the multiplier 42 and the channel estimation value of another pilot block multiplied by the weight coefficient. For example, if the nth pilot block is a pilot block 11 (see FIG. 1), the channel estimation value of the pilot block 11 multiplied by the weighting factor W2 is multiplied by the weighting factor W1. Then, the channel estimation value in the pilot block 10 and the channel estimation value in the pilot block 12 multiplied by the weight coefficient W 2 are added to the vector. As a result, a channel estimation value for synchronous detection is obtained.
- the channel estimation value obtained by the channel estimation circuit 33 in this way is sent to the synchronous detection circuit 34 shown in FIG.
- the synchronous detection circuit 34 the synchronous detection process using the despread data signal from the despreading circuit 32 and the channel estimation value from the channel estimation circuit 33 is performed. Done.
- the synchronously detected data signal is sent to the RAKE combining circuit 35.
- the despreading circuit 32, the channel estimation circuit 33, and the synchronous detection circuit 34 described above are provided for each finger.
- the data signals that are synchronously detected by the synchronous detection circuit 34 in each of the fingers are RAKE combined by the RAKE combining circuit 35.
- the conventional receiving apparatus has the following problems. That is, when the phase offset is large due to frequency offset, fading, etc. during the period in which the pilot signal is inserted (that is, for example, the period in which the pilot block in FIG. 1 is inserted), the channel in FIG. When vector synthesis using weighted addition is performed in the estimation circuit 33, The amplitude component of the weighted channel estimation value decreases.
- FIG. 4A is a schematic diagram showing a first example of the amplitude component of the channel estimation value weighted and added by the conventional receiving apparatus.
- ⁇ FIG. 4B is the amplitude of the channel estimation value weighted and added by the conventional receiving apparatus.
- FIG. 4 is a schematic diagram showing a second example of the components. Note that, for simplicity, the channel estimate in the nth pilot block is the channel estimate in one other pilot block (the pilot program immediately before or immediately after the IIth pilot block). It is assumed that a weighted addition is made to the estimated value.
- the channel estimation value 51 indicates a channel estimation value in the n-th pilot block
- the channel estimation value 52 indicates a channel estimation value in another pilot block.
- the channel estimation value 54 indicates the channel estimation value in the n-th pilot block
- the channel estimation value 55 indicates the channel estimation value in another pilot block.
- channel estimation value 54 and channel estimation value 55 are used.
- the amplitude component of the channel estimation value 56 obtained by performing the weighting and the vector combination is greatly reduced.
- the synchronous detection is performed using the channel estimation value with the reduced amplitude component. Therefore, the amplitude of the data signal obtained by the synchronous detection also decreases. Therefore, since the maximum ratio combination of the synchronously detected data signals cannot be performed at the time of RAKE combining, the reception quality of the data signals obtained by the RAKE combining deteriorates.
- in-phase addition of a pilot signal is performed to calculate an in-phase addition value for each of a plurality of pilot symbols, and weighted addition is performed using the amplitude component and the phase component of the calculated in-phase addition value individually.
- the amplitude component and the phase component of the channel estimation value are calculated respectively.
- FIG. 1 is a schematic diagram conceptually showing channel estimation by a conventional receiving apparatus.
- FIG. 2 is a block diagram showing a configuration of a conventional receiving apparatus.
- FIG. 3 is a block diagram showing a configuration of a channel estimation circuit in a conventional receiver.
- FIG. 4A is a schematic diagram showing a first example of amplitude components of channel estimation values weighted and added by a conventional receiving apparatus.
- FIG. 4B is a schematic diagram showing a second example of the amplitude component of the channel estimation value weighted and added by the conventional receiving apparatus.
- FIG. 5 is a block diagram showing a configuration of the receiving apparatus according to the first embodiment of the present invention.
- FIG. 6 is a block diagram showing a configuration of a channel estimation circuit in the receiving device according to the first embodiment of the present invention.
- FIG. 7 is a schematic diagram conceptually showing channel estimation by the receiving apparatus according to the first embodiment of the present invention.
- FIG. 8 is a block diagram showing a configuration of the receiving apparatus according to the second embodiment of the present invention.
- FIG. 9 is a block diagram illustrating a configuration of a channel estimation circuit in the receiving apparatus according to the second embodiment of the present invention.
- FIG. 10 is a block diagram illustrating a configuration of a channel estimation circuit in the receiving apparatus according to the third embodiment of the present invention.
- FIG. 11 is a block diagram showing a configuration of a channel estimation circuit in the receiving apparatus according to the fourth embodiment of the present invention.
- FIG. 5 is a block diagram showing a configuration of the receiving apparatus according to the first embodiment of the present invention.
- the AD converter 101 performs AZD conversion on the received signal and sends it to the despreading circuit 102.
- the despreading circuit 102 despreads the pilot signal and the demodulated signal (information signal) using the A / D-converted received signal, and sends the despread pilot signal to the channel estimation circuit 103.
- Despread data The evening signal is sent to the synchronous detection circuit 104.
- Channel estimation circuit 103 performs channel estimation using the despread pilot signal, obtains a channel estimation value for synchronous detection, and sends it to synchronous detection circuit 104.
- the specific configuration of the channel estimation circuit 103 will be described later.
- Synchronous detection circuit 104 performs synchronous detection processing using the despread data signal from despreading circuit 102 and the channel estimation value from channel estimation circuit 103.
- the despreading circuit 102, the channel estimation circuit 103 and the synchronous detection circuit 104 described above are provided for each finger (FIG. 5 shows an example where the number of fingers is three). ing.
- the data signal synchronously detected by the synchronous detection circuit 104 in each finger is sent to the RAK synthesis circuit 105.
- FIG. 6 is a block diagram showing a configuration of a channel estimation circuit in the receiving apparatus according to the first embodiment of the present invention.
- an in-phase adding circuit 201 converts the pilot signal despread by the despreading circuit 102 shown in FIG. 5 into n symbols (where n is an integer of 1 or more) for each pilot block. Add phases.
- the angle detection circuit 202 detects the angle component of the pilot signal (in-phase addition value) added in-phase by the in-phase addition circuit 201 and sends it to the phase calculation circuit 203.
- the phase calculation circuit 203 performs a phase calculation process using the angle component of the pilot signal from the angle detection circuit 202 and the weight coefficient of each pilot block, and obtains the phase component of the channel estimation value.
- the absolute value calculation circuit 204 performs absolute value processing on the pilot signal (in-phase addition value) added in-phase by the in-phase addition circuit 201, and executes the in-phase added pilot signal (in-phase addition value). And sends it to multiplier 205.
- the multiplier 205 multiplies the amplitude component of the pilot signal from the absolute value calculation circuit 204 by a pilot block weighting factor.
- the amplitude calculation circuit 206 The amplitude component multiplied by the weight coefficient of the pilot block is added to obtain the amplitude component of the channel estimation value.
- the vector conversion circuit 207 converts the phase component of the channel estimation value from the phase calculation circuit 203 and the amplitude component of the channel estimation value from the amplitude calculation circuit 206 into a vector, and Output an estimate.
- FIG. 7 is a schematic diagram conceptually showing channel estimation by the receiving apparatus according to the first embodiment of the present invention.
- FIG. 7 shows an example in which the receiving apparatus according to the present embodiment is applied to a W—C D M A uplink.
- the data channel (channel for communicating data signals) is in-phase component
- the control channel (channel for communicating control signals such as pilot signals) is carried on quadrature components ( IQ multiplexing), and HPSK modulated by a scramble ring code and transmitted.
- the receiving apparatus transmits data signals (for example, “A” and “B” in FIG. 7) transmitted by the data channel and the control signal by the control channel.
- a control signal (for example, “P i 1 otj” in FIG. 7) is IQ-multiplexed and received.
- an n-symbol pilot signal (known signal) is periodically inserted into the control signal.
- An n-symbol pilot signal (“P ilot” in FIG. 7 corresponds to the pilot block described above).
- the received signal is A / D converted by an AZD converter 101 and sent to a despreading circuit 102.
- the despreading circuit 102 uses the A / D-converted received signal to generate a pilot signal (such as “Pi1ot” in FIG. 7) and a data signal (“A” and “A” in FIG. 7). "B") is despread.
- Despread pilot signal Is sent to a channel estimation circuit 103, and the despread data signal is sent to a synchronous detection circuit 104.
- the channel estimation circuit 103 channel estimation is performed using the despread pilot signal, and a channel estimation value for synchronous detection is obtained.
- the despread pilot signal ie, n pilot symbols in pilot program 302
- the angle detection circuit 202 detects the angle component of the pilot block 302 subjected to the in-phase addition. The detected angle component is sent to the phase calculation circuit 203.
- the phase calculation circuit 203 performs a phase calculation process using the angle component of the pilot signal from the angle detection circuit 202 and the weight coefficient of each pilot block.
- the phase component of the channel estimation value in pilot block 302 is obtained.
- the phase component of the channel estimation value in pilot block 302 is obtained by adding the in-phase-added angle component of pilot block 302, the in-phase added angle component of pilot block 301, and the in-phase addition.
- W 1 to W 3 see FIG. 7
- the in-phase added pilot signal That is, absolute value processing is performed on the pilot block 302), and the in-phase added amplitude component of the pilot block 302 is detected.
- the detected amplitude component is multiplied by the weight coefficient (W 2) of the pilot block 302 by the multiplier 205 and then sent to the amplitude calculation circuit 206.
- the amplitude component multiplied by the weight coefficient of each pilot block is added, and the amplitude component of the channel estimation value of the pilot block 302 is obtained.
- the amplitude component of the channel estimation value in the pilot program 302 is multiplied by the amplitude component of the pilot block 302 multiplied by the weight coefficient (W 2) and the weight coefficient (W 1).
- W 2 weight coefficient
- W 3 weight coefficient
- the amplitude component of the channel estimation value of the pilot block 302 obtained in this way is sent to the vector conversion circuit 207.
- the phase The phase component of the channel estimation value of the pilot block 302 from the arithmetic circuit 203 and the amplitude component of the channel estimation value of the pilot block 302 from the amplitude arithmetic circuit 206 are converted into a vector. As a result, a channel estimation value of pilot block 302 is obtained.
- the phase component and the amplitude component of the pilot signal subjected to in-phase addition are obtained, and then the phase component of each pilot block and the amplitude component of each pilot block are individually weighted and added.
- the phase component and the amplitude component of the channel estimation value are individually obtained.
- the phase and amplitude components of the obtained channel estimation value are converted to vectors to obtain the channel estimation value. This makes it possible to reduce the amount of phase rotation caused by frequency offset and fading as shown in Fig. 4B.
- the channel estimation value 54 and the channel estimation value 55 are added to each of the amplitude component and the phase component instead of simply performing the vector addition of the channel estimation value 54 and the channel estimation value 55 as in the related art. By weighting and adding, it is possible to prevent the amplitude component of the channel estimation value finally obtained from decreasing.
- the channel estimation value of pilot block 302 obtained in this way is sent to synchronous detection circuit 104 shown in FIG.
- synchronous detection processing is performed using the despread data signal from the despreading circuit 102 and the channel estimation value from the channel estimation circuit 103. That is, for example, if attention is paid to the synchronous detection processing for the data signal 304 (see FIG. 7), the synchronous detection circuit 104 outputs the despread data signal 304 from the despreading circuit 102. 4 and the channel estimation value of the pilot block 302 from the channel estimation circuit 103, a synchronous detection process is performed. As a result, a synchronously detected data signal 304 is obtained.
- the synchronously detected decryption signal is RAKE-combined with the decryption signals of other fingers in the RAK synthesis circuit 105.
- the RAKE combining circuit 105 converts each of the synchronously detected data signals into signals. The maximum ratio can be combined. Therefore, the reception quality of the overnight signal obtained by R AKE combining becomes good.
- weighting factor (W1 to W3 in the present embodiment) at the time of weighting addition in the middle of the slot (that is, according to the position of the information signal to be synchronously detected in the received signal).
- Such a setting of the weight coefficient reflects that the propagation path state in the data signal 304 is closest to the propagation path state in the pilot block 302.
- Such setting of the weighting factor reflects that the propagation path state in the overnight signal 305 is closest to the propagation path state of the pilot block 302 and the pilot block 303.
- the weighting factors are normalized such that the sum of all weighting factors is always constant (for example, 1 in the present embodiment).
- the weight coefficient is set in the middle of the slot (that is, the reception of the information signal to be synchronously detected) so that the pilot block corresponding to the channel closest to the channel in the data signal to be demodulated is reflected in the channel estimation.
- Switching (according to the position in the signal) enables more accurate channel estimation even when the amount of phase rotation is large.
- the channel estimation value of each pilot block is weighted and added for each amplitude component and each phase component, and the phase component and the amplitude component of the channel estimation value are individually determined.
- the information signal can be reduced while reducing the amount of calculation even in the presence of frequency offset and fading.
- the degradation of the reception quality can be reduced.
- by switching the weighting factor in the middle of the slot more accurate Channel estimation can be performed.
- the present embodiment has been described by taking as an example a case where a signal transmitted by IQ multiplexing a data channel and a control channel is received, the present invention is not limited to this, and a plurality of pilot signals are weighted.
- the present invention can be applied to the case where a signal transmitted in any frame format is received (for example, the frame format shown in FIG. 1). Things. That is, the present invention is applied only when, for example, a pilot block of a predetermined symbol (n symbol) receives a signal transmitted in a frame format (see FIG. 1) periodically inserted into each slot. Rather, it is applicable to a case where a pilot program provided with a different number of symbols for each slot receives a signal transmitted in a frame format periodically inserted in each slot. .
- FIG. 8 is a block diagram showing a configuration of the receiving apparatus according to the second embodiment of the present invention. Note that the same components as those in Embodiment 1 (FIG. 5) in FIG. 8 are denoted by the same reference numerals as those in FIG. 5, and detailed description thereof will be omitted.
- the phase rotation detecting circuit 401 uses a signal despread by the despreading circuit 102 (for example, it is possible to use a demodulated signal, but it is necessary to use a control signal such as a pilot signal). The phase difference of this signal is taken to detect the amount of phase rotation.
- the phase rotation detection circuit 401 sends the detected phase rotation amount to the channel estimation circuit 402.
- FIG. 9 is a block diagram showing a configuration of a channel estimation circuit in the receiving apparatus according to the second embodiment of the present invention.
- the same reference numerals as those in FIG. 3 denote the same parts, and a detailed description thereof will be omitted.
- the channel estimation circuit 402 shown in FIG. 9 controls the channel estimation circuit shown in FIG. 6 and the channel estimation circuit shown in FIG. 3 according to the amount of phase rotation from the phase rotation detection circuit 401. It is switched and used by the switch 501 controlled by the section 502.
- a highly accurate channel estimation value can be obtained by using the conventional channel estimation.
- the switch 501 can generate an in-phase added pilot signal from the in-phase addition circuit 201 so as to perform conventional channel estimation.
- the channel estimation value in each Pilot block multiplied by the weight coefficient is vector-added.
- the switch 501 is controlled by the control unit 502 to control the embodiment.
- the in-phase added pilot signal from the in-phase addition circuit 201 is sent to the angle detection circuit 202 and the absolute value calculation circuit 204.
- the same operation as that described in the first embodiment is performed.
- the threshold value when the phase rotation amount is small and when the phase rotation amount is large can be set, for example, depending on whether or not the reception quality of the synchronously detected data signal exceeds desired quality.
- the number can be switched in the middle of the slot.
- the amount of computation and the amount of memory at the time of channel estimation are changed. Increase can be suppressed. Furthermore, by controlling the weighting factor at the time of weighting addition according to the amount of phase rotation, highly accurate channel estimation can be performed regardless of the amount of phase rotation.
- this embodiment does not describe the RAKE combining, the despreading circuit 102, the phase rotation detecting circuit 401, the channel estimating circuit 402, and the synchronous detecting circuit shown in FIG.
- a circuit 104 for each finger and a RAKE combining circuit for RAKE combining the data signal synchronously detected by the synchronous detecting circuit 104 in each finger it is possible to perform maximum ratio combining of the overnight signals at each finger. Therefore, the reception quality of the overnight signal obtained by the RAKE combination is good.
- FIG. 10 relates to the third embodiment of the present invention.
- FIG. 3 is a block diagram illustrating a configuration of a channel estimation circuit in the receiving device. Note that the same components as those in Embodiment 1 (FIG. 6) and the conventional method (FIG. 3) in FIG. 10 are denoted by the same reference numerals as those in FIGS. 6 and 3, and detailed description is omitted. I do. Further, the configuration of the receiving apparatus according to the present embodiment is the same as that shown in FIG. 5 except for the internal configuration of channel estimation circuit 103, and thus detailed description is omitted.
- the channel estimation circuit shown in FIG. 10 is configured to be equivalent to the channel estimation circuit (FIG. 6) in the first embodiment.
- the normalization circuit 600 performs normalization on the pilot signal (in-phase addition value) added in-phase by the in-phase addition circuit 201, and outputs the normalized in-phase addition value. Send to multiplier 2.
- Multiplier 42 multiplies the normalized in-phase addition value from normalization circuit 600 by the weight coefficient of the pilot block to obtain a multiplication value for the pilot block.
- the vector addition circuit 43 adds the in-phase addition value (multiplication value) of each of the pilot blocks normalized and multiplied by the weight coefficient to obtain a vector addition value.
- the normalization circuit 600 performs normalization on the obtained vector added value.
- the multiplier 602 multiplies the normalized vector addition value from the normalization circuit 601 by the amplitude component of the channel estimation value from the amplitude calculation circuit 206 to obtain a channel estimation value.
- the operation of the receiving apparatus according to the present embodiment will be described using a case where channel estimation is performed using pilot block 302 in FIG. 7 as an example.
- pilot block 302 when performing channel estimation using the pilot block 302, as an example, one pilot block before and after the pilot block 302 (ie, the pilot block 301 and the pilot block 303) ) Is used for weighted addition.
- the operation of the receiving apparatus according to the present embodiment other than the channel estimation circuit is the same as that of the first embodiment, and a detailed description thereof will be omitted.
- the amplitude component of the channel estimation value is obtained by the amplitude calculation circuit 206 by performing the same processing as in the first embodiment.
- the amplitude component of the channel estimation value obtained by amplitude calculation circuit 206 is sent to multiplier 62.
- the normalization circuit 600 normalizes the in-phase addition value from the in-phase addition circuit 201 (the in-phase addition value of the pilot block 302). That is, in the normalization circuit 600, the in-phase addition value from the in-phase addition circuit 201 is a vector (unit vector) whose amplitude is 1. This corresponds to removing the influence of the amplitude component from the in-phase addition value from the in-phase addition circuit 201, and the phase detection is performed using the in-phase addition value in the angle detection circuit 202 in Embodiment 1 (FIG. 6). This is equivalent to seeking only the components.
- the in-phase addition value of the normalized pilot block 302 is multiplied by the weight coefficient (W 2) of the pilot block 302 by the multiplier 402. As a result, a multiplication value for pilot block 302 is obtained.
- the obtained multiplication value for pilot block 302 is sent to vector addition circuit 43.
- the multiplication value of each pilot block (that is, the in-phase addition value of each of the pilot blocks normalized and multiplied by the weight coefficient) is added to obtain a vector addition value.
- the multiplication value for the pilot block 302, the multiplication value for the pilot block 301, and the multiplication value for the pilot block 303 are added. Then, the vector addition value is obtained.
- the vector addition value obtained by the vector addition circuit 43 is, as described above, when the amount of phase rotation is small, the amount of decrease in the amplitude component is small (FIG. 4A), but the amount of phase rotation is small. Is large, the amplitude component is reduced. That is, in the vector addition value obtained by this vector addition, the accuracy is low for the amplitude component, but high for the phase component. But In the present embodiment, attention is paid to using the phase component in the vector addition value obtained by the vector addition circuit 43.
- the vector addition value obtained by the vector addition circuit 43 is normalized by the normalization circuit 61 to be a vector (unit vector) having an amplitude of 1.
- the vector having the magnitude of 1 obtained by the normalizing circuit 601 is multiplied by the amplitude component of the channel estimation value from the amplitude calculating circuit 206 in the multiplier 602.
- a channel estimation value is obtained.
- the channel estimation circuit of the present embodiment is equivalent to the channel estimation circuit of the first embodiment (FIG. 6).
- the accuracy of the obtained channel estimation value is the same as the accuracy of the channel estimation value obtained in the first embodiment.
- the required amount of computation and circuit scale can be reduced.
- phase component of the channel estimation value is determined using the conventional vector addition method in the case where it is applied to the receiving apparatus in Embodiment 1 has been described.
- Obtaining the phase component of the value can be similarly applied to the receiving apparatus according to the second embodiment.
- a vector addition value is obtained by vector-adding the in-phase addition value of each of the normalized pilot blocks, and a unit for normalizing the vector addition value to express a phase component.
- the channel estimation value is obtained by multiplying the amplitude component of the channel estimation value by this unit vector. This eliminates the need for the angle detection circuit 202 in Embodiments 1 and 2 described above, and thus requires a greater amount of computation and circuit scale than in Embodiments 1 and 2. (Amount of memory) can be reduced. (Embodiment 4)
- FIG. 11 is a block diagram showing a configuration of the channel estimation circuit in the receiving apparatus according to the fourth embodiment of the present invention. Note that the same components as those of the third embodiment (FIG. 10) in FIG. 11 are denoted by the same reference numerals as those in FIG. 10, and detailed description thereof will be omitted. Further, the configuration of the receiving apparatus according to the present embodiment is the same as that shown in FIG. 5 except for the internal configuration of channel estimation circuit 103, and therefore detailed description is omitted.
- the channel estimation circuit shown in FIG. 11 has a configuration obtained by removing the normalization circuit 600 from the channel estimation circuit (FIG. 10) in the third embodiment. That is, the in-phase addition circuit 201 sends the in-phase addition value to the multiplier 42, and the multiplier 42 multiplies the in-phase addition value from the in-phase addition circuit 201 by the weight coefficient of the pilot block.
- pilot block 302 in FIG. 7
- pilot block 302 one pilot block before and after pilot block 302 (that is, pilot block 301 and pilot block 303) Is used for weighted addition.
- pilot block 301 and pilot block 303 pilot block before and after pilot block 302
- pilot block 301 and pilot block 303 pilot block before and after pilot block 302
- the operation of the receiving apparatus according to the present embodiment other than the channel estimation circuit is the same as that of the first embodiment, and a detailed description thereof will be omitted.
- the amplitude component of the channel estimation value is subjected to the same processing as in the third embodiment, is obtained by the amplitude calculation circuit 206, and is sent to the multiplier 602.
- the in-phase addition value obtained by the in-phase addition circuit 201 (the in-phase addition value of the pilot block 302) is sent to the multiplier 42 without normalization. 3 0 2 weighting factor (W 2) and Multiplied.
- W 2 weighting factor
- a multiplied value for the pilot block 302 is obtained.
- the obtained multiplication value for the pilot block 302 is sent to the vector addition circuit 43.
- a multiplication value for each pilot block (that is, an in-phase addition value of each pilot block multiplied by a weight coefficient) is added to obtain a vector addition value.
- the multiplied value of the pilot block 302 the multiplied value of the pilot block 301, and the multiplied value of the pilot block 303 are added.
- the vector addition value is obtained.
- the vector addition value obtained by the vector addition circuit 43 is normalized by the normalization circuit 61 so as to be a vector (unit vector) having an amplitude of 1.
- the vector obtained by the normalization circuit 601 in the present embodiment is different from the vector obtained by the normalization circuit 601 in the third embodiment in the following points.
- the in-phase addition value of each of the pilot blocks normalized and multiplied by the weight coefficient is vector-added to obtain a vector addition value, and further, the vector addition value is normalized to obtain a phase component.
- a vector that indicates In other words, since the in-phase sum of each pilot block is converted to a vector of magnitude 1 and then weighted and added, the vector indicating the phase component contains the amplitude of the in-phase sum of each pilot block. Ingredients are not reflected.
- the in-phase addition value of each pilot block is weighted and added without being normalized, so that the vector representing the phase component includes the amplitude component of the in-phase addition value of each pilot block. Has been reflected.
- the vector indicating the phase component the amplitude component of the in-phase addition value of the pilot block having a larger amplitude component is reflected more heavily, and the amplitude component of the pilot block of the pilot block having the smaller amplitude component is reflected lighter. It has become.
- the vector indicating the phase component obtained in the present embodiment has higher accuracy than the vector indicating the phase component obtained in the third embodiment.
- the vector obtained by the normalization circuit 601 as described above is multiplied by the amplitude component of the channel estimation value from the amplitude calculation circuit 206 in the multiplier 602. This gives a channel estimate.
- the accuracy of the vector obtained by the normalization circuit 601 in the present embodiment is higher than the accuracy of the vector obtained by the normalization circuit 601 in the third embodiment
- the channel estimation value obtained in the embodiment is more accurate than the channel estimation value obtained in the third embodiment.
- a normalization circuit for normalizing the in-phase addition value of each pilot block that is, a normalization circuit of a number corresponding to the in-phase addition value to be vector-added
- an obtained vector In contrast to the necessity of a normalization circuit for normalizing the addition value, in the present embodiment, only the normalization circuit for normalizing the obtained vector addition value is required. Therefore, in the present embodiment, the required operation amount and circuit scale (memory amount) can be further reduced as compared with the third embodiment.
- the vector addition value is obtained by vector addition of the in-phase addition value of each pilot block, and this vector addition value is normalized and converted into a unit vector expressing a phase component.
- the channel estimation value is obtained by multiplying the amplitude component of the channel estimation value by this unit vector.
- in-phase addition of pilot signals is performed to calculate an in-phase addition value for each pilot symbol, and amplitude components and phase components of the calculated in-phase addition values are individually used.
- the amplitude component and the phase component of the channel estimation value are calculated in each case, and therefore, even in the presence of frequency offset and fading, it is possible to improve the channel estimation accuracy while suppressing the amount of calculation. It is possible to provide a receiving device that reduces deterioration of reception quality of an information signal.
- the present invention is suitable for use in a base station device and a communication terminal device in a digital mobile communication system.
- the base station device and the communication terminal device using the present invention can improve the channel estimation accuracy while suppressing the amount of operation and reduce the degradation of the reception quality of information signals even in the presence of frequency offset and fusing.
- a receiving device that reduces the number of demodulated signals a highly accurate demodulated signal can be obtained, so that good wireless communication can be performed.
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Radio Transmission System (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
- Circuits Of Receivers In General (AREA)
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP20010972716 EP1233561A1 (en) | 2000-10-10 | 2001-10-09 | Receiving device and receiving method |
AU2001292366A AU2001292366A1 (en) | 2000-10-10 | 2001-10-09 | Receiving device and receiving method |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000308883A JP3419749B2 (ja) | 2000-10-10 | 2000-10-10 | 受信装置および受信方法 |
JP2000-308883 | 2000-10-10 |
Publications (1)
Publication Number | Publication Date |
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WO2002032030A1 true WO2002032030A1 (fr) | 2002-04-18 |
Family
ID=18789132
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/JP2001/008841 WO2002032030A1 (fr) | 2000-10-10 | 2001-10-09 | Dispositif et procede de reception |
Country Status (7)
Country | Link |
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US (1) | US20030165185A1 (ja) |
EP (1) | EP1233561A1 (ja) |
JP (1) | JP3419749B2 (ja) |
KR (1) | KR100445496B1 (ja) |
CN (1) | CN1186896C (ja) |
AU (1) | AU2001292366A1 (ja) |
WO (1) | WO2002032030A1 (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7623467B1 (en) * | 2003-09-17 | 2009-11-24 | Atheros Communications, Inc. | Wireless channel estimation |
US7848438B2 (en) * | 2006-02-14 | 2010-12-07 | Motorola Mobility, Inc. | Method and apparatus for pilot signal transmission |
US7983208B2 (en) * | 2007-01-31 | 2011-07-19 | Telefonaktiebolaget Lm Ericsson (Publ) | MMSE channel estimation in a communications receiver |
JP5146592B2 (ja) * | 2009-02-18 | 2013-02-20 | 日本電気株式会社 | 周波数補正回路及び周波数補正方法並びにそれを用いた無線通信装置 |
US9118413B2 (en) * | 2012-12-20 | 2015-08-25 | Nokia Technologies Oy | Apparatus and a method |
Citations (6)
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JPH1051424A (ja) * | 1996-08-05 | 1998-02-20 | N T T Ido Tsushinmo Kk | Cdma復調装置 |
JPH11186990A (ja) * | 1997-12-18 | 1999-07-09 | Ntt Mobil Commun Network Inc | Cdma復調装置および方法 |
WO1999055033A1 (fr) * | 1998-04-23 | 1999-10-28 | Ntt Mobile Communications Network Inc. | Recepteur amdc et emetteur/recepteur amdc |
JP2000244366A (ja) * | 1999-02-24 | 2000-09-08 | Nec Corp | Cdma受信装置の受信パス・サーチ方法およびサーチャー回路 |
JP2001189768A (ja) * | 1999-12-28 | 2001-07-10 | Matsushita Electric Ind Co Ltd | 同期検波装置 |
JP2001267960A (ja) * | 2000-03-15 | 2001-09-28 | Nec Corp | Cdma復調装置及びその方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
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FR2709029B1 (fr) * | 1993-08-13 | 1995-10-20 | Matra Communication | Procédé de transmission pour des radio communications AMRC et dispositifs pour sa mise en Óoeuvre. |
JP2785804B2 (ja) * | 1996-05-30 | 1998-08-13 | 日本電気株式会社 | 移動通信システム |
JP3745502B2 (ja) * | 1997-06-24 | 2006-02-15 | ソニー株式会社 | 受信装置及び送受信装置並びに通信方法 |
JP3305639B2 (ja) * | 1997-12-24 | 2002-07-24 | 株式会社エヌ・ティ・ティ・ドコモ | 直接拡散cdma伝送方式におけるrake受信機 |
JP2982797B1 (ja) * | 1998-08-03 | 1999-11-29 | 日本電気株式会社 | Cdma受信装置における復調回路 |
US6192040B1 (en) * | 1999-04-16 | 2001-02-20 | Motorola, Inc. | Method and apparatus for producing channel estimate of a communication channel in a CDMA communication system |
-
2000
- 2000-10-10 JP JP2000308883A patent/JP3419749B2/ja not_active Expired - Fee Related
-
2001
- 2001-10-09 US US10/149,029 patent/US20030165185A1/en not_active Abandoned
- 2001-10-09 EP EP20010972716 patent/EP1233561A1/en not_active Withdrawn
- 2001-10-09 AU AU2001292366A patent/AU2001292366A1/en not_active Abandoned
- 2001-10-09 KR KR10-2002-7007336A patent/KR100445496B1/ko not_active IP Right Cessation
- 2001-10-09 WO PCT/JP2001/008841 patent/WO2002032030A1/ja not_active Application Discontinuation
- 2001-10-09 CN CNB018030599A patent/CN1186896C/zh not_active Expired - Fee Related
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1051424A (ja) * | 1996-08-05 | 1998-02-20 | N T T Ido Tsushinmo Kk | Cdma復調装置 |
JPH11186990A (ja) * | 1997-12-18 | 1999-07-09 | Ntt Mobil Commun Network Inc | Cdma復調装置および方法 |
WO1999055033A1 (fr) * | 1998-04-23 | 1999-10-28 | Ntt Mobile Communications Network Inc. | Recepteur amdc et emetteur/recepteur amdc |
JP2000244366A (ja) * | 1999-02-24 | 2000-09-08 | Nec Corp | Cdma受信装置の受信パス・サーチ方法およびサーチャー回路 |
JP2001189768A (ja) * | 1999-12-28 | 2001-07-10 | Matsushita Electric Ind Co Ltd | 同期検波装置 |
JP2001267960A (ja) * | 2000-03-15 | 2001-09-28 | Nec Corp | Cdma復調装置及びその方法 |
Also Published As
Publication number | Publication date |
---|---|
JP3419749B2 (ja) | 2003-06-23 |
CN1186896C (zh) | 2005-01-26 |
CN1393077A (zh) | 2003-01-22 |
EP1233561A1 (en) | 2002-08-21 |
JP2002118493A (ja) | 2002-04-19 |
AU2001292366A1 (en) | 2002-04-22 |
KR20020059848A (ko) | 2002-07-13 |
KR100445496B1 (ko) | 2004-08-21 |
US20030165185A1 (en) | 2003-09-04 |
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