WO2002014576A1 - Cible de pulverisation - Google Patents

Cible de pulverisation Download PDF

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Publication number
WO2002014576A1
WO2002014576A1 PCT/US2001/017996 US0117996W WO0214576A1 WO 2002014576 A1 WO2002014576 A1 WO 2002014576A1 US 0117996 W US0117996 W US 0117996W WO 0214576 A1 WO0214576 A1 WO 0214576A1
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WIPO (PCT)
Prior art keywords
alloying elements
thin film
sputtering target
elements comprise
less
Prior art date
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PCT/US2001/017996
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English (en)
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WO2002014576B1 (fr
Inventor
Jianxing Li
Stephen Turner
Lijun Yao
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Honeywell International Inc.
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Application filed by Honeywell International Inc. filed Critical Honeywell International Inc.
Priority to US10/297,001 priority Critical patent/US20030227068A1/en
Priority to EP01941866A priority patent/EP1309736A1/fr
Priority to AU2001275184A priority patent/AU2001275184A1/en
Priority to KR10-2003-7002169A priority patent/KR20030020986A/ko
Priority to JP2002519698A priority patent/JP2004506814A/ja
Publication of WO2002014576A1 publication Critical patent/WO2002014576A1/fr
Publication of WO2002014576B1 publication Critical patent/WO2002014576B1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C9/00—Alloys based on copper
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34—Sputtering
    • C23C14/3407—Cathode assembly for sputtering apparatus, e.g. Target
    • C23C14/3414—Metallurgical or chemical aspects of target preparation, e.g. casting, powder metallurgy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864—Thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the invention pertains to titanium alloy thin films with improved copper diffusion barrier properties.
  • the invention also pertains to titanium alloy sputtering targets, and additionally pertains to methods of inhibiting copper diffusion into substrates.
  • Integrated circuit interconnect technology is changing from aluminum subtractive processes to copper dual damascene processes.
  • the shift from aluminum and its alloys to copper and its alloys is causing new barrier layer materials, specifically TaN, to be developed.
  • TiN films which were used in aluminum technologies, could be formed by, for example, reactively sputtering a titanium target in a nitrogen-comprising sputtering gas atmosphere.
  • TiN films are reportedly poor barrier layers relative to copper in comparison to TaN because the diffusivity of copper atoms through TiN films is too high.
  • Fig. 1 illustrates a preferred barrier layer construction
  • Fig. 2 illustrates problems associated with TiN barrier layers.
  • Wafer fragment 10 comprises a substrate 12 which can comprise, for example, monocrystalline silicon.
  • substrate 12 can comprise, for example, monocrystalline silicon.
  • semiconductor substrate and “semiconductor substrate” are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials).
  • substrate refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
  • Insulative layer 14 is formed over substrate 12.
  • Insulative layer 14 can comprise, for example, silicon dioxide or borophosphosilicate glass (BPSG). .
  • BPSG borophosphosilicate glass
  • layer 14 can comprise fluorinated silicon dioxide having a dielectric constant less than or equal to 3.7, or a so-called "low-k" dielectric material.
  • layer 14 can comprise an insulative material having a dielectric constant less than or equal to 3.0.
  • a barrier layer 16 is formed to extend within a trench in insulative material 14, and a copper-containing seed layer 18 is formed on barrier layer 16.
  • Copper- > containing seed layer 18 can be formed by, for example, sputter deposition from a high purity copper target, with the term "high purity” referring to a target having at least 99.995% purity (i.e., 4N5 purity).
  • a copper-containing material 20 is formed over copper-containing seed layer 18, and can be formed by, for example, electrochemical deposition onto seed layer 18. Copper-containing material 20 and seed layer 18 can together be referred to as a copper-based layer or copper-based mass.
  • Barrier layer 16 is provided to prevent copper diffusion from materials 18 and 20 into insulative material 14. It has been reported that prior art titanium materials are not suitable as barrier layers for preventing diffusion of copper. Problems associated with prior art titanium-comprising materials are described with reference to Fig. 2, which shows the construction 10 of Fig. 1, but which is modified to illustrate specific problems that can occur if either pure titanium or titanium nitride are utilized as barrier layer 16. Specifically, Fig. 2 shows channels 22 extending through barrier layer 16. Channels 22 can result from columnar grain growth associated with the titanium materials of barrier layer 16. Channels 22 effectively provide paths for copper diffusion through a titanium-comprising barrier layer 16 and into insulative material 14.
  • the columnar grain growth can occur during formation of a Ti or TiN layer 16, or during high temperature processing subsequent to the deposition. Specifically, it is found that even when prior art titanium materials are deposited without columnar grain, the materials can fail at temperatures in excess of 450°C.
  • non-titanium barrier materials for diffusion layer 16 there has been a development of non-titanium barrier materials for diffusion layer 16.
  • tantalum nitride TaN
  • TaN tantalum nitride
  • a difficulty associated with TaN is that the high cost of tantalum can make it difficult to economically incorporate TaN layers into semiconductor fabrication processes.
  • Titanium alloys are a lower cost material than tantalum. Accordingly, it is . possible to reduce materials cost for the microelectronics industry relative to utilization of copper interconnect technology if methodology could be developed for utilizing titanium-comprising materials, instead of tantalum-comprising materials, as barrier layers for inhibiting copper diffusion. It is therefore desirable to develop new titanium-comprising materials which are suitable as barrier layers for impeding or ⁇ preventing copper diffusion.
  • the titanium comprising materials can be of any purity, but are preferably high purity; with the term "high purity” referring to a target having at least 99.95% purity (i.e., 3N5 purity).
  • the invention described herein relates to new titanium-comprising materials which can be utilized for forming titanium alloy sputtering targets. These sputtering targets can be used to replace tantalum-comprising targets due to their high-strength and resulting film properties. Specifically, in certain embodiments, the titanium alloy sputtering targets can be used to form barrier layers for Cu applications.
  • the titanium alloy sputtering targets can be reactively sputtered in a nitrogen-comprising sputtering gas atmosphere to form titanium alloy nitride film, or alternatively in a nitrogen- comprising and oxygen-comprising atmosphere to form titanium alloy oxygen nitrogen thin film.
  • the thin films formed in accordance with the present invention can have a non-columnar grain structure, low electrical resistivity, high chemical stability, and barrier layer properties comparable to those of TaN. Further, the titanium alloy sputtering target materials produced in accordance with the present invention are more cost-effective for semiconductor applications than are high-purity tantalum materials.
  • the invention encompasses a sputtering target comprising Ti and one or more alloying elements which have a standard electrode potential of less than - 1.0 volt.
  • a sputtering target comprising Ti and one or more alloying elements which have a standard electrode potential of less than - 1.0 volt.
  • Zr, Al or Si it can be desirable that they are ⁇ not present in the form of binary alloys with Ti (with binary complexes being TiZr, TiAl and TiSi).
  • a target comprises a binary alloy of TiZr, it can be desirable that Zr be present in a range of from 32-38 atom% or a range of 12-18 atom%>; or it can be desired to have the Zr present in any amount from greater than 0 atom% to less than 50 atom% in Cu barrier applications.
  • the sputtering target comprises multiple alloying elements
  • all of the alloying elements can have the standard electrode potential of less than -1.0 volt, or less than all of the alloying elements can have
  • the invention encompasses a method of inhibiting copper diffusion into a substrate.
  • a first layer comprising titanium and one or more alloying elements which have a standard electrode potential of less than -1.0V is formed over the substrate.
  • a copper-based layer is then formed over the first layer and separated from the substrate by the first layer.
  • the first layer inhibits copper diffusion from the copper-based layer to the substrate.
  • the invention encompasses a sputtering target comprising Ti and one or more elements which have melting temperatures greater than or equal to 2400°C.
  • all of the elements other than Ti can have the melting temperature greater than or equal to 2400°C, or less than all of the elements other than Ti can have the melting temperature greater than or equal to 2400°C.
  • the invention encompasses a sputtering target comprising Ti and one or more alloying elements with differences in atomic radii relative to Ti of at least 8%, or at least 10%, and in some applications at least 20%.
  • the sputtering target comprises multiple alloying elements
  • all of the alloying elements can have the difference in atomic radii relative to Ti of at least 8%, or less than all of the alloying elements can have the difference in atomic radii relative to Ti of at least 8%.
  • titanium-based material is defined as a material in which titanium is a majority element
  • an “alloying element” is defined as an element that is not a majority element in a particular material.
  • a “majority element” is defined as an element which is present in larger concentration than any other element of material.
  • a majority element can be a predominate element of material, but can also be present as less than 50% of a material.
  • titanium can be a majority element of a material in which the titanium is present to only 30%, provided that no other element is present in the material to a concentration of greater than or equal to 30%.
  • alloying elements present to concentrations of less than or equal to 30% would be "alloying elements.”
  • titanium-based materials described herein will contain alloying elements at concentrations of from 0.001 atom % to 50 atom %.
  • the percentages and concentrations referred to herein are atom percentages and concentrations, except, of course, for any concentrations and percentages specifically indicated to be other than atom percentages or concentrations.
  • copper-based material is defined as a material in which copper is the majority element.
  • FIG. 1 is a diagrammatic, cross-sectional view of a prior art semiconductor wafer fragment illustrating a conductive copper material separated from an insulative material by a barrier layer. >
  • Fig. 2 is a view of the Fig. 1 prior art wafer fragment illustrating problems which can occur when utilizing prior art Ti-containing materials as the barrier layer.
  • Fig. 3 is a diagrammatic, cross-sectional view of semiconductor wafer fragment at a preliminary step of a method of the present invention.
  • Fig. 4 is a view of the Fig. 3 wafer fragment shown at a processing step subsequent to that of Fig. 4.
  • Fig. 5 is a view of the Fig. 3 wafer fragment shown at a processing step subsequent to that of Fig. 4.
  • Fig. 6 is a view of the Fig. 3 wafer fragment shown at a processing step subsequent to that of Fig. 5.
  • Fig. 7 is an expanded view of a portion of the Fig. 5 wafer fragment.
  • Fig. 8 is a diagrammatic graph illustrating a relative concentration of a material "Q" relative to a copper-containing layer, TiQ layer and SiO layer along an axis shown in Fig. 4.
  • Fig. 9 is a diagrammatic graph of a relative concentration of a material "Q" relative to a copper-containing layer, TiQ layer and SiO layer along an axis shown in Fig. 5.
  • Fig. 10 is a chart showing improvements in mechanical properties of Ti-Zr alloys in comparison to prior art Ta.
  • Fig. 11 is a diagrammatic, cross-sectional view of an exemplary sputtering target construction.
  • Fig. 12 is a graph illustrating a Rutherford Back-scattering Spectroscopy (RBS) profile of as-deposited Tio. 45 Zro. 02 N 0.52 .
  • Fig. 13 is an illustration of sheet resistance of Ti 0.45 Zro . o 2 N 0 . 52 .
  • the Rs spacing is equal to 1/3 sigma, and the shown gradients correspond to 68.99; 67.88; 66.76; 65.65; 64.54; 63.42; 62.31; 61.19; and 60.08.
  • Fig. 14 is a graph illustrating a Rutherford Back-scattering Spectroscopy profile Tio . 5 Zr 0. o 2 No. 52 after vacuum annealing for 1 hour at from 450°C to 700°C.
  • Fig. 15 is a graph illustrating a Rutherford Back-scattering Spectroscopy profile of a TiZrN thin film after stripping Cu layer from a wafer.
  • the TiZrN thin film and Cu layer being initially part of a structure formed in accordance with an exemplary method of the present invention.
  • the illustrated data shows no apparent diffusion of Cu into the TiZrN layer after 5 hours at 700°C.
  • Wafer fragment 50 comprises a semiconductive material substrate 52, such as, for example, monocrystalline silicon.
  • An insulative material 54 is formed over substrate 52, and an opening 56 is formed into insulative material 54.
  • Materials 52 and 54 can comprise the same materials as described with reference to the prior art for materials 12 and 14, respectively.
  • Opening 56 can comprise, for example, a trench for formation of copper in a dual damascene process.
  • barrier layer 58 is formed over insulative layer 54 and within opening 56.
  • barrier layer 58 comprises titanium, and is configured to impede diffusion from subsequently-formed copper-based layers into insulative material 54.
  • barrier layer 58 comprises titanium and one or more elements which have a standard electrode potential (specifically, a standard reduction potential measured with a Cl " /Cl reference electrode) of less than - 1.0V (i.e. more negative than -1.0 volt).
  • Suitable elements can be selected from the group consisting of Al, Ba, Be, Ca, Ce, Cs, Hf, La, Mg, Nd, Sc, Sr, Y, Mn, V, Si and Zr; although in particular embodiments the elements will not include Al, Si, or Zr.
  • barrier layer 58 can consist essentially of the titanium and one or more elements having a standard electrode potential of less than about -1.0 V, or can consist of the titanium and one or more elements having a standard electrode potential of less than -1.OV.
  • Barrier layer 58 can also comprise one or both of nitrogen and oxygen in addition to the Ti and the one or more elements having a standard electrode potential of less than -1.0V.
  • Layer 58 can be considered as a film formed over substrate 54, and in particular embodiments will have a thickness of from about 2 nanometers to about 500 nanometers, and can specifically have a thickness of from about 2 nanometers to about 50 nanometers, or can specifically have a thickness of from about 2 nanometers to about 20 nanometers.
  • barrier layer 58 comprises titanium and one or more elements which have a melting temperature of greater than or equal to about 2400°C. Suitable elements can be selected from the group consisting of Nb, Mo, Ta and W.
  • barrier layer 58 can consist essentially of the titanium and one or more elements having a melting temperature of greater than or equal to about 2400°C, or can consist of the titanium and one or more elements having a melting temperature of greater than or equal to about 2400°C. Barrier layer 58 can also comprise one or both of nitrogen and oxygen in addition to the Ti and the one or more elements having a melting temperature of greater than or equal to about 2400°C. Layer 58 can be considered as a film formed over substrate 54, and in particular embodiments will have a thickness of from about 2 nanometers to about 50 nanometers, and can specifically have a thickness of from about 2 nanometers to about 20 nanometers.
  • the elements having a melting temperature of greater than or equal to about 2400°C can stabilize a titanium alloy due to refractory characteristics of the elements.
  • the elements incorporated into the titanium-comprising ⁇ targets can have atomic sizes which are more than 8% different than the atomic size of titanium, and preferably more than 10%), or even more than 20% different than the atomic size of titanium.
  • Such difference in atomic size can disrupt a titanium lattice structure, and accordingly impede grain growth within the lattice.
  • a magnitude of difference in grain size between the titanium and the other elements incorporated into barrier layer 58 can effect the amount by which a lattice is disrupted, and accordingly can influence an amount of grain growth occurring at various temperatures.
  • a group of elements having an atomic radii difference relative to titanium of at least 8% is Mn, Fe, Co, Ni and Y; and a group of elements having an atomic radii difference relative to titanium of at least 20% is Be, B, C, La, Ce, Pr, P, S, Nd, Sm, Si, Gd, Dy, Ho, Er, and Yb. It is noted that some of the elements having an atomic radii difference relative to titanium of greater than 8%, or greater than 20%, overlap with the elements having a standard electrode potential of less than -l.OV, and some do not.
  • the present invention encompasses utilizing elements having an atomic radii difference relative to titanium of greater than 8%> (or in some applications greater than 20%) in combination with titanium for forming barrier layers, and accordingly comprises sputtering targets comprising titanium and one or more of Si, P, S, Sc, Mn, Fe, Co, Ni, Y, Be, B, C, Mo, La, Ce, Pr, Nd, Sm, Gd, Dy, Ho, Er, and Yb.
  • the invention encompasses alloying elements that fall within three categories: a standard electrode potential of less than about -l.OV; a melting temperature of greater than or equal to about 2400°C; or an atomic size which is more than 8% different than the atomic size of titanium.
  • Table 1 lists several exemplary elements that can fall within one or more of such three categories. Table 1 is not an ' all-inclusive listing of elements that fit within one or more of the three categories.
  • layer 58 is a barrier layer for preventing diffusion from a conductive copper-based material to insulative material 54.
  • barrier layer 58 it can be preferred that barrier layer 58 be conductive to provide additional electron flow beyond that provided by the conductive copper-based layer.
  • barrier layer 58 it can be preferred that barrier layer 58 have an electrical resistivity of equal to or less than 300 ⁇ *cm.
  • An exemplary method of forming barrier layer 58 is to sputter deposit layer 58 from a target comprising titanium and one or more elements.
  • the one or more elements can have a standard electrode potential of less than about -l.OV, an atomic radii size difference relative to Ti of at least 8%>, and/or melting temperatures greater than or equal to 2400°C.
  • the target can consist essentially of the titanium and the one or more elements which have a standard electrode potential of less than about -l.OV, an atomic radii size difference relative to Ti of at least 8%, and/or melting temperatures greater than or equal to 2400°C.
  • the invention encompasses embodiments wherein the target consists of the titanium and the one or more elements having a standard electrode potential of less than about - l.OV, an atomic radii size difference relative to Ti of at least 8%, and/or melting temperatures greater than or equal to 2400°C.
  • An exemplary target will comprise at least 50 atom% titanium, and from 0.001 atom% to 50 atom% of the one or more elements having a standard electrode potential of less than about -1.0V, an atomic radii size difference relative to Ti of at least 8%, and/or melting temperatures greater than or equal to 2400°C.
  • the target can comprise at least 90 atom.% titanium, and from 0.001 atom%> to 10 atom% of the one or more elements which have a standard electrode potential of less than -l.OV, an atomic radii size difference relative to Ti of at least 8%>, and/or melting temperatures greater than or equal to 2400°C.
  • targets of the present invention can differ from the previous targets in that they are used for copper barrier applications and/or the concentration of the Nb, W and Zr can be different in targets of the present invention than in previous targets.
  • an alloy of the present invention can comprise titanium as the majority element and include an additional element of Nb, W or Zr, excluding the ranges 32-38 atom % and 12-18 atom% for Zr; excluding the range 6-8 atom % for Nb; and excluding the range 35-50 atom % for W.
  • prior art titanium- comprising targets can be utilized for a new method in accordance with methodology of the present invention for forming copper barrier layers.
  • a target utilized in methodology of the present invention can be sputtered in an atmosphere such that only target materials are deposited in film 58, or alternatively can be sputtered in an atmosphere so that materials from the atmosphere are deposited in barrier layer 58 together with the materials from the target.
  • the target can be sputtered in an atmosphere comprising a nitrogen-containing component to form a barrier layer 58 that comprises nitrogen in addition to the materials from the target.
  • An exemplary nitrogen-containing component is diatomic nitrogen (N 2 ).
  • the deposited thin film can be referred to by the stoichiometry Ti x Q y N z , with "Q" being a label for the one or more elements having a standard electrode potential of less than - l.OV, an atomic radii size difference relative to Ti of at least 8%, and/or melting temperatures greater than or equal to 2400°C, that were incorporated into the target.
  • barrier layer 58 Another exemplary method of forming barrier layer 58 is to sputter deposit the layer from a target comprising titanium and one or more elements other than titanium in the presence of both a nitrogen-comprising component and an oxygen-comprising component, to incorporate both nitrogen and oxygen into barrier layer 58.
  • Such processing can form a barrier layer having the stoichiometry Ti x Q y N z O w , with Q again referring to the elements having an atomic radii size difference relative to Ti of at least 8%, elements comprising a standard electrode potential of less than about -l.OV, > and/or elements having melting temperatures greater than or equal to 2400°C.
  • the oxygen-containing component used to form the Ti x Q y N z O w can be, for example O 2 .
  • nitrogen and/or oxygen can, for example, disturb a Ti columnar grain structure and thus form a more equi-axed grain structure.
  • a barrier layer 58 formed in accordance with the present invention can comprise a mean grain size of less than or equal to 100 nanometers, and in particular processing can preferably comprise a mean grain size of less than or equal to 10 nanometers. More preferably, the barrier layer can comprise a mean grain size of less than 1 nanometer. Further, the barrier layer material can have sufficient stability so that the mean grain size remains less than or equal to 100 nanometers, and in particular embodiments less than or equal to 10 nanometers or 1 nanometer, after the film is exposed to 500°C for 30 minutes in a vacuum anneal.
  • the small mean grain size of the film 58 of the present invention can enable the film to better preclude copper diffusion than can prior art titanium-containing films.
  • the prior art titanium-containing films frequently would form large grain sizes at processing above 450°C, and accordingly would have the columnar-type defects described above with reference to Fig. 2.
  • Processing of the present invention can avoid formation of such defects, and accordingly can enable better titanium-containing diffusion layers to be formed than could be formed by prior art processing.
  • Copper-containing seed layer 60 is formed over barrier layer 58.
  • Copper-containing seed layer 60 can comprise, for example, ' high purity copper (i.e., copper which is at least 99.995% pure), and can be deposited by, for example, sputter deposition from a high purity copper target.
  • Fig. 7 shows an expanded view of a region of the Fig. 5 wafer fragment 50, and more clearly illustrates the region 62.
  • Fig. 7 also illustrates that another region 64 having an enhanced concentration of the elements with a standard electrode potential of less than -1.0V can be formed adjacent to copper-based layer 60.
  • Region 64 is not shown in Fig. 5 due to limitations of space in the drawing. It is to be understood that region 64 may be effectively eliminated in particular processing of the present invention, depending on the elements incorporated into barrier layer 58.
  • Figs. 8 and 9 graphically illustrate the aspect of the invention that elements with a standard electrode potential less than -1.0V can migrate within barrier layer 58 during a high-temperature anneal.
  • Fig. 8 such illustrates a graph ofa concentration of the elements with a standard electrode potential of less than -1.OV (illustrated as "Q", and specifically illustrated as a relative percent of "Q") relative to the copper of layer 60, the TiQ of layer 58 and the SiO of layer 54.
  • Q concentration of the elements with a standard electrode potential of less than -1.OV
  • the TiQ and SiO are not intended to be stoichometric representations of the materials of either barrier layer 58 or insulative material 54, but rather simply identify layers 58 and 64 in the drawing of Fig.
  • Fig. 8 (for instance, the material referred to as "SiO" would generally be SiO 2 ).
  • the graph of Fig. 8 is illustrated along an axis shown in Fig. 4, and accordingly corresponds to a processing step prior to the anneal of Fig. 5.
  • Fig. 9 shows a graph similar to that of Fig. 8, but shows the graph along an axis of Fig. 5, and accordingly is showing relative concentrations after the Fig. 5 anneal.
  • Fig. 9 illustrates that a concentration of Q is increased at an interface between the TiQ layer 58 and SiO layer 54, relative to a concentration throughout a middle region of TiQ.
  • Fig. 9 also illustrates that a concentration of Q can be increased at an interface between copper-based layer 60 and TiQ layer 58.
  • Figs. 8 and 9 refer to insulative layer 54 specifically as a SiO layer, such is an exemplary composition for insulative layer 54, and the invention encompasses embodiments wherein layer 54 comprises other insulative materials. It is also to be understood that the relative concentrations of Q shown in Fig. 9 are for illustrative purposes only, and that Fig. 9 is showing a qualitative representation of the concentrations of Q, rather than a quantitative representation.
  • Figs. 7, 8 and 9 An advantage of utilizing an element having a standard electrode potential of less than -l.OV is evidenced by Figs. 7, 8 and 9. Specifically, such elements will tend to diffuse toward the interface regions of barrier layer 58 during an anneal. The element can thus form the regions 62 and 64 of Fig. 7, which can have enhanced copper-barrier aspects relative to the remaining central region of layer 58. Also, the region 62 can have enhanced characteristics for adhering layer 58 to insulative material 54. Accordingly, barrier layers formed in accordance with the present invention can adhere to insulative materials better than barrier layers formed in accordance with the prior art, and can thus alleviate some of the problems associated with prior art barrier layers.
  • Fig. 6 illustrates wafer fragment 50 at a processing step subsequent to that of Fig. 5, and specifically shows a copper-based material 70 formed within trench 56 (Fig. 5).
  • Copper-based material 70 can be formed by, for example, electrodeposition of copper onto seed layer 60.
  • An advantage of having a conductive barrier layer 58 is evidenced in Fig. 6. Specifically, as trenches become increasingly smaller, the amount of the trench made smaller by barrier layer 58 relative to that consumed by copper material 70 can increase. Accordingly, layers 58, 60 and 70 can be considered a conductive component, with layer 58 having an increasingly larger representative volume as trench sizes become smaller. A reason that layer 58 can have an increasingly larger volume is that there are limits relative to the thickness of layer 58 desired to maintain suitable copper-diffusion barrier characteristics.
  • Fig. 10 shows that materials formed in accordance with the present invention can have mechanical properties equal to, or better than, those of 3N5 tantalum, with the mechanical properties of Fig. 10 being reported in units of Ksi (i.e, 1000 lbs/in 2 ).
  • the invention is illustrated by, but not limited to, the following examples.
  • the examples describe exemplary methodologies for forming sputtering targets comprising various materials encompassed by the present invention.
  • the sputtering targets can have any of numerous geometries, with an exemplary geometry being a so-called ENDURATM target of the type available from Honeywell Electronics, Inc.
  • An exemplary ENDURATM target construction 200 is shown in Fig. 11 to comprise a backing plate 202 and a target 204.
  • Target construction 200 is shown in cross- > sectional view in Fig. 11, and would typically comprise a circular outer periphery if viewed from the top.
  • target construction 200 is shown to comprise the backing plate 202 supporting the target 204, it is to be understood that the invention also encompasses monolithic target constructions (i.e., target constructions in which, the entirety ofa construction is target material) and other planar target designs.
  • a TiY target comprises 1.0at% Y, which is a reactive element with a standard electrode potential of —2.6V and has an atomic radii which is 13.5% larger than that of Ti.
  • a predetermined amount of 3N (99.9%) purity Y was added to a 5N (99.999%) purity Ti during a vacuum skull melt. After a homogeneous alloy is formed, the alloy was cast into a graphite mold to form a billet. The billet was forged and rolled using conventional thermomechanical processes and fabricated into a sputtering target.
  • the Ti-5at%Y target was reactively sputtered in a N 2 /Ar atmosphere with four different values for N 2 flows (0, 5, 10, 15 seem) and with a total chamber pressure of 4 x 10 "3 mTorr.
  • the resulting TiYN thin film had a thickness of approximately 20 nm, an electrical resistivity ranging from approximately 130-300 ⁇ *cm, and comprised a very small grain size, which could not be measured by x-ray and could be microcrystalline or amorphous.
  • a TiTa target comprises 0.65at% Ta, which is an element with a melting point of 2996°C and is a reactive element with a standard electrode potential of -1.07V.
  • a predetermined amount of 3N5 (99.95%) purity Ta was added to a 5N (99.999%) purity Ti during a vacuum skull melt. After a homogeneous alloy was formed, the alloy was cast into a graphite mold to form a billet. The billet was forged and rolled using conventional thermomechanical processes, and fabricated into a sputtering target.
  • the Ti-0.65at%Ta target was reactively sputtered in a N 2 /Ar atmosphere with four different values for N 2 flows (0, 5, 10, 15 seem) and with a total chamber pressure of 4 x 10 "3 mTorr.
  • the resulting TiTaN thin film had a thickness of approximately 20 nm, an electrical resistivity ranging from approximately 130-250 ⁇ »cm and comprised avery small grain size, which could not be measured by x-ray and could be microcrystalline or amorphous.
  • a TiZr target comprises 5.0at%> Zr, which is a reactive element with a standard electrode potential of -1.65V.
  • a predetermined amount of 2N8 (99.8%) purity Zr was added to a 5N (99.999%>) purity Ti during a vacuum skull melt.
  • the alloy was cast into a graphite crucible to form a billet.
  • the billet was forged and rolled using conventional thermomechanical processes and fabricated into a sputtering target.
  • the Ti-5at%Zr target was reactively sputtered in a N 2 /Ar atmosphere.
  • the resulting TiZrN thin film had a thickness of • approximately 20 nm and an electrical resistivity of approximately 125 ⁇ *cm.
  • the TiZrN film had a very small grain size, which could not be measured by x-ray and could be > microcrystalline or amorphous, which was stable after vacuum annealing at 700°C for 5 hours.
  • a 150 nm Cu film was then deposited onto the TiZrN film so that diffusional properties of the TiZrN film could be tested after annealing at high temperature. Results indicate that the TiZrN film had good adhesion to intermetallic dielectrics and wetting characteristics with Cu.
  • the thin film had overall properties that are adequate for a typical Cu/low-k dielectric process. Fig.
  • FIG. 12 shows the Rutherford Back- scattering Spectroscopy (RBS) profile of as-deposited Tio. 5 Zr 0 .o2 4 N 0 . 52 ; and Table 2 tabulates various aspects of the data of Fig. 12.
  • Figure 14 illustrates that there is no apparent diffusion of Cu into the TiZrN layer after vacuum annealing at about 450 - 700°C for 1 hour.
  • Fig. 15 shows the RBS profile of the TiZrN film after the Cu layer has been stripped from the wafer. This figure again shows no apparent diffusion of Cu into the TiZrN layer after 5 hours at 700°C. TABLE 2; RBS determined film composition in atomic percent

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Abstract

L'invention concerne de nouveaux matériaux contenant du titane qui peuvent servir à former des cibles de pulvérisation en alliage de titane. Ces dernières peuvent être pulvérisées réactivement dans une atmosphère de pulvérisation comportant du nitrogène, en vue de former un film en alliage TiN ou une atmosphère de pulvérisation comportant du nitrogène et de l'oxygène, en vue de réaliser un film fin en alliage TiON. Les films fins ainsi formés peuvent posséder une structure granulaire non-basaltique, une faible capacité de résistance électrique, une forte stabilité chimique et des propriétés de couche de protection comparables à celles de TaN pour des applications de protection Cu de films fins. De plus, les matériaux de cibles de pulvérisation en alliage de titane produites conformément à la présente invention sont plus rentables pour les applications de semi-conducteurs que les matériaux en tantale très purs et possèdent de plus, une force mécanique supérieure adaptée à des applications de pulvérisation à énergie élevée.
PCT/US2001/017996 2000-08-15 2001-05-31 Cible de pulverisation WO2002014576A1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
US10/297,001 US20030227068A1 (en) 2001-05-31 2001-05-31 Sputtering target
EP01941866A EP1309736A1 (fr) 2000-08-15 2001-05-31 Cible de pulverisation
AU2001275184A AU2001275184A1 (en) 2000-08-15 2001-05-31 Sputtering target
KR10-2003-7002169A KR20030020986A (ko) 2000-08-15 2001-05-31 스퍼터링 타겟
JP2002519698A JP2004506814A (ja) 2000-08-15 2001-05-31 スパッタリングターゲット

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US22551800P 2000-08-15 2000-08-15
US60/225,518 2000-08-15

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US10/783,247 Division US20040164420A1 (en) 2000-08-15 2004-02-19 Sputtering target compositions, and methods of inhibiting copper diffusion into a substrate
US10/783,418 Division US20040166693A1 (en) 2000-08-15 2004-02-19 Sputtering target compositions, and methods of inhibiting copper diffusion into a substrate

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002088413A2 (fr) * 2001-05-01 2002-11-07 Honeywell International Inc. Cibles renfermant ti et zr pour depot physique en phase vapeur, et techniques d'utilisation
WO2004009866A2 (fr) * 2002-07-19 2004-01-29 Cabot Corporation Ensemble cible de pulverisation monolithique
CN102000702A (zh) * 2010-12-21 2011-04-06 重庆大学 一种高纯钽溅射靶材的加工工艺
CN114561622A (zh) * 2022-01-14 2022-05-31 西安理工大学 梯度组织Ti-Nb合金薄膜及其制备方法

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* Cited by examiner, † Cited by third party
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CN102094172B (zh) * 2010-12-03 2014-01-01 无锡润鹏复合新材料有限公司 一种TiWN/MoS2复合薄膜的制备方法
JP6274026B2 (ja) 2013-07-31 2018-02-07 三菱マテリアル株式会社 銅合金スパッタリングターゲット及び銅合金スパッタリングターゲットの製造方法
KR20160049255A (ko) * 2014-10-27 2016-05-09 한국생산기술연구원 스퍼터링 타겟용 합금 및 이로 이루어진 스퍼터링 타겟
WO2017164302A1 (fr) 2016-03-25 2017-09-28 Ｊｘ金属株式会社 CIBLE DE PULVÉRISATION EN ALLIAGE Ti-Nb ET PROCÉDÉ POUR LA FABRIQUER
EP3339469A4 (fr) * 2016-03-25 2019-03-27 JX Nippon Mining & Metals Corporation CIBLE DE PULVÉRISATION EN ALLIAGE Ti-Ta ET SON PROCÉDÉ DE PRODUCTION
CN111910101B (zh) * 2020-07-14 2021-08-03 中南大学 一种高纯度高强高导铜基靶材及其制备方法
CN112063891B (zh) * 2020-09-29 2022-02-15 中国科学院金属研究所 一种高热稳定性等轴纳米晶Ti-Zr-Cr合金及其制备方法
CN114480915A (zh) * 2021-12-24 2022-05-13 宝鸡市亨信稀有金属有限公司 钛钨合金靶板的加工工艺
CN114262872B (zh) * 2021-12-31 2024-03-08 北京安泰六九新材料科技有限公司 一种铬铝硼合金复合靶材及其制备方法
CN115522102B (zh) * 2022-10-12 2023-07-18 苏州大学 一种铝合金导电材料及其制备方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2585730A1 (fr) * 1985-08-01 1987-02-06 Centre Nat Rech Scient Procede de depot de metaux en couche mince sur un substrat non metallique, avec depot intermediaire d'hydrures par pulverisation cathodique reactive
GB2202237A (en) * 1987-03-12 1988-09-21 Vac Tec Syst Cathodic arc plasma deposition of hard coatings
US4903117A (en) * 1985-09-11 1990-02-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
JPH08120445A (ja) * 1994-10-17 1996-05-14 Kobe Steel Ltd Ｔｉ−Ａｌ合金ターゲット材の製造方法
JPH1174348A (ja) * 1996-08-16 1999-03-16 Asahi Chem Ind Co Ltd 半導体装置およびその製造方法
US5939788A (en) * 1998-03-11 1999-08-17 Micron Technology, Inc. Copper diffusion barrier, aluminum wetting layer and improved methods for filling openings in silicon substrates with cooper
JP2000012539A (ja) * 1998-06-17 2000-01-14 Nec Corp 半導体装置の製造方法
WO2000013235A1 (fr) * 1998-08-28 2000-03-09 Advanced Technology Materials, Inc. Couches barriere de nitrure-carbure ternaire

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2585730A1 (fr) * 1985-08-01 1987-02-06 Centre Nat Rech Scient Procede de depot de metaux en couche mince sur un substrat non metallique, avec depot intermediaire d'hydrures par pulverisation cathodique reactive
US4903117A (en) * 1985-09-11 1990-02-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
GB2202237A (en) * 1987-03-12 1988-09-21 Vac Tec Syst Cathodic arc plasma deposition of hard coatings
JPH08120445A (ja) * 1994-10-17 1996-05-14 Kobe Steel Ltd Ｔｉ−Ａｌ合金ターゲット材の製造方法
JPH1174348A (ja) * 1996-08-16 1999-03-16 Asahi Chem Ind Co Ltd 半導体装置およびその製造方法
US5939788A (en) * 1998-03-11 1999-08-17 Micron Technology, Inc. Copper diffusion barrier, aluminum wetting layer and improved methods for filling openings in silicon substrates with cooper
JP2000012539A (ja) * 1998-06-17 2000-01-14 Nec Corp 半導体装置の製造方法
WO2000013235A1 (fr) * 1998-08-28 2000-03-09 Advanced Technology Materials, Inc. Couches barriere de nitrure-carbure ternaire

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
KNOTEK O ET AL: "THE STRUCTURE AND COMPOSITION OF TI-ZR-N, TI-AI-ZR-N AND TI-AI-V-N COATINGS", MATERIALS SCIENCE AND ENGINEERING A: STRUCTURAL MATERIALS: PROPERTIES, MICROSTRUCTURE & PROCESSING, LAUSANNE, CH, vol. A105/106, 1988, pages 481 - 488, XP000108123, ISSN: 0921-5093 *
PATENT ABSTRACTS OF JAPAN vol. 1996, no. 09 30 September 1996 (1996-09-30) *
PATENT ABSTRACTS OF JAPAN vol. 1999, no. 08 30 June 1999 (1999-06-30) *
PATENT ABSTRACTS OF JAPAN vol. 2000, no. 04 31 August 2000 (2000-08-31) *
SAKAMOTO I ET AL: "PREPARATION AND MICROSTRUCTURE OF REACTIVELY SPUTTERED TI1-XZRXN FILMS", THIN SOLID FILMS, ELSEVIER-SEQUOIA S.A. LAUSANNE, CH, vol. 228, no. 1 / 2, 15 May 1993 (1993-05-15), pages 169 - 172, XP000381082, ISSN: 0040-6090 *

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002088413A2 (fr) * 2001-05-01 2002-11-07 Honeywell International Inc. Cibles renfermant ti et zr pour depot physique en phase vapeur, et techniques d'utilisation
WO2002088413A3 (fr) * 2001-05-01 2003-01-30 Honeywell Int Inc Cibles renfermant ti et zr pour depot physique en phase vapeur, et techniques d'utilisation
WO2004009866A2 (fr) * 2002-07-19 2004-01-29 Cabot Corporation Ensemble cible de pulverisation monolithique
WO2004009866A3 (fr) * 2002-07-19 2004-03-25 Cabot Corp Ensemble cible de pulverisation monolithique
CN102000702A (zh) * 2010-12-21 2011-04-06 重庆大学 一种高纯钽溅射靶材的加工工艺
CN114561622A (zh) * 2022-01-14 2022-05-31 西安理工大学 梯度组织Ti-Nb合金薄膜及其制备方法
CN114561622B (zh) * 2022-01-14 2024-04-26 西安理工大学 梯度组织Ti-Nb合金薄膜及其制备方法

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