WO2002003767A1 - Circuit a couches metalliques multiples - Google Patents

Circuit a couches metalliques multiples Download PDF

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Publication number
WO2002003767A1
WO2002003767A1 PCT/US2000/030007 US0030007W WO0203767A1 WO 2002003767 A1 WO2002003767 A1 WO 2002003767A1 US 0030007 W US0030007 W US 0030007W WO 0203767 A1 WO0203767 A1 WO 0203767A1
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WO
WIPO (PCT)
Prior art keywords
conductive
layer
forming
composite base
base substrate
Prior art date
Application number
PCT/US2000/030007
Other languages
English (en)
Inventor
Donald K. Larson
David C. Lueneburg
Vicki L. Richmond
Bradley J. Schlader
James R. Shirck
Robert L. W. Smithson
Original Assignee
3M Innovative Properties Company
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 3M Innovative Properties Company filed Critical 3M Innovative Properties Company
Priority to AU2001214479A priority Critical patent/AU2001214479A1/en
Publication of WO2002003767A1 publication Critical patent/WO2002003767A1/fr

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
    • H05K3/424—Plated through-holes or plated via connections characterised by electroplating method by direct electroplating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0038—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material combined with laser drilling through a metal layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0393—Flexible materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/032—Materials
    • H05K2201/0323—Carbon
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09827—Tapered, e.g. tapered hole, via or groove
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0723—Electroplating, e.g. finish plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0779—Treatments involving liquids, e.g. plating, rinsing characterised by the specific liquids involved
    • H05K2203/0786—Using an aqueous solution, e.g. for cleaning or during drilling of holes
    • H05K2203/0793—Aqueous alkaline solution, e.g. for cleaning or etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0055—After-treatment, e.g. cleaning or desmearing of holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer

Definitions

  • the invention disclosed herein relates generally to printed circuits. More specifically, the invention relates to multi-metal layer flexible circuits having microvia constructions.
  • a typical two metal circuit construction includes patterned conductive features on opposing surfaces of a dielectric substrate. Conductive vias electrically connect the conductive features of one surface with one or more conductive feature on the other surface for communicating electrical signals through the dielectric substrate.
  • two metal circuit constructions allow for higher circuit densities per unit area than single metal circuits. Higher circuit densities are desirable in high performance applications.
  • PTH vias are a metallized hole that extends completely through opposing surfaces of a metallized dielectric substrate.
  • PTH vias are typically formed using mechanical drilling, laser ablation or chemical etching techniques followed by a suitable metal deposition process.
  • Blind vias extend through the metal layer on one side of the dielectric substrate and terminate into the metal layer formed on the other side of the dielectric substrate.
  • Blind vias are typically formed using laser drilling or chemical etching techniques.
  • the microvia structure refers to circuits having via capture pads with diameters of 150 micrometers or smaller.
  • the via capture pad diameter is the critical design parameter for determining maximum circuit density rather than the via diameter.
  • the capture pad diameter is the sum of the via diameter, the required fringe or "land" around the via, and the via to pad misalignment tolerance.
  • Substrate distortion and via placement capabilities both of which can be significant, contribute to defining the misalignment tolerance.
  • Capture pad diameters can be reduced by achieving a reduction in the via size, reducing substrate distortion, improving via placement or a combination thereof. Via size can be reduced through the use of sophisticated etching or laser drilling techniques.
  • a printed circuit includes a dielectric substrate having two spaced apart major surfaces.
  • a first conductive layer is formed on each major surface of the dielectric substrate.
  • the dielectric substrate and the first conductive layers define a composite base substrate.
  • a via including a sidewall extends through the composite base substrate.
  • a conductive seed layer is formed on the sidewall of the via.
  • a second conductive layer is formed contiguously on each one of the first conductive layers and on the conductive seed layer.
  • Vias according to the present invention preferably have a microvia construction.
  • a microvia has a capture pad diameter less than 150 micrometers, a maximum via diameter less than 50 micrometers and a sidewall having a via taper angle less than 25 degrees.
  • the composite base substrate preferably has a tensile modulus at least 2 times greater than the tensile modulus of the dielectric substrate.
  • Preferred materials for the dielectric substrate and for the conductive layers are polyimide film and copper, respectively.
  • a process for making a printed circuit includes providing a dielectric substrate having two spaced apart major surfaces and forming a first conductive layer on each one of the major surfaces of the dielectric substrate.
  • the dielectric substrate and the first conductive layers define a composite base substrate.
  • a via including a sidewall is then formed through the composite base substrate and a conductive seed layer is formed on the sidewall of the via.
  • Each first conductive layer is patterned to define a perimeter of a capture pad therein after the via is formed.
  • Each capture pad encompasses the via and the perimeter of each capture pad having a diameter less than 150 micrometers.
  • a contiguous second conductive layer is then formed on each one of the first conductive layers and on the conductive seed layer.
  • Formation of the via preferably includes the step of laser ablating through the composite base substrate. It is advantageous to form the via after forming the first conductive layers on the dielectric substrate.
  • the composite base substrate exhibits significantly less distortion than does the dielectric substrate alone. Accordingly, reducing the distortion of the composite base substrate allows for precise positioning of the vias and capture pads and for reduced size of the capture pads.
  • Formation of the vias through the composite base substrate also allows the first conductive layer to act as a processing mask. The mask results in the vias having a smaller entrance side diameter and a smaller exit side diameter when formed using techniques such as laser ablation and chemical etching.
  • a unique aspect of processes according to the present invention is that laser ablation debris is removed during the step of forming a conductive seed layer on the side wall of the via.
  • a plurality of steps are eliminated by structuring the process such that the web is cleaned during the via seeding operation.
  • the via seeding operation is preferably accomplished using an chemical deposition method such as a direct metallization technique.
  • Formation of the contiguous second conductive layer preferably includes the step of simultaneously electroplating a layer of conductive material on the first conductive layer and on the seed layer of the via. •
  • a flexible circuit in a further embodiment of the present invention, includes a flexible dielectric substrate having two spaced apart major surfaces.
  • a first conductive layer is formed on each major surface of the dielectric substrate.
  • the first conductive layers and the dielectric substrate define a composite base substrate having a tensile modulus at least 2 times greater than the tensile modulus of the dielectric substrate.
  • a via including a sidewall extends through the composite base substrate.
  • the via defines edge portions in the composite base substrate.
  • the edge portions of the via have respective diameters less than 50 micrometers and define a via taper angle less than 25 degrees.
  • Each first conductive layer is patterned to define a perimeter of a capture pad encompassing the via. The perimeter of each capture pad has a diameter less than 150 micrometers.
  • a conductive seed layer is formed on the sidewall of the via.
  • a second conductive layer is formed contiguously on each first conductive layer and on the seed layer.
  • composite base substrate refers to a dielectric substrate having continuous conductive layers on at least one major surface thereof.
  • via refers to an aperture extending through the dielectric substrate and at least one conductive layer of the composite base substrate.
  • direct metallization process refers to a chemical process of forming a coating of electrically conductive material directly on a surface of a dielectric substrate, a layer of conductive material or both.
  • contiguous and “contiguously” refers to a physically and electrically continuous manner in which a conductive layer extends from one major surface of a dielectric substrate to another major surface thereof through a via.
  • laser ablation debris refers to by-product portions of the dielectric substrate and conductive layers that are produced during the laser ablation process and that are deposited on a surface of the composite base substrate.
  • edge portion refers to a perimeter edge of the via at a respective surface of the composite base substrate.
  • sidewall via taper angle refers to the angle of the sidewall of the via relative to a reference axis extending perpendicular to the major surfaces of the composite base substrate.
  • linear of sight refers to a surface of a feature being visible from a particular position, such as, for example, the position of a plating material target in a sputtering deposition process.
  • Fig. 1 is a fragmentary plan view illustrating an embodiment of a circuit assembly including a plated through hole via having an open configuration.
  • Fig. 2 is a cross-sectional view taken along the line 2-2 in Figure 1.
  • Fig. 3 is a cross-sectional view illustrating an embodiment of a plated through hole via having a closed configuration.
  • Figs. 4A-4J are views illustrating an embodiment of a process for fabricating circuits according to the present invention.
  • Circuit constructions according to the present invention provide a superior multi-metal layer circuit construction relative to conventional circuit constructions.
  • Methods for fabricating circuits according to the present invention utilize a two-side metallized dielectric substrate.
  • the substrate is metallized with a seed layer of a conductive material such as copper.
  • the metallized dielectric substrate is laser drilled to generate the desired pattern of vias.
  • the metallized substrate exhibits greater resistance to distortion resulting from applied web tension and thermally induced stresses. Accordingly, microvias can be readily formed using such a substrate.
  • the circuit assembly 10 includes a dielectric substrate 12 having a thickness t, a first major surface 12a and a second major surface 12b.
  • a preferred material for the dielectric substrate 12 is a polyimide film such as that sold by DuPont under the tradename KAPTON E.
  • Other suitable commercially available flexible polymeric films include, for example, UpilexTM offered by Ube and ApicalTM offered by Kaneka.
  • the first major surface 12a extends generally parallel to the second major surface 12b.
  • a first conductive layer 14 is formed on each one of the major surfaces 12a, 12b.
  • the dielectric substrate 12 and the first conductive layers 14 define a composite base substrate 16, Fig. 2.
  • each first conductive layer 14 preferably includes a base sputter layer, such as a layer of chromium, and a flash plate layer, such as a layer of copper.
  • This first conductive layer 14 serves as an adhesive tie layer between the dielectric substrate 12 and subsequently formed conductive layers and as a plating bus for subsequently formed pattered conductive features.
  • the first conductive layer 14 also adds enhanced stability of the composite substrate 16.
  • the first conductive layer 14 can also be formed by other techniques such as vacuum metallization or electron beam evaporation.
  • a via 18 extends through the composite base substrate 16.
  • the via 18 includes a sidewall 20 that extends through the composite base substrate 16.
  • a seed layer 22 of electrically conductive material is formed on the sidewall 20 of the via 18.
  • First and second edge portions 23 a, 23b of the via 18 are defined at the intersections of the sidewall 20 and the first conductive layers 14.
  • the first conductive layers 14 are patterned to define a perimeter of a capture pad 24 that encompasses the corresponding edge portions 23a, 23b and to define a perimeter of at least one trace 26 extending from the capture pad 24.
  • a second conductive layer 28 is formed in a contiguous manner on the first conductive layers 14 and on the seed layer 22.
  • the second conductive layer 28 is plated such that the via 18 has an open configuration wherein with an opening extends through the via 18.
  • the via 18 illustrated in Figs. 1 and 2 has a tapered sidewall profile.
  • Vias having a tapered sidewall profile are typically produced using through hole fabrication methods such as, for example, laser ablation, laser drilling and chemical etching.
  • through hole fabrication methods such as, for example, laser ablation, laser drilling and chemical etching.
  • each one of these through hole fabrication methods produces a via 18 wherein the first edge portion 23 a corresponding to an entry side of the through hole defines a first diameter Dl and wherein the second edge portion 23b corresponding to an exit side of the through hole defines a second diameter D2.
  • the first diameter Dl is greater than the second diameter D2.
  • the first diameter Dl and the second diameter D2 define a via taper angle A.
  • a via taper angle A of between 0 degrees and 60 degrees can be produced.
  • the via taper angle A is defined herein according to the following equation.
  • a via having a first diameter Dl of 50 microns, a second diameter D2 of 25 microns and a dielectric thickness t of 50 micros has a via taper angle A of 15 degrees.
  • An embodiment of a circuit assembly 110 is illustrated in Fig. 3.
  • the circuit assembly 110 includes a dielectric substrate 112 having a via 118 extending therethrough.
  • a first conductive layer 114 is formed on major surfaces 112a, 112b of the dielectric substrate 112.
  • the dielectric substrate 112 and the first conductive layers 114 define a composite base substrate 116.
  • the via 118 has a sidewall 120 that extends in a direction substantially perpendicular to the major surfaces 112a, 112b of dielectric substrate 112.
  • a seed layer 122 of electrically conductive material is formed on the sidewall 120 of the via 118.
  • Typical through hole fabrication methods for forming non-tapered vias include, but are not limited to, mechanical punching and mechanical drilling.
  • the via 118 has a closed configuration, meaning that the through hole has been plated closed. This type of configuration is useful for preventing solder from draining from one side of a circuit to the another side thereof.
  • the dimensions of the sidewall of a via and the thickness of the conductive layers dictate whether the via will have an open configuration (Fig. 1) or a closed configuration (Fig. 3). Decreasing the diameter of the via and increasing the thickness of the first and the second conductive layers will yield a closed via configuration. Increasing the diameter of the via or reducing the thickness of the first and the second conductive layers will yield an open via configuration.
  • a dielectric substrate 200 has a base layer 202 formed on a first major surface 200a thereof and on a second major surface 200b thereof, Fig. 4A. It is preferred that the base layer 202 includes a tie layer, such as a layer of chromium, formed directly on the dielectric substrate 200 and a conductive seed layer, such as a layer of copper, formed on the tie layer.
  • the base layers 202 enable plating and enhanced adhesion of subsequently formed conductive layers thereon.
  • the tie layer serves as a diffusion barrier between the dielectric substrate and the conductive seed layer.
  • Sputtering is a preferred technique for forming the base layer 202.
  • Other techniques for forming the base layer 202 include other chemical deposition techniques such as chemical vapor deposition.
  • the base layer 202 is formed on the first surface 200a and then on the second surface 200b. However, depending on the specific application and processing equipment, other sequences for forming the base layers 202 may be applicable.
  • the dielectric substrate 200 is subjected to an infrared preheating operation to remove moisture.
  • the first and second surfaces 200a, 200b of the dielectric substrate 200 are exposed to an oxygen plasma for preconditioning the surfaces 200a, 200b.
  • the first surface 200a of the dielectric substrate 200 is then subjected to a tie layer sputter operation and then to a seed layer sputter operation, forming the base layer 202 on the first surface 200a.
  • the same operations are repeated on the second surface 200b to form the base layer 202 thereon.
  • a typical thickness for the tie layer and for the seed layer on the first surface 200a is 70 angstroms and 150 nm, respectively.
  • the plasma and sputter energies may be maintained at levels about 10% lower than those used on the first surface 200a, reducing heating and distortion of the dielectric substrate 200.
  • a typical thickness for the tie layer and for the seed layer on the second surface 200b of the dielectric substrate 200 is 70 angstroms and 130 nm, respectively.
  • a plurality of suitable plasma and sputtering processes and process equipment are known in the circuit fabricating industry. Preferred process equipment will have a plurality of deposition zones such that the tie layer and the seed layer can be formed in a single pass through the process equipment.
  • a flash plate layer 204 is formed on each one of the base layers 202.
  • Each base layer 202 and the adjacent flash plate layer 204 define a first conductive layer 205.
  • Electroplating is a preferred plating technique for forming the flash plate layer 204.
  • the flash plate layers 204 are preferably formed simultaneously to reduce the total number of processing steps.
  • a target thickness for each flash plate layer 204 is 3 ⁇ m. However, the thickness of the flash plate layers 204 may vary depending on the specific application.
  • a plurality of suitable electroplating processes and process equipment are known in the circuit fabricating industry.
  • the dielectric substrate 200, the base layers 202 and the flash plate layers 204 define a composite base substrate 206, Fig. 4C.
  • the composite base substrate 206 preferably exhibits a composite tensile modulus at least 2 times greater than the tensile modulus of the dielectric substrate 200. By achieving such a composite tensile modulus, distortion of the composite base substrate 206 is substantially reduced during subsequent processing operations.
  • one or more vias 208 are formed through the composite base substrate 206, Fig. 4C.
  • Commercially available methods for forming the one or more vias 208 include methods such as laser ablation, laser drilling, mechanical drilling, mechanical punching and chemical milling. Laser ablation is a preferred method of forming the one or more vias 208.
  • a commercially available laser system is used for forming the one or more vias 208.
  • a suitable laser system is offered by Electro Scientific Industries, Incorporated (ESI) under the model number 5200.
  • ESI Electro Scientific Industries, Incorporated
  • U.S. Patent number 5,593,606 issued to ESI discloses a suitable method for using a laser to laser ablate apertures such as vias in materials such as the dielectric substrate 200.
  • the one or more vias 208 are formed through the composite base substrate 206 from an entry side 206a to an exit side 206b, Fig. 4C. Formation of the one or more vias 208 through the composite base substrate 206 is known to deposit laser ablation debris 210 on the entry side 206a of the composite base substrate 206 and to form a rim portion 212 on the exit side 206b of the composite base substrate 206.
  • the laser ablation debris 210 and rim portion 212 are preferably removed from the composite base substrate 206 during the following process steps.
  • a seed layer 214 is formed on a sidewall 216 of each one of the vias 208, Fig. 4D.
  • a deposition process known as "direct metallization" is a preferred process for forming the seed layer 214.
  • Direct metallization is a process technique in which a non-conductive surface can be directly electroplated without first having to form a conductive layer thereon. Direct metallization involves coating of a surface with a conductive material, allowing the surface to be subsequently electroplated. The direct metallization process may be facilitated using commercially available process equipment from suppliers such as Finishing Services, Western Technology Associates, Schmid and Atotech.
  • Suitable commercially available direct metallization process and chemistry include carbon-based systems such as those offered by Electrochemicals Incorporated under the tradename Shadow Direct Metallization, by McDermid under the tradename BlackHole and by Shipley-LeaRonal under the tradename Graphite 2000; Pd-Colloid chemistries such as those offered by Atotech under the tradename Neopact and by Solution Technology Systems under the designation HN504; and conductive polymer systems such as that offered by Atotech under the tradename Compact CP. Any of these direct metallization processes and chemistries or suitable known chemical copper deposition techniques can be used to form the seed layer on the sidewall 216 of the one or more vias 208.
  • a key benefit of direct metallization processes is the ability to form a conductive seed layer on vias having high aspect ratios because this type of metallization process is not line-of-sight limited. Because direct metallization processes are predominately based on wetting or viscosity characteristics of the direct metallization solution, forming a seed layer on difficult to reach locations is directly related to the ability to expose such locations to the direct metallization plating solutions. Providing that the proper chemistry of the plating solution is maintained, the plated layer of material resulting from the direct metallization process will be relatively uniform on all exposed surfaces of the article being plated.
  • Another key benefit of direct metallization is that the laser ablation debris 210, Fig. 4C, is removed during the direct metallization process.
  • Metallization techniques such as sputtering and evaporation are line-of-sight.
  • the uniformity of the resulting layer of material is dependent on the orientation of the substrate and features therein.
  • the relative coating rate between the side walls of a via and the flat surface of a substrate is related to two ratios: (1) via diameter/via depth and (2) via diameter/molecular mean free path. If the mean free path is much less that of the diameter, then the resulting coating will be uniform. If the mean free path is greater than or slightly equal to the diameter, then the coating rate is a strong function of via depth. In most vacuum processes, the mean free path is typically greater than 100 micrometers.
  • An embodiment of a direct metallization process includes a first operation of conditioning the composite base substrate 206 in a mildly alkaline solution.
  • the alkaline solution cleans and conditions the substrate surfaces 206, including sidewall 216. Loosely adhered portions of the laser ablation debris 210 are removed during conditioning of the composite base substrate 206.
  • the conditioning agents present in the alkaline solution form strong cationic charges on the exposed surfaces of the composite base substrate 206. These charges remain intact through the conditioner operation and through subsequent rinse, allowing for the attraction and attachment of seeding material.
  • the direct metallization process uses a metallization solution comprised of a mildly alkaline conductive colloid dispersion formulated from bound graphite. Graphite, together with an organic binder exists as an anionic charged particle which is very attracted to the cationic charge left on the sidewall 216 of the via 208 during the conditioner step.
  • the composite base substrate 206 is immersed in the metallization solution such that the seed layer 214 is formed on the sidewall 216 of each via 208, Fig. 4D, and on the exposed portions of the flash plate layers 204.
  • the composite base substrate 206 is subjected to an acidic fixer solution which removes excess graphite colloid. Exposure to the fixer solution promotes better adhesion from the remaining, tightly bound seed layer 214.
  • the fixer solution acts to neutralize and crosslink the carboxyl groups on the binder, causing the graphite particles to flocculate onto the sidewall 216 and reducing the amount of graphite that turns to precipitate.
  • a rinse water step directly after exposure to the fixer solution removes any graphite precipitate.
  • the seed layer 214 is then dried to prevent it from being washed off in subsequent operations. Heat applied during the drying operation completes the crosslinking of the seed layer 214.
  • the portions (not shown) of the seed layer 214 deposited on the flash plate layers 204 are removed during a subsequent micro-etch operation.
  • the seed layer 214 on the exposed portions of the flash plate layers 204 is removed using a persulfate etchant. If the flash plate layer 204 is made of copper, the persulfate penetrates the seed layer 214 on the flash plate layer 204 and begins to etch the copper away, carrying the graphite with it. The persulfate does not react with polymeric substrates. Accordingly, the seed layer 214 remains intact on the sidewall 216 of each via 208. Well adhered portions of the laser ablation debris 210, Fig. 4C, are removed during micro etching operation.
  • each photoresist layer 218 is preferably an aqueous processible, dry-film, negative- acting photoresist applied using heat and pressure.
  • the thickness of each photoresist layer 218 is typically between 15 micrometers and 50 micrometers.
  • Suitable photoresists for each photoresist layer 218 include, for example, photoresists offered by MacDermid Incorporated under the series designations SF, CF, and MP. Specific examples include MacDermid SF310 and MP413 photoresists.
  • each photomask 220 includes a pattern that is registered with respective portions of the corresponding flash plate layer 204 and dielectric substrate 200.
  • Commercially available equipment such as that available from Perkin Elmer-ORC, is used to register each photomask 220 with respective portions of the corresponding flash plate layer 204 and dielectric substrate 200.
  • the photoresist layers 218 are then exposed to energy from a suitable source for exposing a desired image in the photoresist layer 206.
  • An ultraviolet light source 222 is commonly used for exposing images in photoimageable photoresists, such as the photoresist layers 218.
  • Other commercially available exposure equipment is offered by companies such as Tamarac, Ushio, and Siposa SA.
  • the photomasks 220 include patterned chrome or emulsion coated portions for blocking the transmission of energy to specific areas of the photoresist layers 218, allowing energy to pass through and react with the photoresist layer 218 in unblocked areas.
  • the photo resist layers 218 are imaged simultaneously, reducing the number of process steps and improving registration. Photomasks of various constructions are commercially available.
  • each photoresist layer 218 is an aqueous negative-acting material
  • the areas of each photoresist layer 218 that were not exposed to energy from the light source 222 are developed out (removed) during the developing step.
  • the developing step includes applying a dilute aqueous solution, such as a 0.5% - 1.5% sodium or potassium carbonate solution, to the photoresist until the desired patterns are obtained in the photoresist layers 218.
  • the developing step is typically performed using commercially available equipment and solutions.
  • the developing step results in a desired circuit pattern in the photoresist layer 206, Fig. 4G.
  • the pattern includes portions exposing the flash plate layers 204 and the vias 208.
  • each via 208 and the portions of the flash plated layer 204 exposed through the photoresist layers 218 are simultaneously plated with a layer of conductive material, Fig. 4H.
  • the layer of conductive material forms a contiguous second conductive layer 224 on the first conductive layers 205 and on the seed layer 214 of each via 208.
  • a typical combined thickness for the first and second conductive layers 205, 224 is 15 ⁇ m. However, the specific thickness may be different for a particular circuit design.
  • a key aspect of the present invention is that the second conductive layer 224 is simultaneously formed on the first conductive layers 205 and on the seed layer 214 of each via 208. Simultaneously plating of the second conductive layer 224 eliminates additional process steps that are required with a multiple pass plating operation. Furthermore, the resulting contiguous second conductive layer 224 provides improved resistance to corrosion and stress related failures.
  • a suitable method for stripping the photoresist layers 218 comprises exposing the photoresist layers 218 to a solution (typically 2 - 10%) of an alkaline metal hydroxide at from 20°C to 80°C, preferably from 20°C to 60°C. Stripping the photoresist layers 218 exposes portions of the first conductive layer 205 that were previously concealed by the photoresist layers 218.
  • first conductive layer 205 that were previously concealed by the photoresist layers 218 are etched away to form electrically isolated capture pad portions 226 encompassing each via 208 and traces 228, Fig. 4J. Suitable methods are known in the art for etching the first conductive layers 205.
  • the via and circuit are formed after the dielectric has been dimensionally stabilized through a metallization process.
  • the metallization process enables superior via to capture pad alignment. This improved alignment in conjunction with the small diameter vias produced using a laser process, such as laser ablation, results in reduced capture pad diameters and higher circuits densities.
  • simultaneous two-sided plating of the circuitry and via is used to provide a via construction with significantly reduced corrosion and stress related reliability concerns.
  • a further advantage is a reduction in the number of processing steps that are required. Conventional methods for producing two side metallized substrates with plated vias require at least 2 times the number of processing steps utilized for a single metal circuit.
  • a process is achieved that uses only 1.5 times the number of steps utilized in a single metal circuit.
  • Process techniques such as simultaneous two-side patterning, direct metallization of the via and simultaneous plating of all conductive features of a circuit results in a reduced number of process steps.
  • Processes according to the present invention enable the fabrication of lower cost two metal layer circuits that offer enhanced reliability, reduced capture pad diameter and higher via density.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

L'invention concerne un circuit (10) comprenant un substrat diélectrique (12) possédant deux surfaces principales espacées (12a, 12b). Une première couche conductrice (14) est formée sur chaque surface principale (12a, 12b) du substrat diélectrique (12). Les premières couche conductrices (14) et le substrat diélectrique (12) définissent un substrat de base composite (16) dont le module d'élasticité en tension est au moins deux fois supérieur à celui du substrat diélectrique (12). Un trou d'interconnexion (18) comprenant une paroi latérale (20) traverse le substrat de base composite (16). Le trou d'interconnexion (18) définit des bords (23a, 23b) dans le substrat de base composite (16). Les bords (23a, 23b) du trou d'interconnexion (18) ont des diamètres respectifs inférieurs à 50 micromètres et définissent un angle conique (A) de trou d'interconnexion inférieur à 25 degrés. Chaque première couche conductrice (14) est conçue pour définir le périmètre d'une plaquette de capture (24) comprenant le trou d'interconnexion (18). Le périmètre de chaque plaquette de capture (24) possède un diamètre inférieur à 150 micromètres. Une couche germe conductrice (22) est formée sur la paroi latérale (20) du trou d'interconnexion (18). Une seconde couche conductrice (28) est formée de façon contiguë sur chaque première couche conductrice (14) et sur la couche germe (22).
PCT/US2000/030007 2000-06-29 2000-10-31 Circuit a couches metalliques multiples WO2002003767A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001214479A AU2001214479A1 (en) 2000-06-29 2000-10-31 Multi-metal layer circuit

Applications Claiming Priority (2)

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US60714900A 2000-06-29 2000-06-29
US09/607,149 2000-06-29

Publications (1)

Publication Number Publication Date
WO2002003767A1 true WO2002003767A1 (fr) 2002-01-10

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AU (1) AU2001214479A1 (fr)
WO (1) WO2002003767A1 (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10302922A1 (de) * 2003-01-24 2004-07-29 Conti Temic Microelectronic Gmbh Elektronische Baugruppe
US7012017B2 (en) 2004-01-29 2006-03-14 3M Innovative Properties Company Partially etched dielectric film with conductive features
CN100562214C (zh) * 2005-07-02 2009-11-18 鸿富锦精密工业（深圳）有限公司 具有改良过孔的印刷电路板
CN113767716A (zh) * 2019-05-06 2021-12-07 3M创新有限公司 图案化导电制品
CN114787757A (zh) * 2020-09-02 2022-07-22 京东方科技集团股份有限公司 柔性电路板及其制备方法、触控面板及其制备方法

Citations (4)

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Publication number Priority date Publication date Assignee Title
EP0257737A2 (fr) * 1986-06-09 1988-03-02 Minnesota Mining And Manufacturing Company Précurseur de circuit imprimé
US5108553A (en) * 1989-04-04 1992-04-28 Olin Corporation G-tab manufacturing process and the product produced thereby
JPH1197491A (ja) * 1997-09-24 1999-04-09 Shindo Denshi Kogyo Kk 両面テープキャリアの製造方法
US6039889A (en) * 1999-01-12 2000-03-21 Fujitsu Limited Process flows for formation of fine structure layer pairs on flexible films

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0257737A2 (fr) * 1986-06-09 1988-03-02 Minnesota Mining And Manufacturing Company Précurseur de circuit imprimé
US5108553A (en) * 1989-04-04 1992-04-28 Olin Corporation G-tab manufacturing process and the product produced thereby
JPH1197491A (ja) * 1997-09-24 1999-04-09 Shindo Denshi Kogyo Kk 両面テープキャリアの製造方法
US6039889A (en) * 1999-01-12 2000-03-21 Fujitsu Limited Process flows for formation of fine structure layer pairs on flexible films

Non-Patent Citations (3)

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Title
"COMBINED LASER PROCESSING OF VIAS AND CIRCUITRY IN FLEX-CIRCUITS", IBM TECHNICAL DISCLOSURE BULLETIN,US,IBM CORP. NEW YORK, vol. 38, no. 5, 1 May 1995 (1995-05-01), pages 607 - 608, XP000519699, ISSN: 0018-8689 *
"STRUCTURING OF LAMINATED CU-POLYIMIDE FILMS VIA LASER ABLATION", IBM TECHNICAL DISCLOSURE BULLETIN,US,IBM CORP. NEW YORK, vol. 37, no. 8, 1 August 1994 (1994-08-01), pages 481, XP000456496, ISSN: 0018-8689 *
PATENT ABSTRACTS OF JAPAN vol. 1999, no. 09 30 July 1999 (1999-07-30) *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10302922A1 (de) * 2003-01-24 2004-07-29 Conti Temic Microelectronic Gmbh Elektronische Baugruppe
US7012017B2 (en) 2004-01-29 2006-03-14 3M Innovative Properties Company Partially etched dielectric film with conductive features
CN100562214C (zh) * 2005-07-02 2009-11-18 鸿富锦精密工业（深圳）有限公司 具有改良过孔的印刷电路板
CN113767716A (zh) * 2019-05-06 2021-12-07 3M创新有限公司 图案化导电制品
CN114787757A (zh) * 2020-09-02 2022-07-22 京东方科技集团股份有限公司 柔性电路板及其制备方法、触控面板及其制备方法

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