WO2001099182A2 - Barriere de diffusion in situ et metallisation au cuivre metallisation pour obtenir des dispositifs a semi-conducteurs d'une plus grande fiabilite - Google Patents

Barriere de diffusion in situ et metallisation au cuivre metallisation pour obtenir des dispositifs a semi-conducteurs d'une plus grande fiabilite Download PDF

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Publication number
WO2001099182A2
WO2001099182A2 PCT/US2001/019820 US0119820W WO0199182A2 WO 2001099182 A2 WO2001099182 A2 WO 2001099182A2 US 0119820 W US0119820 W US 0119820W WO 0199182 A2 WO0199182 A2 WO 0199182A2
Authority
WO
WIPO (PCT)
Prior art keywords
diffusion barrier
trenches
metal
recited
depositing
Prior art date
Application number
PCT/US2001/019820
Other languages
English (en)
Other versions
WO2001099182A3 (fr
Inventor
Stefan Weber
Alexander Ruf
Chenting Lin
Andreas Knorr
Original Assignee
Infineon Technologies North America Corp.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies North America Corp. filed Critical Infineon Technologies North America Corp.
Priority to KR1020027017434A priority Critical patent/KR100788064B1/ko
Priority to EP01946617A priority patent/EP1292977A2/fr
Publication of WO2001099182A2 publication Critical patent/WO2001099182A2/fr
Publication of WO2001099182A3 publication Critical patent/WO2001099182A3/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28568—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising transition metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures

Definitions

  • This disclosure relates to semiconductor fabrication and more particularly, to a method for reducing failures while employing copper metallizations in semiconductor devices.
  • Metal layers for semiconductors are electrically isolated from other metal lines and layers by employing dielectric layers.
  • a dielectric layer is deposited on a semiconductor device and then is patterned to form trenches or holes therein. The trenches or hole's are then filled with metal to provide interlevel connections or same level connections to various electrical components .
  • a method for forming metallizations for semiconductor devices includes forming trenches in a dielectric layer, depositing a single layer diffusion barrier in the trenches, and without an air-brake, depositing a seed layer of metal on the surface of the diffusion barrier.
  • the trenches are then filled with metal.
  • the metal adheres to the seed layer, which adheres to the diffusion barrier to provide many improvements to electrical characteristics as well as to reduce failures in the semiconductor devices.
  • the present invention avoids this air-brake and overcomes, among other things, problems due to adhesion problems.
  • Another method for forming metallizations for semiconductor devices includes the steps of forming trenches in a dielectric, depositing a single layer diffusion barrier in the trenches, without an air-brake, depositing a seed layer of metal on the surface of the diffusion barrier, filling the trenches with metal, and planarizing a top surface down to the dielectric layer in a single polishing step to remove the metal and the diffusion barrier.
  • the step of without an air-brake, depositing a seed layer preferably includes the step of without an air-brake, chemical vapor depositing a seed layer of metal on the surface of the diffusion barrier.
  • the steps of depositing a single layer diffusion barrier in the trenches and without an airbrake, depositing a seed layer of metal are performed in a same processing chamber.
  • the seed layer and the metal preferably include copper.
  • the trenches may include dual damascene trenches.
  • the diffusion barrier may include one of Ti, TiN, WN, or TaN.
  • the diffusion barrier is preferably less than or equal to 5 nm.
  • the step of filling the trenches with metal may include the step of electroplating the metal to fill the trenches with the metal .
  • the step of depositing a single layer diffusion barrier may include the step of chemical vapor depositing the diffusion barrier.
  • the step of without an air-brake, depositing a seed layer may include the step of without an air-brake, ionized sputtering a seed layer of metal on the surface of the diffusion barrier.
  • the step of filling the trenches with metal may include the step of sputtering to fill the trenches with the metal.
  • FIG. 1 is a cross-sectional view of a dual damascene trench formed in a dielectric layer for applying the present invention
  • FIG. 2 is a cross-sectional view of a via, trench or single damascene structure formed in a dielectric layer for applying the present invention
  • FIG. 3 is a cross-sectional view of the dual damascene trench of FIG. 1, with a single layer diffusion barrier formed therein in accordance with the present invention
  • FIG. 4 is a cross-sectional view of the trench of FIG. 2, with a single layer diffusion barrier formed therein in accordance with the present invention
  • FIG. 5 is a cross-sectional view of the dual damascene trench of FIG. 3, with an in-situ seed layer of metal formed on the diffusion barrier in accordance with the present invention
  • FIG. 6 is a cross-sectional view of the trench of FIG. 4, with an in-situ seed layer of metal formed on the diffusion barrier in accordance with the present invention
  • FIG. 8 is a cross-sectional view of the trench of FIG. 6, filled with metal in accordance with the present invention.
  • FIG. 9 is a cross-sectional view of the dual damascene trench of FIG. 7, planarized down to the dielectric layer in a single step polish process in accordance with the present invention.
  • dielectric layer 104 may also be patterned using a resist layer 114 to etch holes 107 which may include vias, contact holes or single damascene structures.
  • etch holes 107 may include vias, contact holes or single damascene structures.
  • the structures shown in FIGS. 1 and 2 are illustrative only and should not be construed as limiting the invention.
  • Seed layer 118 provides nucleation sites on diffusion barrier 116 such that when the structures are filled better adhesion is provided and voids are eliminated or significantly reduced.
  • Seed layer 118 may be formed by a physical vapor deposition (PVD) process, such as, an ionized sputtering process or by a CVD process. The CVD process is preferred. Seed layer 118 need only be about 0.03 nm in thickness although other thicknesses may also be useful .
  • PVD physical vapor deposition
  • copper metallizations may be used instead of aluminum (although aluminum sees improvements as well if used) which improves conductivity of metal lines and contacts;

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention porte sur un procédé permettant de réaliser des métallisations pour des dispositifs à semi-conducteurs et consistant à former des tranchées (107) dans une couche de diélectrique (104), déposer une barrière de diffusion unique (116) dans les tranchées, et sans coupure d'air, déposer une métallique à germe monocristallin (118) sur la surface de la barrière de diffusion. Les tranchées sont ensuite remplies de métal (120). Le métal adhère à la couche à germe monocristallin qui adhère elle-même à la barrière de diffusion, ce qui permet d'améliorer considérablement les caractéristiques électriques et de réduire les pannes des dispositifs à semi-conducteurs.
PCT/US2001/019820 2000-06-21 2001-06-21 Barriere de diffusion in situ et metallisation au cuivre metallisation pour obtenir des dispositifs a semi-conducteurs d'une plus grande fiabilite WO2001099182A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1020027017434A KR100788064B1 (ko) 2000-06-21 2001-06-21 반도체 디바이스에 대한 금속화를 형성하는 방법
EP01946617A EP1292977A2 (fr) 2000-06-21 2001-06-21 Barriere de diffusion in situ et metallisation au cuivre metallisation pour obtenir des dispositifs a semi-conducteurs d'une plus grande fiabilite

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US59837500A 2000-06-21 2000-06-21
US09/598,375 2000-06-21

Publications (2)

Publication Number Publication Date
WO2001099182A2 true WO2001099182A2 (fr) 2001-12-27
WO2001099182A3 WO2001099182A3 (fr) 2002-04-18

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PCT/US2001/019820 WO2001099182A2 (fr) 2000-06-21 2001-06-21 Barriere de diffusion in situ et metallisation au cuivre metallisation pour obtenir des dispositifs a semi-conducteurs d'une plus grande fiabilite

Country Status (4)

Country Link
EP (1) EP1292977A2 (fr)
KR (1) KR100788064B1 (fr)
TW (1) TW512490B (fr)
WO (1) WO2001099182A2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114477779A (zh) * 2021-12-30 2022-05-13 厦门云天半导体科技有限公司 一种基于异质键合的多层玻璃基板工艺和结构

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5770520A (en) * 1996-12-05 1998-06-23 Lsi Logic Corporation Method of making a barrier layer for via or contact opening of integrated circuit structure
EP0878834A2 (fr) * 1997-05-12 1998-11-18 Motorola, Inc. Prévention du dépÔt électrolytique sur les surfaces exposées de la bordure d'une tranche de semi-conducteur
US5918149A (en) * 1996-02-16 1999-06-29 Advanced Micro Devices, Inc. Deposition of a conductor in a via hole or trench
US6037258A (en) * 1999-05-07 2000-03-14 Taiwan Semiconductor Manufacturing Company Method of forming a smooth copper seed layer for a copper damascene structure
WO2000021120A1 (fr) * 1998-10-03 2000-04-13 Applied Materials, Inc. Procede et appareil pour deposer un materiau sur une plaquette de semi-conducteur au moyen d'une chambre de transition faisant partie d'un systeme de traitement de plaquettes de semi-conducteur a chambres multiples
US6174811B1 (en) * 1998-12-02 2001-01-16 Applied Materials, Inc. Integrated deposition process for copper metallization

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5918149A (en) * 1996-02-16 1999-06-29 Advanced Micro Devices, Inc. Deposition of a conductor in a via hole or trench
US5770520A (en) * 1996-12-05 1998-06-23 Lsi Logic Corporation Method of making a barrier layer for via or contact opening of integrated circuit structure
EP0878834A2 (fr) * 1997-05-12 1998-11-18 Motorola, Inc. Prévention du dépÔt électrolytique sur les surfaces exposées de la bordure d'une tranche de semi-conducteur
WO2000021120A1 (fr) * 1998-10-03 2000-04-13 Applied Materials, Inc. Procede et appareil pour deposer un materiau sur une plaquette de semi-conducteur au moyen d'une chambre de transition faisant partie d'un systeme de traitement de plaquettes de semi-conducteur a chambres multiples
US6174811B1 (en) * 1998-12-02 2001-01-16 Applied Materials, Inc. Integrated deposition process for copper metallization
US6037258A (en) * 1999-05-07 2000-03-14 Taiwan Semiconductor Manufacturing Company Method of forming a smooth copper seed layer for a copper damascene structure

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
"Cluster MOCVD for copper interconnects" EUROPEAN SEMICONDUCTOR, NOV. 1998, ANGEL PUBLISHING, UK, vol. 20, no. 11, pages 31, 33-34, XP008000187 ISSN: 0265-6027 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114477779A (zh) * 2021-12-30 2022-05-13 厦门云天半导体科技有限公司 一种基于异质键合的多层玻璃基板工艺和结构
CN114477779B (zh) * 2021-12-30 2023-09-08 厦门云天半导体科技有限公司 一种基于异质键合的多层玻璃基板工艺和结构

Also Published As

Publication number Publication date
TW512490B (en) 2002-12-01
KR100788064B1 (ko) 2007-12-21
WO2001099182A3 (fr) 2002-04-18
KR20030020304A (ko) 2003-03-08
EP1292977A2 (fr) 2003-03-19

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