EP1292977A2 - Barriere de diffusion in situ et metallisation au cuivre metallisation pour obtenir des dispositifs a semi-conducteurs d'une plus grande fiabilite - Google Patents

Barriere de diffusion in situ et metallisation au cuivre metallisation pour obtenir des dispositifs a semi-conducteurs d'une plus grande fiabilite

Info

Publication number
EP1292977A2
EP1292977A2 EP01946617A EP01946617A EP1292977A2 EP 1292977 A2 EP1292977 A2 EP 1292977A2 EP 01946617 A EP01946617 A EP 01946617A EP 01946617 A EP01946617 A EP 01946617A EP 1292977 A2 EP1292977 A2 EP 1292977A2
Authority
EP
European Patent Office
Prior art keywords
diffusion barrier
trenches
metal
recited
depositing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01946617A
Other languages
German (de)
English (en)
Inventor
Stefan Weber
Alexander Ruf
Chenting Lin
Andreas Knorr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Polaris Innovations Ltd
Original Assignee
Infineon Technologies AG
Infineon Technologies North America Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG, Infineon Technologies North America Corp filed Critical Infineon Technologies AG
Publication of EP1292977A2 publication Critical patent/EP1292977A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28568—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising transition metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures

Definitions

  • This disclosure relates to semiconductor fabrication and more particularly, to a method for reducing failures while employing copper metallizations in semiconductor devices.
  • Metal layers for semiconductors are electrically isolated from other metal lines and layers by employing dielectric layers.
  • a dielectric layer is deposited on a semiconductor device and then is patterned to form trenches or holes therein. The trenches or hole's are then filled with metal to provide interlevel connections or same level connections to various electrical components .
  • Metal lines formed in such trenches typically include Aluminum.
  • Aluminum although sufficient for many applications, other materials, such as copper, provide higher conductivity. Further, for logic applications, aluminum may be unsuitable especially in smaller groundrule designs.
  • Copper also has several shortcomings, however.
  • the dielectric layers employed for isolating copper often include oxygen, for example, silicon oxides. Electrical properties of copper degrade significantly when oxidized. Diffusion barriers employed between the dielectric layer and the copper, especially for smaller linewidths, reduce the cross-sectional area of the copper in the trench since these diffusion barrier layers occupy space. This increases the resistance of the metal line for a given linewidth.
  • a method for forming metallizations for semiconductor devices includes forming trenches in a dielectric layer, depositing a single layer diffusion barrier in the trenches, and without an air-brake, depositing a seed layer of metal on the surface of the diffusion barrier.
  • the trenches are then filled with metal.
  • the metal adheres to the seed layer, which adheres to the diffusion barrier to provide many improvements to electrical characteristics as well as to reduce failures in the semiconductor devices.
  • the present invention avoids this air-brake and overcomes, among other things, problems due to adhesion problems.
  • Another method for forming metallizations for semiconductor devices includes the steps of forming trenches in a dielectric, depositing a single layer diffusion barrier in the trenches, without an air-brake, depositing a seed layer of metal on the surface of the diffusion barrier, filling the trenches with metal, and planarizing a top surface down to the dielectric layer in a single polishing step to remove the metal and the diffusion barrier.
  • Yet another method for forming copper metallizations for semiconductor devices includes the steps of forming trenches in a dielectric layer including an oxide, chemical vapor depositing a single layer diffusion barrier comprised of Ti or TiN in the trenches, without an air-brake after the chemical vapor depositing of the single layer diffusion barrier, chemical vapor depositing a seed layer of copper on the surface of the diffusion barrier, and filling the trenches with copper.
  • the step of without an air-brake, depositing a seed layer preferably includes the step of without an air-brake, chemical vapor depositing a seed layer of metal on the surface of the diffusion barrier.
  • the steps of depositing a single layer diffusion barrier in the trenches and without an airbrake, depositing a seed layer of metal are performed in a same processing chamber.
  • the seed layer and the metal preferably include copper.
  • the trenches may include dual damascene trenches.
  • the diffusion barrier may include one of Ti, TiN, WN, or TaN.
  • the diffusion barrier is preferably less than or equal to 5 nm.
  • the step of filling the trenches with metal may include the step of electroplating the metal to fill the trenches with the metal .
  • the step of depositing a single layer diffusion barrier may include the step of chemical vapor depositing the diffusion barrier.
  • the step of without an air-brake, depositing a seed layer may include the step of without an air-brake, ionized sputtering a seed layer of metal on the surface of the diffusion barrier.
  • the step of filling the trenches with metal may include the step of sputtering to fill the trenches with the metal.
  • FIG. 1 is a cross-sectional view of a dual damascene trench formed in a dielectric layer for applying the present invention
  • FIG. 2 is a cross-sectional view of a via, trench or single damascene structure formed in a dielectric layer for applying the present invention
  • FIG. 3 is a cross-sectional view of the dual damascene trench of FIG. 1, with a single layer diffusion barrier formed therein in accordance with the present invention
  • FIG. 4 is a cross-sectional view of the trench of FIG. 2, with a single layer diffusion barrier formed therein in accordance with the present invention
  • FIG. 5 is a cross-sectional view of the dual damascene trench of FIG. 3, with an in-situ seed layer of metal formed on the diffusion barrier in accordance with the present invention
  • FIG. 6 is a cross-sectional view of the trench of FIG. 4, with an in-situ seed layer of metal formed on the diffusion barrier in accordance with the present invention
  • FIG. 7 is a cross-sectional view of the dual damascene trench of FIG. 5, filled with metal in accordance with the present invention.
  • FIG. 8 is a cross-sectional view of the trench of FIG. 6, filled with metal in accordance with the present invention.
  • FIG. 9 is a cross-sectional view of the dual damascene trench of FIG. 7, planarized down to the dielectric layer in a single step polish process in accordance with the present invention.
  • FIG. 10 is a cross-sectional view of the trench of FIG. 8, planarized down to the dielectric layer in a single step polish process in accordance with the present invention.
  • the present invention relates to semiconductor fabrication processing and more particularly, to a method for reducing failures while employing copper metallizations in semiconductor devices.
  • Attempts by the inventors to employ copper metallizations in semiconductor devices included employing a conformal chemical vapor deposited (CVD) TiN diffusion barrier for a Cu metallization scheme.
  • the diffusion barrier may also include other CVD materials, such as, for example, TaN, WN, etc.
  • the additional layer reduced the effective current carrying cross- section of Cu.
  • the inventors have discovered new methods for employing metallizations for semiconductor devices with surprising results.
  • a diffusion barrier for example, a titanium nitride (TiN) barrier
  • CVD chemical vapor deposition
  • a seed layer for a metal may be deposited with superior adhesion to the diffusion barrier.
  • the diffusion barrier may be made conformally, thin diffusion barriers are provided, and metal seed layers may advantageously be deposited directly on the chemical vapor deposited diffusion barrier.
  • Device 100 may include a memory device, a logic device or a combination of both.
  • Device 100 may include an application specific device or any other semiconductor device, which employs metal lines.
  • a target layer 102 includes a conductive material, such as a metal line, a contact and/or a diffusion region formed in a substrate.
  • a dielectric layer 104 is formed on target layer 102.
  • Dielectric layer 104 may include a silicate glass or an oxide, such as silicon dioxide. Other dielectric materials may be employed as well. Dielectric layer 104 is patterned, in this case, to form a dual damascene structure.
  • the dual damascene structures includes vias or holes 106 extending to target layer 102 and a trench 108 extending into and/or out of the plane of the page.
  • a resist layer 112 is shown for patterning trenches 108.
  • Vias 106 may be formed prior to trenches 108 using a different resist layer (not shown) which is patterned to etch open vias 106.
  • dielectric layer 104 may also be patterned using a resist layer 114 to etch holes 107 which may include vias, contact holes or single damascene structures.
  • etch holes 107 may include vias, contact holes or single damascene structures.
  • the structures shown in FIGS. 1 and 2 are illustrative only and should not be construed as limiting the invention.
  • Diffusion barrier 116 is deposited over dielectric layer 104 and over an exposed portion of target layer 102.
  • Diffusion barrier 116 is advantageously conformally deposited. This conformal deposition of diffusion barrier 116 is preferably performed in an evacuated chamber by a chemical vapor deposition process. A physical vapor deposition process, such as sputtering may also be employed.
  • Diffusion barrier 116 preferably includes Ti, TiN or equivalent materials. Diffusion barrier 116 is preferably as thin as possible, for example less than or equal to 5 nm, or more preferably less than or equal to 3 nm. In some cases, the thickness of diffusion barrier 116 is at least 1 nm.
  • a seed layer 118 is deposited or flashed onto diffusion barrier.
  • seed layer 118 is formed without an air-brake between the deposition of diffusion barrier 116 and the deposition of seed layer 118. Eliminating the air-brake which is typically performed after a diffusion barrier deposition may be performed by employing a same tool to deposit both diffusion barrier 116 and seed layer 118. A different tool may be employed if the environment around device 100 is maintained in an inert or evacuated state. Eliminating the air-brake after diffusion barrier deposition has demonstrated surprising results as will be described in greater detail below. Seed layer 118 is preferably copper, although other metals, such as aluminum may be employed.
  • Seed layer 118 provides nucleation sites on diffusion barrier 116 such that when the structures are filled better adhesion is provided and voids are eliminated or significantly reduced.
  • Seed layer 118 may be formed by a physical vapor deposition (PVD) process, such as, an ionized sputtering process or by a CVD process. The CVD process is preferred. Seed layer 118 need only be about 0.03 nm in thickness although other thicknesses may also be useful .
  • PVD physical vapor deposition
  • a conductive material 120 which is preferably the same material as seed layer 118.
  • Conductive material is preferably copper, although benefits for aluminum and other metals may be obtained in accordance with the present invention.
  • Conductive material 120 may be performed in a different tool other than the tool for the deposition of diffusion barrier 116 and/or seed layer 118 deposition. Conventional tools may be employed as are known to those skilled in the art. A CVD process, a PVD process or a combination of both processes may be employed to provide conductive material 120. Alternately, an electro-chemical deposition (ECD) process may be used to deposited conductive material.
  • ECD electro-chemical deposition
  • conductive material 120 nucleates on seed layer 118 and significantly greater adhesion to diffusion barrier 116 is achieved.
  • the following illustrative options are possible for a reliable Cu metallization scheme:
  • phase II copper metallization is provided.
  • a phase II cooper includes a copper metallization, which is extendable at least down to 0.1 microns !
  • an in-situ TiN diffusion barrier includes the capability of a 1-step polish process, for example, a chemical-mechanical polish (CMP) process to remove conductive material 120.
  • CMP chemical-mechanical polish
  • multiple diffusion barrier layers are employed, such as those including an additional Ta/TaN barrier, the additional layers have to be removed in an additional CMP step after conductive material removal .
  • a planarized surface 122 is provided by a one-step CMP process. Testing by the inventors has shown that dishing of conductive material 120 in a trench or hole due to overpolishing is reduced by using the fast one-step process instead of a more expensive two step polish. Interconnect shorts and opens are at least equivalent if not better for the cheaper 1- step CMP process as opposed to the expensive 2-step CMP process.
  • the present invention is particularly useful for sub- micron groundrules, for example, less than 0.3 microns, although the invention may be practiced with larger groundrules.
  • the present invention is also particularly useful for structures (trenches or holes) with aspect ratios of 4:1 or greater.
  • contact resistance between metal lines of a first layer and contacts to metal lines of a second layer was at least 2.5 times better than for copper metallizations in accordance with the present invention (in-situ diffusion barrier and seed layer) as opposed to copper metallizations with a bi- layer diffusion barrier and air-brake.
  • sheet resistance is improved slightly for the present invention.
  • chain resistance tests showed results of at least about 10 times better for the present invention as opposed to copper metallizations with a bi-layer diffusion barrier and air-brake. Chain resistance for 0.175 micron structures with 100,000 chains was tested by known testing techniques . If copper is employed about 1000 times fewer electromigration failures occur due to in- situ CVD TiN diffusion barrier and copper metal.
  • CVD barrier in accordance with the invention, provides higher conformity and therefore prevents significant diffusion resulting in fewer failures.
  • copper metallizations may be used instead of aluminum (although aluminum sees improvements as well if used) which improves conductivity of metal lines and contacts;
  • a single polish step reduces costs (e.g., by about 40%) ;

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention porte sur un procédé permettant de réaliser des métallisations pour des dispositifs à semi-conducteurs et consistant à former des tranchées (107) dans une couche de diélectrique (104), déposer une barrière de diffusion unique (116) dans les tranchées, et sans coupure d'air, déposer une métallique à germe monocristallin (118) sur la surface de la barrière de diffusion. Les tranchées sont ensuite remplies de métal (120). Le métal adhère à la couche à germe monocristallin qui adhère elle-même à la barrière de diffusion, ce qui permet d'améliorer considérablement les caractéristiques électriques et de réduire les pannes des dispositifs à semi-conducteurs.
EP01946617A 2000-06-21 2001-06-21 Barriere de diffusion in situ et metallisation au cuivre metallisation pour obtenir des dispositifs a semi-conducteurs d'une plus grande fiabilite Withdrawn EP1292977A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US59837500A 2000-06-21 2000-06-21
US598375 2000-06-21
PCT/US2001/019820 WO2001099182A2 (fr) 2000-06-21 2001-06-21 Barriere de diffusion in situ et metallisation au cuivre metallisation pour obtenir des dispositifs a semi-conducteurs d'une plus grande fiabilite

Publications (1)

Publication Number Publication Date
EP1292977A2 true EP1292977A2 (fr) 2003-03-19

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP01946617A Withdrawn EP1292977A2 (fr) 2000-06-21 2001-06-21 Barriere de diffusion in situ et metallisation au cuivre metallisation pour obtenir des dispositifs a semi-conducteurs d'une plus grande fiabilite

Country Status (4)

Country Link
EP (1) EP1292977A2 (fr)
KR (1) KR100788064B1 (fr)
TW (1) TW512490B (fr)
WO (1) WO2001099182A2 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114477779B (zh) * 2021-12-30 2023-09-08 厦门云天半导体科技有限公司 一种基于异质键合的多层玻璃基板工艺和结构

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5918149A (en) * 1996-02-16 1999-06-29 Advanced Micro Devices, Inc. Deposition of a conductor in a via hole or trench
US5770520A (en) * 1996-12-05 1998-06-23 Lsi Logic Corporation Method of making a barrier layer for via or contact opening of integrated circuit structure
US5933758A (en) * 1997-05-12 1999-08-03 Motorola, Inc. Method for preventing electroplating of copper on an exposed surface at the edge exclusion of a semiconductor wafer
US6174811B1 (en) * 1998-12-02 2001-01-16 Applied Materials, Inc. Integrated deposition process for copper metallization
US6251759B1 (en) * 1998-10-03 2001-06-26 Applied Materials, Inc. Method and apparatus for depositing material upon a semiconductor wafer using a transition chamber of a multiple chamber semiconductor wafer processing system
US6037258A (en) * 1999-05-07 2000-03-14 Taiwan Semiconductor Manufacturing Company Method of forming a smooth copper seed layer for a copper damascene structure

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0199182A2 *

Also Published As

Publication number Publication date
KR100788064B1 (ko) 2007-12-21
TW512490B (en) 2002-12-01
WO2001099182A2 (fr) 2001-12-27
KR20030020304A (ko) 2003-03-08
WO2001099182A3 (fr) 2002-04-18

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