WO2001099167A3 - Dispositif memoire comportant des nano-amas et procede de fabrication dudit dispositif - Google Patents

Dispositif memoire comportant des nano-amas et procede de fabrication dudit dispositif Download PDF

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Publication number
WO2001099167A3
WO2001099167A3 PCT/US2001/016585 US0116585W WO0199167A3 WO 2001099167 A3 WO2001099167 A3 WO 2001099167A3 US 0116585 W US0116585 W US 0116585W WO 0199167 A3 WO0199167 A3 WO 0199167A3
Authority
WO
WIPO (PCT)
Prior art keywords
nanoclusters
dielectric layer
tunnel dielectric
layer
formation
Prior art date
Application number
PCT/US2001/016585
Other languages
English (en)
Other versions
WO2001099167A2 (fr
Inventor
Sucharita Madhukar
Ramachandran Muralidhar
David L O'meara
Hsing H Tseng
Bruce E White
Michael A Sadd
Sufi Zafar
Bich-Yen Nguyen
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Priority to AU2001263370A priority Critical patent/AU2001263370A1/en
Publication of WO2001099167A2 publication Critical patent/WO2001099167A2/fr
Publication of WO2001099167A3 publication Critical patent/WO2001099167A3/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42332—Gate electrodes for transistors with a floating gate with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate

Abstract

La présente invention concerne un dispositif mémoire à semi-conducteur doté d'une grille flottante qui comporte une pluralité de nano-amas (21), ainsi que des techniques utiles pour la fabrication dudit dispositif. Selon ledit procédé, une couche diélectrique à effet tunnel (14) est formée sur un substrat semi-conducteur (12). Une pluralité de nano-amas (19) est ensuite amenée à croître sur la couche diélectrique à effet tunnel (14). Cette croissance est facilité par la formation d'une couche contenant de l'azote (502), qui peut être du nitrure, destinée à couvrir la couche diélectrique à effet tunnel (14). Des parties sélectionnées de la couche contenant de l'azote (502) peuvent être éliminées pour permettre un meilleur contrôle des sites où les nano-amas sont formés. La croissance des nano-amas peut également être facilitée par traitement de la surface de la couche diélectrique à effet tunnel (14) pour modifier la structure de liaison de ladite couche (14). Après formation des nano-amas (21), un couche diélectrique de commande (20) est formée sur lesdits nano-amas (21). Une électrode (24) de grille est ensuite formée sur le diélectrique de commande. Puis des parties de la couche diélectrique de commande (20), de la pluralité de nano-amas et du diélectrique de grille qui ne se trouvent pas sous l'électrode de grille sont sélectivement éliminées. Après formation des éléments d'écartement (35), des régions de source et de drain (32, 34) sont formées par implantation dans la couche de semi-conducteur (12) de manière qu'une région de canal soit formée entre les régions de source et de drain (32, 34) se trouvant sous l'électrode (24) de grille.
PCT/US2001/016585 2000-06-16 2001-05-23 Dispositif memoire comportant des nano-amas et procede de fabrication dudit dispositif WO2001099167A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001263370A AU2001263370A1 (en) 2000-06-16 2001-05-23 Memory device including nanoclusters and method for manufacture

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US59583000A 2000-06-16 2000-06-16
US09/595,830 2000-06-16

Publications (2)

Publication Number Publication Date
WO2001099167A2 WO2001099167A2 (fr) 2001-12-27
WO2001099167A3 true WO2001099167A3 (fr) 2002-04-04

Family

ID=24384850

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/016585 WO2001099167A2 (fr) 2000-06-16 2001-05-23 Dispositif memoire comportant des nano-amas et procede de fabrication dudit dispositif

Country Status (3)

Country Link
AU (1) AU2001263370A1 (fr)
TW (1) TW494572B (fr)
WO (1) WO2001099167A2 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100601943B1 (ko) * 2004-03-04 2006-07-14 삼성전자주식회사 고르게 분포된 실리콘 나노 도트가 포함된 게이트를구비하는 메모리 소자의 제조 방법
US7361567B2 (en) * 2005-01-26 2008-04-22 Freescale Semiconductor, Inc. Non-volatile nanocrystal memory and method therefor
WO2010023575A1 (fr) * 2008-08-26 2010-03-04 Nxp B.V. Condensateur et procédé de fabrication

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11111869A (ja) * 1997-10-03 1999-04-23 Sharp Corp 半導体記憶素子
JPH11330273A (ja) * 1998-05-08 1999-11-30 Toshiba Corp 半導体素子
EP0971416A1 (fr) * 1998-01-26 2000-01-12 Sony Corporation Dispositif memoire et procede de fabrication correspondant, et circuit integre et procede de fabrication correspondant
US6060743A (en) * 1997-05-21 2000-05-09 Kabushiki Kaisha Toshiba Semiconductor memory device having multilayer group IV nanocrystal quantum dot floating gate and method of manufacturing the same
US6140181A (en) * 1997-11-13 2000-10-31 Micron Technology, Inc. Memory using insulator traps

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6060743A (en) * 1997-05-21 2000-05-09 Kabushiki Kaisha Toshiba Semiconductor memory device having multilayer group IV nanocrystal quantum dot floating gate and method of manufacturing the same
JPH11111869A (ja) * 1997-10-03 1999-04-23 Sharp Corp 半導体記憶素子
US6140181A (en) * 1997-11-13 2000-10-31 Micron Technology, Inc. Memory using insulator traps
EP0971416A1 (fr) * 1998-01-26 2000-01-12 Sony Corporation Dispositif memoire et procede de fabrication correspondant, et circuit integre et procede de fabrication correspondant
JPH11330273A (ja) * 1998-05-08 1999-11-30 Toshiba Corp 半導体素子
US6208000B1 (en) * 1998-05-08 2001-03-27 Kabushiki Kaisha Toshiba Semiconductor element having charge accumulating layer under gate electrode and using single electron phenomenon

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1999, no. 09 30 July 1999 (1999-07-30) *

Also Published As

Publication number Publication date
WO2001099167A2 (fr) 2001-12-27
AU2001263370A1 (en) 2002-01-02
TW494572B (en) 2002-07-11

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