TW494572B - Memory device including nanoclusters and method for manufacture - Google Patents

Abstract

A semiconductor memory device with a floating gate that includes a plurality of nanoclusters (21) and techniques useful in the manufacturing of such a device. The device is formed by first providing a semiconductor substrate (12) upon which a tunnel dielectric layer (14) is formed. A plurality of nanoclusters (19) is then grown on the tunnel dielectric layer (14). Such growth is facilitated by formation of a nitrogen-containing layer (502), which may be nitride, overlying the tunnel dielectric layer (14). Selected portions of the nitrogen-containing layer (502) may be removed to aid in controlling where nanoclusters are formed. The growth of the nanoclusters may also be facilitated by treating the surface of the tunnel dielectric layer (14) to alter the bonding structure of the tunnel dielectric layer. After formation of the nanoclusters (21), a control dielectric layer (20) is formed over the nanoclusters (21). A gate electrode (24) is then formed over the control dielectric, and portions of the control dielectric layer (20), the plurality of nanoclusters, and the gate dielectric that do not underlie the gate electrode are selectively removed. After formation of spacers (35), source and drain regions (32, 34) are formed by implantation in the semiconductor layer (12) such that a channel region is formed between the source and drain regions (32, 34) underlying the gate electrode (24).

Description

494572 V. Description of the invention (i) Participants in Mai Qianshen's case This application has been proposed in the United States as a patent application number 0 9/5 9 5, 8 3 0 on June 16, 2000. FIELD OF THE INVENTION The present invention relates generally to semiconductor devices. More specifically, the present invention relates to a semiconductor memory device and the manufacturing-related techniques for forming such a semiconductor memory device. The subject document is disclosed in US Patent Application No. SC11076TP, named & quot Memory device and manufacturing method f '("Mem〇ry Device and Method for Manufacture") and U.S. Patent No. SC10966TP, named n-memory and method using pre-isolated storage elements "(" Memory Device and Method for Using Prefabricated Isolated Storage Elements), and U.S. Patent Application No. SC11062TP, named " oral memory device and manufacturing method containing protected nanoparticle groups " ("Memory Device That

Includes Passivated Nanoclusters and Method for anu f act ure "), which was simultaneously proposed and licensed to the assignee.

A 7% eT electrical erasable programmable memory-only memory module (EEPROM) structure is often used for non-volatile and often contains a floating gate, I = medium. As is known, the EEPROM device structure is either a floating gate structure or a charge storage capability. Charge can be added to the floating idler to remove it from the floating idler structure. The isoelectricity can obviously be stored in the floating gate

494572 V. Invention description (2) The charge exists and changes. Since the difference in conductivity of a charged or uncharged floating gate can be current-sensed, a binary memory state is allowed to be determined. This conductivity difference can also be represented by a bias with respect to the threshold voltage (VT) of the device in two different states. As semiconductor devices continue to improve, the operating voltage of such semiconductor devices can often be reduced to suit low-power applications. It is necessary to achieve this reduction in operating voltage, while still guaranteeing to maintain or improve the rate and function of the device. The controlling factor that needs to be programmed and erased in the operating voltage is the thickness of the tunneling oxide, thereby allowing carriers to be exchanged between the floating gate and the channel region below it.

In many prior art device structures, the floating gate system is formed from a uniform material layer, such as polycrystalline silicon. In this prior art device structure, a thin tunneling dielectric layer under the floating gate will present a charge leaking from the floating gate to the channels below it through defects in the thin tunneling dielectric layer. problem. Such charge leakage may cause deterioration of the state of the memory stored in the device, and therefore, it is not suitable to be generated. To avoid this charge leakage, it is common to increase the thickness of the tunneling dielectric layer. However, a thicker tunneling dielectric layer requires a higher (programming and erasing) voltage to store and remove the charge of the floating gate because the charge carrier must pass through the thicker tunneling dielectric layer. In many cases, a higher programmed voltage requires a charge pump on the integrated circuit to increase the supply voltage to meet the demand for the programmed voltage. This charge pump consumes a considerable amount of chip area of the integrated circuit, so it will reduce the memory array area efficiency and increase the overall cost. In order to reduce the required thickness of the tunneling dielectric layer, and by reducing the charge pump

Page 8 494572 V. Description of the invention (3) ~~~~~ = ^ to improve the area efficiency of the memory structure. For this floating sentence ^, the layer can be replaced by a plurality of nanoparticle groups, and how is it stored? element. This group of femtoparticles is also commonly referred to as femtocells, as they are formed from silicon crystals. Provides a proper charge storage in a nanoparticle group: σ surname ^ plural inter-isolation, so that any potential through a local: "Qiao Bi: Really, any leakage occurred in the particle group will not cause electricity, = = (By controlling the average interval between the nano-particle groups, the wave leakage effect in the nano-two-layer device is reduced by :! Loss of state information occurs in the cladding sub-brake device. The small floating device constituted by the floating device is a large floating Η 洋 洋 of the nano-particle group in the ocean moving gate structure. The density of the nano-particle group is sufficient for the device: = Γ determines the The current limit i = higher density.] When the charge density of the germanium storage element is increased, it is necessary to change the threshold voltage for its conductance in the prior art. Higher storage density in the millimeter will basically cause a loss of tritium's charge, thus deteriorating the floating

5. Description of the invention (4), the overall charge retention characteristic p & = Γ is a longer stylized section to enter each nanoparticle group at the beginning of storage. It is difficult to control the silicon when using this technology to improve the formation of nano-particles of each nano-particle group in the previous technology to implant silicon atoms into a dielectric material causing these implanted silicon atoms to pass through the micro-particle group. The nanoparticle group cannot control the level due to the electronic characteristics of the isolated storage element. In another previous technique, an amorphous stone layer was deposited in the step of passing through the medium to recrystallize the amorphous fragment. The amorphous particles need to have a density and size of nano-particles so that the thickness can be difficult to control. Therefore, during and outside the process, due to pre-problems in the amorphous dream layer. Such pre-existing crystals can adversely interfere with the nanoparticle population growth. At the time when this limit is formed for other nanoparticle groups, because the particle is strong, the subsequent charge density particle group technology is added. The next phase is separated and gathered, because the thickness of the meso-form will be greatly provided outside the one system, and the carrier that requires a continuous performance will be lower when it is needed. It will be implanted and used together. In the electrical materials, the ionic annealing that will affect the nano-long charge in the forming situation is formed on the electrical materials in the technology of forming the required nano-particle groups. It subsequently becomes a nanoparticle group. For the group ', this layer of amorphous silicon must be graded. It is not practical to deposit such a thin layer. In addition to this pre-existing crystalline region, the nucleation and formation required for the growth of the crystals are accompanied by the occurrence of microparticles at the same time as the plant time. The implantation step is completely separate. What's important is that a thin layer of a layer is used to generate the deposited silicon. The amorphous silicon layer is controlled by additional factors. Its crystals are formed in the prior art.

Page 10 -_______ 4 494572 V. Description of the invention (5) '(CVD) technology' such as low pressure chemical vapor deposition (LpcvD) is used to nucleate and grow the nanoparticle group directly on the tunneling oxide . This prior art L PC C V D technology basically occupies a very short deposition period, and its number of stages is about 10-30 seconds. Part of this deposition period includes an incubation period, in which a suitable number of silicon atoms are aggregated to form the crystal structure of the nanoparticle group, and will be generated on the surface of the dielectric layer before the action. The rest of the time = is used to nucleate and grow the nanoparticle group to the required size. Due to the tendency of ^ nucleation and growth period to be unduly short ^ + &μ; = the completeness of the edge of the fork non-cold sister, in the processing parameters small = change, the resulting density and size of the final nanoparticle group Both have 2 deep effects. Furthermore, systemic effects can be significant. For example, the part of Shixi wafer processed by Gumi II can form a higher group: the size of the inch field, which is far away from the source of the reactive gas, is an inhomogeneity in the process. = And smaller rulers: a way to include the size dispersion of nanoparticle populations in one way. The simple jgj class: the example to illustrate 'is not limited to the attached drawings, where the reference text represents similar elements, and where [, qu] 1 shows The curve formed by the microparticle group, i, 4, and You are the dense production of nanoparticle groups in the CVD process, and the medium is a lane. Its jealousy and time are green; A cross-sectional view of a part of a semiconductor substrate, 1 layer of tunneling dielectric layer;

FIG. 14 is a cross-sectional view of the semiconductor substrate portion of FIG. 3 ′ according to its nitrogen-containing layer; FIG. Which includes the junction structure; FIG. Figure, which is continued in the period of the shape of 'where according to the warp partly or' where according to the dielectric layer; 'where according to the material layer;' where according to the patterned and 'where according to the fifth, the description of the invention (6) = 3 A specific embodiment of the semiconductor substrate of FIG. 2 is shown next. FIG. 4 shows the semiconductor substrate of FIG. 2. The surface of the dielectric layer covering u has the initial surface shown in FIG. 4. The :::: chain semiconductor of the semiconductor substrate-a special embodiment. Next, the molecular chain structure is changed at the surface; the technical change is shown in the tunnel of the semiconductor substrate of the invention of FIG. 2- In a specific embodiment, the microparticle group is shown in FIGS. 7-9, which are corresponding to the truncated nanoparticle group 1 of the part of FIG. 6 according to a special I of the present invention. In the later version Π Ξ:;: 9 bodies and half = ^: all reach the tunnel The flat J-grain group on the surface of the dielectric layer has been shown as f11 in the semiconductor substrate portion of FIG. 10, and the semiconductor substrate shown in FIG. 1 is shown. -Gate of the Invention & FIG. 12 is a cross-sectional view of a portion of a semiconductor substrate.

Page 12 rz V. Description of the invention (7) A special embodiment of the present invention, a part of the control dielectric layer in the bean has been selectively removed; $ 15 shows the semiconductor substrate portion of FIG. 14 A cross-sectional view of 'wherein according to a special specific embodiment of = I, which is partially removed. 1 electric layer 'after a plurality of nanoparticle groups and the control dielectric layer; 16 is a cross-sectional view of the semiconductor substrate portion which is not shown in FIG. 15' where a specific embodiment is described, for a semiconductor The device has been formed: "wall 'source region and drain region 敁:, H a / jnfj lyn 7 gap wall, source region and drain region 掳 -19 is a cross section of the semiconductor substrate portion shown in FIG. 3 Figure 'where a root ^ f' is a special embodiment, which is after using subsequent steps to cover ^ the nitrogen-containing layer section of the dielectric layer passing through; this is not shown in Figure 19 A cross-sectional view of a semiconductor substrate portion, where according to a special embodiment, the next selection tunnel of the nanoparticle group is not a special embodiment according to the present invention, and is formed in a layer An enlarged cross-sectional view of the plurality of nanoparticle groups on the above; ^ 摅 太 ^ is an enlarged cross-sectional view of the plurality of nanoparticle groups in FIG. 21, and a special embodiment of the hidden ^^ below it is Partially or completely in equilibrium with the surface of the electrical layer; according to Γ 发 3: 巧 2 "粒"; large cross-section view, in which the root-coating layer, ^ _ β "耄 microparticle group has been coated in the enlarged section of the structure of Ming J 2-f: 23, according to the Benfa Temple special In a specific embodiment, a control dielectric layer has been formed in the tunneling

----- Page 13 V. Description of Invention

Dielectric layer diagram 2 5 According to the present particle group diagram 26, one-to-one control diagram 27, one particle group diagram 28, and 28, a tunnel, and a professional view, the size can be specific and the coating is shown in Figure 2 2 A special concrete dielectric layer formed under a special structure shown in Figure 2 is shown in Figure 2 5; a special multi-layered dielectric structure shown in Figure 2 2 is shown in the figure. It may be unnecessary to compare with respect to other embodiments. An enlarged cross-sectional view of the nanoparticle group below the nanoparticle group; a specific embodiment is an enlarged cross-sectional view of the structure next to the plurality of thin dielectric layers; the root embodiment is the next An enlarged cross-sectional view of the structure of the thin dielectric 'layer, wherein the root embodiment' is to form a dielectric layer covering the plurality of dielectric layers next; and in a special embodiment of the present invention, a plurality of covering the tunneling dielectric is formed. The components in the schematic drawing of the processing device for controlling the dielectric layer with the nano-layer covering the electrical layer are only for simplicity and example drawing. For example, some elements in the drawing are enlarged to help improve the understanding. The nanofibers are formed to form the particle group to form a picture. DETAILED DESCRIPTION OF THE INVENTION This invention is clear from elements. Generally speaking, the present invention relates to a semiconductor device having a floating gate, which contains a plurality of nanoparticle groups, and a technique that can be used to manufacture the same. The device is formed by first providing a tunneling semiconductor substrate formed thereon. A plurality of nanoparticle groups then grows through the dielectric layer. This growth is facilitated by the formation of a nitrogen-containing layer, which nitride ' covers the tunneling dielectric layer. The memory layer selected in the nitrogen-containing layer may be part of the electrical layer. 494572 V. Description of Invention (9) " is removed to help control the formation of nanoparticle groups. The growth of the nanoparticle group can also be promoted by processing the surface of the tunneling dielectric layer to modify the chain structure of the tunneling dielectric layer. After forming the nanoparticle group, a control dielectric layer is formed on the nanoparticle group. A gate is then formed over the control dielectric layer, a portion of the control dielectric layer not located below the gate, a plurality of nanoparticle groups, and the gate dielectric layer is selectively removed. . After the formation of the gap wall, the 'source and electrode' and the electrode region are formed by implantation in the semiconductor layer ', so that a channel region is formed between the source electrode and the drain electrode region below the gate electrode. By forming a floating gate of the semiconductor device using a long nanoparticle group formed through a controlled LPCVD, RTCVD or UHCVD process, the density of the nanoparticle group contained in the floating gate structure can be tightly controlled. In this box, a reference to the LPCVD process can describe a process that can be performed using LPCVD or RTCVD process technology. In a specific embodiment using LPCVD, a multi-step process can be used to ensure selectivity for nucleation and growth for different nanoparticle population formation stages. Therefore, the required nanoparticle group density can be achieved when the size and density uniformity are guaranteed in the manufacturing process. In a specific embodiment where UHVCVD is used to grow the nanoparticle group structure, additional benefits can be achieved because the background pollution is reduced in the environment where the formation of the nanoparticle group occurs. Similar optimization of the formation of the nanoparticle group used in the LPCVD technique can be applied to the UHVCVD technique to generate the desired nanoparticle group structure. In UHVCVD technology, even if the pressure is lower than the pressure existing in LPCVD technology, it can provide a further reduction in growth kinetics, so a higher layer can be reached when the nanoparticle group is formed

P.15 494572 V. Control of Invention (ίο) Times. Furthermore, the present invention in the group growth rate can be generalized by the nucleation and microparticle group. The curve 3 0 2 ′ is due to the potential latent gradient before referring to Figure 1-The growth phase of the development should be consistent with the one-step growth time system. Corresponding to a single nanoparticle at the beginning of the breeding stage, at the beginning, it showed a lower temperature and two deposits were also higher in the shape of its quilt ° ~ Shi Xi at a longer nuclear rate segment, which will cause The formation of grain clusters began with the previous technique Shen, in which the Shi Xi dielectric material sinks. Due to the higher temperature in the environment above the dielectric layer. Condition of temperature. . At higher temperatures, a stable nucleus atom that already exists is affected by an existing diffusion distance and has a large impact. The atom suddenly accumulates in silicon. The atomic product of silicon has stabilized. Before the nucleus, the crystal nucleus will have zero emptying effect of this gas, which can be further minimized in nano particles. 28 to get a better understanding. Figure 1 shows the milli-curve as a function of time. Figure 1 shows the two curves 3 0 2 and the previous process of the nano particle group development and integration process. The higher temperature and shorter micro particle group growth control levels are limited by the parameters provided in the curve corresponding to curve 3. During the 02 period, there was a lack of control over nucleation to selectivity. The technical curve 302, which begins with a short hair deposition on the tunneling dielectric layer after Q _ sufficient silicon atoms, the fact that the nucleation is opened and used in conjunction with the previous technology will have a high surface diffusivity. The size of the key crystal nucleus present in plutonium is also higher than the growth of the formed crystal nucleus. At higher temperatures, the silicon atoms reaching the surface of the dielectric layer must be captured or combined with other diffused silicon. And the probability of moving through a longer diffusion distance to catch is at a higher temperature, = ^, so the growth rate of this nucleus is limited to the nucleation and rapid growth of the species β

Page 16 494572 V. Description of the invention (11)-necessary because it will f1 a small number of large nanoparticle groups. Once the saturation region 304 on curve 2 has been passed, these large femtoparticle populations continue to grow and begin to fuse at a density of H = f particle populations that is less than the maximum saturation density of 306 with respect to curve 3 02. Note that the flat portion of the curve 302 has—a fairly short period of time—that it reaches the saturation density. The higher temperature corresponding to curve 302, during the initial nucleation and subsequent growth of the nanoparticle group, will result in a greatly reduced period, thus reducing the degree of control of the overall nanoparticle group development. Again and again, the time corresponding to the growth of the nanoparticle group corresponding to the curve 302

A slight change will cause a more pronounced change in the density and size of the nanoparticle group. ’

The curve 3 1 2 corresponds to the development of a nanoparticle group according to a part of the principle provided here. This principle provides a lower temperature treatment, which can lead to a greater degree of control over the nucleation and growth of the nanoparticle population. Therefore, the development of the nanoparticle group can be performed by a multi-step process instead of a single and difficult to control step. At the development stage 32Q ' corresponding to this curve 312, a south selective nucleation stage 3 1 8 will occur. The nucleation stage 8 allows for a relative nucleation to growth ratio with respect to the formation of a group of rhenium microparticles on the surface of the tunneling dielectric layer. Therefore, Shi Xi atoms (or atoms of other materials used to form the nanoparticle group) existing on the surface of the tunneling dielectric layer are more likely to form crystal nuclei than adhere to the pre-existing crystal nuclei, It will cause growth. The better conditions for this selective nucleation stage may include low temperatures and higher partial pressures of the reaction gas. Please note that the temperature must not be too low to limit the reaction. Therefore, during this nucleation stage (a first

Page 17 494572 V. Description of the invention (12) The first stage), which forms a plurality of key crystal nuclei (sufficient to maintain stable large crystal nuclei). ‘After this nucleation stage 3 1 8, a saturation region 314 that is much longer than the nanoparticle group formation technology of the prior art allows the growth of the nucleated nanoparticle group structure to be controlled. During this second or growth phase, the key nucleus system grows into a nanoparticle group. The control existing in the saturated region 314 can make the size of the required nanoparticle group uniformly formed on the surface of the tunneling dielectric layer covering the surface. Since in fact the saturated region 3 1 4 is considerably longer in time, the optimized saturation density can be achieved in a manufacturing environment. Therefore, the change in the period during which the growth of the nanoparticle f occurs will have less influence on the density of the nanoparticle group obtained on the tunneling dielectric layer. Once saturation has been reached, factors that are important for extending the saturation region 3 [4] include the lower pressure of the precursor gas and a temperature greater than or equal to the nucleation temperature. Therefore, factors that increase the growth rate during the saturated region 3,4 also reduce the f-nucleation rate, which is typically associated with the nucleation stage 318. Therefore, depositing the nanoparticle group on the dielectric layer can be divided into a two-step process, and each step can be individually controlled to achieve a desired result. It must be noted that the time with respect to the curve shown in FIG. 1 is provided as an example only, and it cannot be regarded as a limitation. Therefore, the period of the nucleation and growth phase of the curve 3, 2 can be modified according to the changes in conditions existing during different deposition phases. As one of ordinary skill in the art can understand, a higher temperature will reduce the pressure when the pressure in this part is maintained at a fixed level.

Page 18

IIH V. Description of the invention (13) Period in f stages. Similarly, higher pressures will reduce periods for different stages while the temperature remains solid. FIG. 2 is a cross-sectional view of a portion of a semiconductor substrate 10 including a semiconductor layer 12. The semiconductor layer 12 may be silicon. A tunneling dielectric layer 14, which may also be referred to as a tunneling oxide layer, has been formed to cover the semiconductor layer 12. The tunneling dielectric layer 14 may be silicon dioxide, silicon oxynitride, or other high dielectric constant materials. The tunneling dielectric layer 14 may be thermally grown or deposited. The thickness of the tunneling dielectric layer 14 may be less than 50 angstroms. In the case where the formed device is used for a more volatile memory structure, it may use a thinner tunneling dielectric layer, such as those in the range of 15-20 angstroms.

In order to facilitate the formation of nanoparticle groups on the surface of the through-dielectric layer 14, the surface of the tunneling dielectric layer 14 may be modified to promote the nucleation of the nanoparticle group structure. In other words, the surface structure can be modified so that the critical crystal nucleus size, the surface diffusion of silicon atoms can be reduced, and the release of the by-products of the reactant is increased.

Fig. 3 shows a technique for changing the surface of the tunneling dielectric layer 14 to increase the promotion of nucleation. Please note that the surface variation of the tunneling dielectric layer 14 also helps to deposit a pre-formed nanoparticle population, as described in the co-filed patent application, entitled "Memory Device Using Prefabricated Isolated Storage Elements and "Method" (" MEMORY DEVICE AND METHOD FOR USING PREFABRICATED ISOLATED STORAGE ELEMENTS "), which has a lawyer's record number SC10966TP, was proposed on the same day as the present invention, and is incorporated herein by reference. Figure 3 shows the semiconductor substrate. A cross-sectional view of this part, in which a nitrogen-containing layer 502 has been formed on the tunneling dielectric layer 14

Page 19 494572 V. Description of the invention (14) ~~ ---. The nitrogen-containing layer 502 can include the nitride and oxynitride. The surface structure of the tunneling dielectric layer can be changed by changing the main stone (SiOA) ° ^ ^ ^ to ^ g M = This kind of nucleation promotes the reduction of surface expansion based on the number of atoms :; crystal plane: r promotes the nucleation of particle groups. Table II should make the 2 desired by-products caused by the formation of nanoparticle groups more Quickly adhered to the surface of the substrate from the surface and the microparticle group atoms. The nitrogen-containing layer 502 can be formed by a CVD process, such as LPCVD or UHVCVD, and the nitrogen-containing layer 502 is directly in contact with the tunneling dielectric layer 14. The UHVCVD of the nitrogen-containing layer can be more controllable than LPCVD, because UHVCVD usually occurs more slowly ^ This growth rate can be adjusted more precisely. The nitrogen-containing layer may be the result of the deposition of these gas reactions, such as silane (or other silicon source precursors such as two-gas silane, or disilazane) and ammonia (or other types of ammonia, such as plasma ions) Nitrogen, or rhenium), or reacts with the surface of a reactive gas, such as ammonia (or other types of ammonia, such as plasma ionized nitrogen, or NO). Dichloromethane and ammonia are combined with a common flow of some inert gases and oxygen-containing gases, which can be used to grow the nitrogen-containing layer 502. Once a thin nitrogen-containing layer has been formed on the surface of the tunneling dielectric layer 14, the nitrogen penetrating to the tunneling dielectric layer 14 below is usually hindered, so leakage of the tunneling dielectric layer 14 may be caused. Contamination can be avoided. The thickness of the nitrogen-containing layer 502 is preferably limited to ensure that the carrier traps contained in the nitrogen structure do not affect the charge storage aspect of the formed semiconductor device. In a specific embodiment, the required thickness of the nitrogen-containing layer is less than 10 Angstroms. In another embodiment, the required thickness may be 5 angstroms or more.

494572 V. Description of the invention (15) ^-~ _____ Small. The use of a thin nitrogen-containing layer ensures the specifications of the memory formed by the structure. Thicker and longer ;: Holder… is required because of the proper device. ”: Those charge retention characteristics at the level of 20 angstroms or more nitrogen layer are extravagant. The characteristics can be passed through the restricted inclusion body. Charge retention characteristics. Affects the entire device or is equal to 20 angstroms, which may increase the nitrogen-containing layer ’, for example, greater than

Hi:!, Caught the -ambiguity on the way for the trap. dense? : Πΐί containing at least 1012 nanoparticle groups—nanoparticle groups II f f It has been determined that a nitrogen-containing layer having a thickness of 10 Angstroms or less can be accepted. In some specific embodiments, the nitrided layer may be smaller than or ίi must be at least required to ensure that the nitrogen-containing layer 502 is ίK layer 14, so that a uniform nanoparticle group can occur. In the example, the thickness of the nitride layer is greater than i between 3 angstroms, so that an acceptable nitride thickness range can be 3 to 7 angstroms. In the case of putting silicon as the nitrogen-containing layer 50 2, The degree of nitrogen disturbance in the oxidation evening can be greater than 5%. Contained in silicon oxynitride, the specific concentration can be controlled so that the coordination between the saturation concentration of the femto group that can be formed on the surface and the trap due to the nitride concentration can be adjusted.

whole. J In other embodiments, the surface of the tunneling dielectric layer 14

Page 494 572

Nucleation of the microparticle population can be improved by changing the tunneling structure. FIG. 4 shows a surface link diagram of the semiconducting layer 14: “connected” to form the cross-section of the tunneling dielectric layer 14 :: “cross section” is false: it is a sulphur dioxide, * also shows the two: two: through Dielectric layer chain structure 5 0 4. Please note that in this silicon dioxide chain structure, 501 = the starting surface, the two 2 stone-Xi atoms are linked to the -mono-oxygen atom. Each of these structures is less reactive to the precursor gas of the syrup, which is usually used more often than Kelvin. ‘House microparticle group

In order to change the link structure of the upper surface of the tunneling dielectric layer 14, a lice body type y is applied to the surface. For example, hydrofluoric acid (hf), which may be in liquid or gas form, or other reagents, may be applied to the surface of the tunneling dielectric layer 14 to change the link structure so that the resulting surface chain The junction structure facilitates the absorption of silicon methane, reduces the size of the key particles, improves the release of reaction by-products, and thus improves the nucleation of the nanoparticle group on the tunneling dielectric layer 14. FIG. 5 shows a cross-sectional view of the portion of the semiconductor substrate 10, in which the link structure of the upper portion or the surface of the tunneling dielectric layer 14 has been changed by exposure to a reagent. The chain structure 506 is shown as a pair of individual silicon atoms linked to an oxygen reactant pair, where the reactant (R) when exposed to HF

It will be either hydrogen (Η) or fluorine (F). In other embodiments, different reagents or reaction gases can be used instead of HF. Exemplary reagents include gases, such as germane, phosphine, boroethane, ammonia, and water vapor. Therefore, the reactant portion of the link structure 506 can be different materials, where the link structure 5 6 will react more to the silicon methane gas, so the nucleation on the surface of the tunneling dielectric layer 14 can be improved. Therefore, other similar reaction gases can be used to reach the chain

Page 22 494572 V. Description of the invention (17) The same change in the knot structure is shown in FIG. 5. The surface structure of the tunneling dielectric layer 14 is changed to change the link structure, which can be transported by wet etching, or an annealing process can be performed by using a reactive gas. It is convenient to change the chain.结 结构。 Knot structure. & Fig. 6 is a sectional view of the portion of the semiconductor substrate 10 formed in Fig. 2, in which crystal nuclei that can eventually grow into nanoparticle groups 5 have begun. The period of time with respect to FIG. 6 preferably corresponds to the curve 312 2 stage 318 shown in FIG. Please note that the tunneling dielectric layer 14 of FIG. 6 can already be processed by one or more of the methods described in FIGS. 3-5 to facilitate the nucleation of M, ^^ 6. The nucleation that will occur in the process is basically based on the development of the nanoparticle population described in the figure. It is preferable to use a CVD process to

Yes, an LPCVD process or a UHVCVD process. This CVD process is based on the control environment of a CVD reaction chamber. The CVD J is made into a reaction chamber under the condition, so before: on the front drive! :::, the unwanted products caused by the operation of the plutonium are released from the surface and leave the reaction chamber. The house will promote the growth of the nanoparticle group, iί ^ ^ ΓΓΓΜδ-Λ material formation, such as Shi Xi, wrong detection, Chifen from the condition of the body materials such as α Α D to form the silicon millet ^ Two gold. In the silicon nanoparticle group…, Ershi Yujia 10% precursor precursor gas can be used to promote the initial nucleation at the same time, and the Shi Xi gas can be used to grow this nanoparticle group for a long time, until

Μ

Page 23 494572 V. Description of the invention (18) ^ ~~-To get the required density and size. In order to promote nucleation, the conditions in the CVD reaction chamber are precisely controlled. A number of factors influence whether the nucleation or growth of the nanoparticle population to be formed will occur. In order to promote nucleation, the surface properties of the tunneling dielectric layer 14 'partial pressure of the semiconductor-containing gas, temperature in the reaction chamber, and the presence and identification of any co-flowing gas are subject to control services. Parameters for the initial nucleation of silicon nanoparticle groups, which include a reaction chamber temperature not exceeding 6-0 0 ° C. The flow rate of a silicon-containing gas will be greater than or equal to 1 to about 50 per minute. In cubic centimeters (SCCM), the partial pressure of the silicon-containing gas is less than or equal to about 200 mTorr. This condition can be maintained for a period greater than 30 seconds, thereby allowing development and initial nucleation to occur. Therefore, after the through-dielectric layer 14 is formed on the substrate 12, the substrate having the through-dielectric layer 14 can be placed in a CVD reaction chamber and heated to not more than 600 ^ Even nanoparticle groups can be formed by the above-mentioned flowing gas. It was found to be effective to use 100% of Shixian methane at a temperature of 580 r at 1 00 SCCM. The knife bell has been used. Although higher pressure can accelerate the deposition of silicon, this high pressure can also shorten the formation time, which is not required for the growth of nanoparticle groups. σ Therefore, the extra lengthening time for the growth of the nanoparticle group can be achieved by lowering the partial pressure of the precursor gas. By combining a lower ^ j = temperature, an extended nucleation time can be obtained, and therefore more controllable and nucleation. A further benefit of lowering the temperature during nucleation can be achieved during this process by reducing the critical size of the nuclei formed. ^ ^ Fewer atoms must be clustered together to form a critical ruler at a lower temperature.

Page 24 IIΗ 494572

V. Description of the invention Under (19), the formation of such critical-sized crystal nuclei will be lower than the temperature required for higher-temperature crystal nuclei. -Ϊ 二 ϊ ί Ϊ ί In the example, during the formation period of the nanoparticle group, that is, the temperature within the reaction will be between 50 r and 600 r. Temperatures in the range of -500 ° C and below can cause the rate of hydrogen evolution / conduction on the surface of the conductor wafer to decrease during the formation of nanoparticle clusters. This low hydrogen release traps the nucleation process by hindering the availability of reactant sites for silicon-containing precursors. Fig. 7+ is a cross-sectional view of the portion of the semiconductor substrate 10 formed as in Fig. 6, followed by nucleation and the growth of some established crystal nuclei. The established nuclei 16 have been shown to increase in size by adding subsequent atoms, whereby additional nuclei 17 can be grown in the first stage of initial nucleation and the initial growth of the established nuclei. Formed during this intermediate stage between the second stages. FIG. 8 is a cross-sectional view of the portion of the semiconductor substrate formed in FIG. 7, because the size and density of the established crystal nucleus 18 have reached the number of atoms to be added to the established crystal nucleus without A condition where new crystal nuclei will be generated, and the nucleation has largely stopped. Generally speaking, the change from nucleation to growth point can be controlled by changing the process parameters, so that the density of the required nanoparticle group can be achieved. Once the desired density has been reached, the conditions in the CVD reaction chamber can be adjusted to promote the growth of the established nanoparticle population 18. Conditions that promote nanoparticle population growth may include lower traumatic pressure of the precursor gas, which may be a silicon-containing gas as described earlier. During this growth phase

Page 25 494572 V. Description of the invention (20) ’Part of the pressure of the stone-containing gas can be reduced to less than or equal to 10 inTorr. There is an additional factor that promotes growth rather than nucleation, which is to increase the temperature and accelerate the movement of atoms, making it more likely to attach to established nucleation sites without forming new crystal nuclei. The reduced partial pressure of the silicon-containing gas can cause fewer silicon atoms to be formed on the surface, so the growth rate of the nanoparticle group can be accurately controlled. In the I ^ CVD process, co-current gas is usually used to ensure the stability of the process. But 'this co-current gas can prevent the deposition of silicon and the growth of nano particles and clusters. For example, hydrogen is a common co-current propellant with silane. When the silicon is to be deposited on the surface of the wafer, the driving force for the decomposition of the methane gas into silicon and hydrogen will be prevented by the co-current gas of hydrogen, because the hydrogen by-product of the decomposition of silicon methane will be prevented by The surface of the wafer is released so that in order to promote the simultaneous generation of nucleation and growth of silicon deposits, a mixed gas is used, including an inert co-current gas, such as argon or argon, and a semiconductor-containing gas, such as silicon Pinane or disilazane can be used to enhance the deposition of lithosene on the wafer. It should be noted that the reason hydrogen is often used as a co-current gas with silicon methane in other CVD operations is that it can help prevent the decomposition of silicon into silicon and hydrogen. However, for the existence of the particles in the reaction chamber, the growth of the particle group, the lower pressure of the lower pressure junction of the silicon dioxide gas will prevent this gas phase decomposition. Therefore, its inert gas can be used as a co-current gas in order to allow the successful completion of LPCVD, processing 'without considering the gas phase decomposition of the silane gas. In the present invention, UHVCVD is used to form the specific embodiment of the nanoparticle group.

Page 26 494572 V. Description of the invention (21) ^ ~~ --——- ~~~ -_ In the embodiment, no co-current gas is required to promote

Distribution of other semiconductor-containing gases. It is not necessary for the 3 / conductor body to be in the UHVCVD i density during the incubation or formation of nano-particle groups. After that, the material conductor wafer is preferably protected; ΓΠ; ί; to prevent the Oxidation of nanoparticle groups. = Sedimentary soil

= 化 ', for example, a coated nanoparticle group, which will be described in detail. The step that can further reduce the adverse effects of this oxidation is silicon = grains Γ to reach its equilibrium shape, which can be generally ΐ! · Zί, the contact angle of the molten stone on the dielectric layer of the dioxin is approximately Is 90. . Therefore, the general shape of the nanoparticle group can be developed into a shape similar to the nanoparticle group 21. The nanoparticle group profile is based on the moisture characteristics of the tunneling dielectric layer 4 underneath. Therefore, the pretreatment through the dielectric layer 14 can be used to promote this wetting. In the case where the nanoparticle group is deposited via the LPCVD operation, the general shape of the obtained nanoparticle group structure is roughly an unbalanced structure, such as the nanoparticle group shown in FIG. 9. In order to allow the nanoparticle population deposited by Lpcv]) to reach a balanced shape as shown in Fig. 10, a process can be used. people

/ In a state where the nanoparticle group is formed via a UHVCVD operation, the extended time regarding the formation of the nanoparticle group can sufficiently allow the nanoparticle group to reach the equilibrium shape shown in FIG. 10. If this time is not sufficient, a similar annealing step can be used to facilitate the transition to the balanced architecture.

Page 27 494572 V. Description of the invention (22)

The required size for a nanoparticle population applied to a semiconductor memory structure is between 30 and 70 angstroms. In some embodiments, a target diameter of 50 angstroms is appropriate. In a Z-body embodiment using a nanoparticle group of 50 Angstroms in diameter, a density greater than 5 X 1 011 nanoparticle groups per square centimeter / 'can be achieved using the formation techniques described herein. In this implementation f, the coverage or area density of the nanoparticle group on the tunneling dielectric layer below is about 20%. The area density of 20% is suitable for manufacturing a semiconductor device because it provides an allowance for the interval between the nanoparticle groups contained in the floating gate structure. Although a higher area density can be achieved, the proximity of the isolated storage element in such a high embodiment of the area density increases the probability of lateral charge transport between the nanoparticle groups, thus reducing the isolation benefit. Fig. 11 is a cross-sectional view of the semiconductor substrate portion 10 of Fig. 10, on which a control dielectric layer 20 has been formed. The control dielectric layer 20 covers the microparticle group 21 and the tunneling dielectric layer 14. The control dielectric layer 20 can be deposited using CVD sputtering or other deposition steps commonly used in semiconductor manufacturing operations. The material included in the control dielectric layer 20 can be oxygen nitrogen oxide (0N〇), which can be oxidized. Silicon or metal oxide. Prior to forming the control dielectric layer 20, each nanoparticle group 21 may be coated to prevent oxidation as described below in Figs. 21-27.

FIG. 12 is a cross-sectional view of the portion of the semiconductor substrate 10 in FIG. 11, in which a conductive layer 22 has been deposited on the control dielectric layer 20. The conductive layer 22 is preferably a gate material, such as doped polycrystalline silicon or metal. The conductive layer 22 can be deposited using CVD or other techniques commonly used to deposit such gate materials.

Page 28 494572 V. Description of the invention (23) 囷 13 is a cross-sectional view of the part of the semiconductor substrate 10 shown in FIG. 9, in which a part of the conductive layer 22 has been removed to form a gate electrode Or gate electrode 24. The formation of the gate 24 defines a channel region in the semiconductor layer 12, which is located below the gate 24. Etching the conductive layer 22 to form the gate electrode 24 can be accomplished using a reactive ion etch.

Fig. 14 is a cross-sectional view of the semiconductor substrate portion 10 of Fig. 10, in which a portion of the control dielectric layer 20 has been etched to form an etched control dielectric layer 26. The portion of the control dielectric layer 20 that is removed to form the etched control dielectric layer 26 is the portion that is adjacent (but not below) the gate 24. Therefore, the portion of the control dielectric layer 20 that is under the gate electrode 24 is not etched. This etching can be performed using reactive ion etching (r 丨 E). FIG. 15 is not a cross-sectional view of the substrate portion 10 of FIG. 14, in which a portion of the plurality of nanoparticle groups 21 has been reacted to form a composite, which has been subsequently removed by an etching operation. The portion to be reacted is the portion which has been etched away under the control dielectric layer 20, thereby generating the etch control dielectric layer 26 shown in FIG. Therefore, the part of the plurality of nanoparticle groups 21 located below the gate 24 is generally not affected by the reaction operation. The reaction may include a reaction with oxygen, which, in the case of silicon nanoparticle populations, produces silicon oxide.

After reflecting the portion of the nanoparticle group, the reacting portion can be removed using an etching operation along with the corresponding portions of the tunneling and control dielectric layers 14 and 26. The etching operation may be a non-selective wet etching operation. For example, in the case of silicon nanoparticle populations, the reaction is part of a complex number

Page 29 494572 V. Description of the invention (24) The tritium microparticle group may include reacting those nanoparticle groups with oxygen to form oxidized stone. If the tunneling and controlling dielectric layers 14 and 26 are oxidized stones, a wet etching operation using dilute hydrofluoric acid will achieve the desired results. Shown in the cross-sectional view of FIG. 15 are the gate 24, a selected portion of the control dielectric layer 28, a portion of the nanoparticle group 21, and the tunneling dielectric layer 30. A selected part of the all is located under the gate 24.

FIG. 16 is a cross-sectional view of the semiconductor substrate 10 of FIG. 15, in which a spacer wall 35 and source and drain regions 32 and 34 have been formed to form a transistor structure (or at least its main part). . The source and drain regions 32 and 34 can be formed in the semiconductor layer 12 by implanting a dopant material. The formation of the source and non-electrode regions 32 and 34 may cause the formation of the channel region under the gate 24 between the source and drain regions 32 and 34. This transistor structure can be created to include a field isolation region (not shown) to isolate adjacent transistors. For example, the transistor shown in FIG. 16 can be used in semi-hibiscus, such as flash memory, EEPROM memory, DRAM memory, or other memory structures with different volatility. In particular, this transistor structure can be used in the production of flash memory structures that require charge retention characteristics, so that the state of the transistor can be maintained for several yearsa

In order to simplify the reaction and etching of this part of the plurality of nanoparticle groups 21 shown in FIGS. 14 and 15, the initial growth or deposition of the nanoparticle group can be controlled so that 1 has only a few or no nanoparticle Groups need to be engraved by response or surname. By simplifying the reaction and etching steps, manufacturing efficiency can be improved. In order to control the formation of the nanoparticle group, the desired position can be reached

V. Description of the invention (25) Higher growth area of nanometer particles following a ^ x; ;;, can be formed on the through-passing: the electric layer 14 forms a region over the growth area corresponding to the tunneling Dielectric layer

Si-specific sections can be formed in the non-conducting dielectric layer 14. The nitrogen-containing section can promote the nucleation of higher nanoparticle groups for the development of nanoparticle groups on nitrogen-containing materials. In contrast, the development time, tunneling and growth of nano-sized silicon dioxide tunneling dielectric materials preferably occurs on those nitrogen-containing sections located below the tunneling dielectric layer 14. Figures 17-20 show the different steps in the selection of microparticles corresponding to 2 bits under the tunneling dielectric layer 丨 4 corresponding to the portion of the semiconductor substrate 10. FIG. 17 shows the part of FIG. 3: the nanometer 10 is formed, followed by the growth of a mask layer 52o: = substrate FIG. 18 shows the part of the part of the semiconductor substrate 10 of FIG. 17 followed by -The next steps, during which screenshots of the cover layer 52 are taken,-the patterned cover layer 5 22. A photoresist leather curtain = 2 to form a case can be exposed by the photolithography of the photoresist, and then the curtain-lifting condition. The second picture is therefore 'the remaining portion of the mask layer 522 is still maintained at the n . Below this part of 14, it corresponds to the need to grow the femto-dielectric layer. Therefore, the area of the part group of the mask layer 5 2 0 is removed. Because of the masked and unmasked part of layer 5 02. Fig. 19 is a cross-sectional view of the semiconductor substrate 10 shown in Fig. 18, which is followed by subsequent fabrication steps, in which the bulk substrate portion 5 2 2 is already in contact with those nitrogen-containing layers 50 The unmasked / part 2 remaining parts of the nutrient layer are still removed together (ie those

494572 V. Description of the invention (26) The part which is not under the remaining part 5 2 2 of the mask layer can be regarded as the part of the mask). The portion of the semiconductor substrate shown in FIG. 18 may be anisotropically etched to remove the unmasked portion of the nitrogen-containing layer that is not located below the portion of the mask layer 522, and then The remaining portion 522 of the cover layer can also be removed to produce the resulting structure shown in FIG. 19. The structure shown in FIG. 9 includes a nitrogen-containing layer section 5 24 (the mask portion of the nitrogen-containing layer), which corresponds to the position where the nano-particle group needs to grow on the through-dielectric layer 14. Those portions of the tunneling dielectric layer 14 which do not have a nitrogen-containing layer section below correspond to areas where the nanoparticle group is not desired to grow. Fig. 20 does not show the selective growth of the nanoparticle group on the structure shown in Fig. 19. As shown in the figure, 'nanoparticle groups are preferably grown on the nitrogen-containing layer section 524' so that some nanoparticle groups 52m can be formed thereon. However, due to the different development time and the less reactive characteristic of the tunneling dielectric layer 14, only a portion of the corresponding nanoparticle group combination will be directly formed on the tunneling dielectric layer 514. Therefore, when an operation is performed to remove a nanoparticle group that is not located under the gate region of the device, the number of nanoparticle groups that must be reacted and removed through the etching operation can be greatly reduced. FIG. 21 is an enlarged cross-sectional view of a plurality of nano-particles ^ 103 formed in a tunneling dielectric layer 102. Thereafter, the milliparticle group 103 and the tunneling dielectric layer 102 are deposited on the semiconductor substrate 100, and the substrate 100 may be exposed to the conditions. In the case of exposure to the surrounding conditions, the oxidation of the particle group 103 will sequentially cause some unwanted / contrast images: a nanometer: i ί ΐ ί ϊ system is considered to consume silicon during this oxidation Or its composite material reduces the effective size of the nanoparticle group. therefore

494572 V. Description of the invention (27) ---- The size of the oxygen 'di-nano-nanoparticles' can make it ymn-n-need to allow them to effectively become a charge, and deposit = pieces. Smaller nanoparticle groups are accepted by charge carriers due to the reduced cross-sectional area and other factors. Because of &, higher stylized voltages, times: ΐstyled time 'and less effective stylizations are all caused by smaller femophilic groups smaller than 25 angstroms in diameter. s Other potential unwanted effects due to oxidation increase the thickness of the tunneling dielectric layer 102, and install the police Hachioji J to Shigading = dental electrical continuity = order. It can be due to the nanoparticle group Oxidation of the substrate 100 occurs at 103 or / '. In particular, oxidation may cause additional silicon oxide between the nanoparticle group 103 and the tunneling dielectric layer 102, which may effectively increase the thickness of the tunneling dielectric 102. It is necessary to affect the overall electronic characteristics of the semiconductor device including the particle group 103. In order to reduce or eliminate the oxidation of the nanoparticle group 103, the subsequent steps may be performed after changing its general shape. FIG. 22 shows the nanoparticle group in the figure, followed by a subsequent process step, which describes the general shape of the nanoparticle group 103 to form a roughly nanosphere group. 104. This change in shape of the nanoparticle group may be generated by an annealing step or other operation, which may allow the original movement in the nanoparticle group to be balanced with the tunneling dielectric layer 102 below it. This step% "is illustrated in Figure 10 above. The resulting substantially hemispherical nanoparticle 5 104 has a reduced surface area that can be exposed during subsequent processing steps.

494572 V. Description of the invention (28) ~~~-Exposed to the surroundings. Furthermore, the diffusion of oxygen to the part of the nanoparticle group 104 that touches the lower tunneling dielectric layer 102 will be reduced, so the problem about the thickness of the tunneling dielectric layer can generally be avoided. A further advantage of the roughly hemispherical nanoparticle group 104 shown in FIG. 22 can be obtained by increasing the substantially hemispherical nanoparticle group 104 in contact with the through-dielectric layer 102. Surface area to achieve. This generally provides an increased cross-sectional area for the hemispherical nanoparticle population 104 to capture the charge carriers received from the channel region of the device below it during stylization. Further processing steps can be performed to limit degradation due to ambient exposure or other nanoparticle population degradation. FIG. 23 shows the structure of the group of FIG. 22, which is followed by a cladding step. This coating step forms a coating layer 106 on each group. Such a coating layer 106 may be made of two milligrams of nitrogen. Silicon nitride can be formed on the surface of the nanoparticle group 104 by exposing the nanoparticle group 104 to a nitriding environment at a high temperature. This surrounding environment may contain ammonia, nitrogen oxides, or other nitrogen-containing compounds, which can react with silicon in a ^ = manner. In a specific embodiment, a thin layer of ϊΙΐΐϊίΞΓ nanoparticle group does not require other reactants and is formed on the nanoparticle group. In the condition that ammonia gas can flow, Ge 7 " 60 /% degrees 〇 ^ 5 range is 7000 ~ 100 degrees Celsius, and the pressure standard range is 1 f must be noted, as described in Figure 2 i_27 The coating technology, which is applied to the performed nanoparticle group, has been on the surface. According to the co-proposed = memory device and method (,, mem〇ry

Page 494572 V. Description of the Invention (29) DEVICE AND METHOD FOR USING PREFABRICATED ISOLATED STORAGE ELEMENTS "), which has references and references in the above. Preferably, the formation of the coating layer 106 can be controlled so that the The thickness of the coating layer 106 is about 5 angstroms, or 10% of the diameter of the small nanoparticle group 104. In the case where the nanoparticle group 104 is a silicon nanoparticle group, it is used to produce the The nitriding process of the cladding layer 106 is basically self-limiting. Therefore, in a controlled environment, the growth of silicon nitride in the silicon nanoparticle group 104 can be self-relative to the nitriding temperature. Restriction. Basically, the nitrided periphery used to form the cladding layer 106 does not affect the tunnel dielectric layer 10 thereunder in a significant way. Therefore, the cladding layer 106 is used to form the cladding layer 106. The gasification step will not cause nitridation of the tunneling dielectric layer 102 below. Therefore, traps that can be generated in the cladding layer 106 are isolated from the substrate 100 underneath, and from adjacent femto. A coating of particle groups. Therefore, traps cause leakage between the nanoparticle groups Leakage is more likely to occur, due to the lack of charge degradation existing in the trap, and its charge storage characteristics into the nanoparticle group 104. Fig. 24 shows the portion of the semiconductor substrate of Fig. 23, which is then deposited The control dielectric layer 108. In the prior art system, it does not include a coating layer 106 to cover the nanoparticle group 104, and the formation of the control dielectric layer 108 may cause oxidation. The periphery of the nanoparticle group 104 is exposed, so by including the coating layer 106, 'the surrounding exposure of the nanoparticle fresh 104 due to oxidation' can reduce or eliminate oxidation or other deterioration. The diameter of the group 104 is not controlled, and an uncontrolled increase in the through-dielectric layer does not occur thereunder.

Page 35 494572 V. Description of the invention (30) In other specific embodiments, a protective nitride layer may be deposited instead of growing on individual millimeter, particle groups. Fig. 25 shows the nanoparticle group structure 'in Fig. 22, which is followed by a step of depositing a thin nitride layer 107. The nitride layer 107 can be deposited by a CVD operation using ammonia gas and two-gas silane. This CVD operation can be performed using LPCVD or UHVCVD technology. The deposition of the thin nitride layer 107 is preferably controlled, so the thickness of the thin nitride layer 107 can be limited. The required thickness of the thin nitride layer 107 is about 5 angstroms. This limited nitride thickness can limit or eliminate potential pitting, which can degrade the charge storage characteristics of semiconductor devices in manufacturing. '

The thin nitride layer 107 shown in FIG. 25 forms a barrier to oxygen, such that the nanoparticle group 104 below the tunneling dielectric layer 102 and the semiconductor substrate 100 below it Both can be protected against oxidation. Therefore, the possibility of increasing the thickness of the through-dielectric layer 102 can be reduced.

FIG. 26 shows the portion of the semiconductor substrate of FIG. 25, which then forms the control dielectric layer 108. During the formation of the control dielectric layer 108, the thin dielectric layer 107 can prevent the oxidation of the nanoparticle group 104, which can also eliminate the uncontrolled increase in the thickness of the tunneling dielectric layer 102. Possibility. ♦ In other embodiments, the control dielectric layer 108 may be formed of a high dielectric constant (high K) material, which does not require an oxygen concentration in the south to form. For this reason, oxidation of the nanoparticle group is less likely to occur. A metal oxide-containing control dielectric layer does not require a high concentration of oxygen to grow, unlike the stone oxide oxide control dielectric layer. Therefore, it is less likely to deteriorate the structure of the nanoparticle group. The high dielectric constant of metal oxides can also be used to reduce the required programming voltage, which is compared to silicon oxide controlled dielectric layers. metal

Page 36 494572 V. Description of the invention (31)-~~ Oxygen, such as hafnium oxide, hafnium oxide, silicidation, hafnium silicide, lanthanum aluminide ', and titanium alloy, can be used as the control dielectric layer. ^ A technique can be used to protect the nanoparticle group 1 (M and the semiconductors / 100 below from oxidation or other degradation, which can be accomplished by dividing the control dielectric formation into several steps. Figure 27 shows Figure 22 The half-body substrate portion is followed by these processing steps. = Initially, a thin layer of high-quality silicon oxide i 2 is formed on the nanoparticle ^^ and the through-dielectric layer 1G2 below it. The thin high-quality f oxide stone oxide can cause a small amount of oxidation of the nanoparticle group 104. However, the thickness of the thin layer insert = 0 mouth oxide stone oxide layer 2 is preferably limited, so This = the time required by the product is also limited. Because the period of the deposition is subject to the 2 system, the degradation of the nanoparticle group 104 is also limited by a tolerance. In a one-piece embodiment, the height of the thin layer is high. The high-quality silicon oxide 2 is formed to a thickness of about 唉. After the thin layer of high-quality silicon oxide 2 is formed, a silicon-rich oxygen f layer 114 is formed on the high-quality silicon oxide covering the thin layer. ^ = ^ = Silicon-containing silicon oxide layer 1 1 4 contains silicon atoms, which can be immediately linked to The oxygen atoms added under the chemical conditions. Therefore, try to move the silicon oxide layer 114 containing silicon and the oxygen atoms of the atoms combined with the nanoparticle group 104, which can be captured by the silicon atoms, so prevent The degradation of the nano-particles and the underlying semiconductor substrate material 100. In a specific embodiment, the silicon-rich silicon oxide layer 4 contains approximately f to 2% non-chemical amount of silicon (excessive Silicon). The thickness of the silicon-rich silicon oxide layer 4 can be in the range of 20 to 25 angstroms. It should be noted that this thickness can be

Page 37 4 ^ 4572 V. Description of the Invention (32) Changes to provide proper protection of the nanoparticle group 104 below according to the surroundings to which the substrate will be exposed. The thickness of the silicon-rich silicon oxide layer 114 can be determined based on the potential oxidation that can occur during subsequent process steps and the amount of excess silicon contained in the material used to form the silicon-rich oxide layer 114. . Therefore, a coordination exists between the concentration of excess silicon in this layer and the degree of oxidation expected to occur during subsequent process steps. It is necessary to ensure that most of the excess silicon in the silicon-rich f-fossil layer 114 will be combined with oxygen atoms to ensure that the conductive quality of the silicon-rich silicon oxide layer 114 is eliminated. After the deposition of the silicon-rich silicon oxide layer i4, the remaining portion of the control dielectric layer may be formed by the growth of an additional high-quality silicon oxide layer 116 that covers the previously formed stack. The growth of the high-quality silicon oxide layer i6 will basically expose the rest of the structure to the surrounding conditions. However, as described above, the silicon-containing silicon oxide layer can help prevent oxidation of the nanoparticle group 104 during such peripheral exposure. The covered high-quality oxide layer 116 may be formed by a high-temperature operation, such as those described above for the above / oxygenation step. The thickness of the ytterbium-quality silicon oxide layer 116 may be on the order of 65 angstroms, or it may be determined to provide an overall control dielectric layer thickness of approximately 100 angstroms. It must also mean that according to the cladding technology described in FIGS. 23 and 24, and the protective layer technology described in 26, including the silicide-rich layer described in FIG. 27, using other control gate dielectric layer images It is metallized and can be spherical or hemispherical nanoparticle groups. In this case, ^ the figure shows = the coating and stacking of the generally hemispherical nanoparticle group. 4 For professionals in this technology, it can be understood that this technology can also be a better solution.

494572 V. Description of the invention (33) Shaped nano particle group or other shaped nano particle group. Furthermore, those skilled in the art can understand that the combination of different technologies described above can be used to protect the nanoparticle group and the substrate below it from degradation caused by exposure to oxidation or other surrounding conditions. In order to further promote the optimization and control of the technology described herein, the formation of the tunneling dielectric layer, the nanoparticle group, and the control dielectric layer can all be completed in a controlled environment. The substrate wafer will not be exposed to surrounding conditions during and between these process steps. This controlled environment is shown in Figure 28, which can represent a cluster of tools. As shown in FIG. 28, a dielectric module 208 can be used to grow or deposit the tunneling dielectric layer, or to form the control dielectric layer, and then form the nanoparticle group on the surface of the tunneling dielectric layer. As shown in the figure above, the dielectric module 208 is a module that includes the cvd of the nanometer particle group gig in the isolated area 20 6 °. Preferably, the isolated area 2 10¼ is for a controlled The environment, for example, a vacuum close to 5 ΐ Ξ ί: Π8 can not give up the two D modules 2 ° 6 between the Japanese substrate and the Japanese yen, and will not be exposed to the surrounding conditions. The substrate, which can be held in an 'environment, comes after the step of controlled microparticle populations continued in the cluster tool. The summer solstice is forming a disparate benefit in performing all these steps without hesitation. In the past, the ability to prevent exposure to the conditions provided a pair of places to first prevent the tunneling dielectric layer from being exposed, and reduce the chance that pollutants will form on the dielectric layer; any reduction in such pollutants is iiUi adverse effects, so this

ιΐϋΐι Page 39 494572 V. Description of the invention (34) Secondly, by preventing the nanoparticle group from being exposed to the surrounding conditions, it can avoid degradation of the nanoparticle group due to oxidation. Therefore, after the formation of the nanoparticle group, the passivation through the above-mentioned nitridation occurs immediately, so the degree of accumulation of the nanoparticle group can be ensured. A control module 204 controls the growth of the dielectric layer in the dielectric module 208 and the growth of the nanoparticle group in the nanoparticle group growth module 206. This control may include adjustments to source gases 202 and 212 to achieve the required flow rate and pressure. Other controls may include adjusting the temperature within the isolated area 2 1 0. The present invention improves the controllability of the nanoparticle group to allow the nanometer to be adjusted. The required tunneling dielectric layer is as described above. However, the scope of this patent application is therefore to amend the regulations regarding the specific cases are already above, and any available for the use of the structure to allow the technical nature of the micro-particle group to achieve electronic characteristics. Therefore, the specifications and drawings of the present invention, which are specialized in the art, can be included in the description of the specific embodiments of the present invention. But cause any good

Formed using LPCVD and UHCVCD deposition techniques. Using the techniques described here, high-density nanoparticle populations can be maintained. This control of size, distribution, and general uniformity can be refined; devices containing a nano-particle group floating gate structure can therefore be produced to include very thin and lean, low-power and high-speed operations. The invention has been illustrated by specific embodiments. One can understand that various modifications and changes can be made without departing from the following claims. It is considered to be illustrative and not restrictive, all within the scope of this description.

^ Benefits, other advantages and problem solving; 5 The benefits, advantages, and problem solving methods ’The advantages or solutions become more obvious 夭

494572 V. Description of Invention (35) The document is not intended to be the key, required, or essential feature or element of any or all patent applications. As used herein, the word π includes π, or other variations thereof, to cover a non-exclusive inclusion, such as a process, method, article, or device, which contains a series of elements, and not just those elements , But may include other components, methods, articles, or devices not explicitly listed or embedded in this process.

Page 494572 Illustration in brief

Page 42

Claims (1)

494572 I 6. Application scope 1. A method for forming a nanoparticle group, comprising the following steps: providing a substrate; forming a tunneling dielectric layer on the substrate; forming a nitrogen-containing layer on the tunneling dielectric Layer, wherein the thickness of the nitrogen-containing layer is less than 10 angstroms; and forming the nanoparticle group on the nitrogen-containing layer. 2. The method according to item 1 of the patent application scope, wherein the nitrogen-containing layer is a layer of nitrogen and nitrogen. 3. A semiconductor device comprising: a semiconductor substrate having a source and a drain with a channel region therebetween; a tunneling dielectric layer covering the channel region; a nitrogen-containing layer in the tunnel Over the dielectric layer, wherein the nitrogen-containing layer has a thickness of less than 10 angstroms; a plurality of silicon nanoparticle groups directly on the nitrogen-containing layer; a control dielectric layer on the silicon nanoparticle group And a gate above the control dielectric layer. 4. The semiconductor device as claimed in claim 3, wherein the nitrogen-containing layer is a nitride layer. 5. A method of forming a nanoparticle group, comprising the steps of: providing a substrate; forming a tunneling dielectric layer on the substrate; exposing the tunneling dielectric layer to a reagent; and after the exposing step To form the nanoparticle group at the tunneling dielectric Page 43 494572 Sixth, the scope of patent application is above the level. 6. The method of claim 5 in which the reagent is hydrofluoric acid. 7. A method of forming a storage device, comprising the steps of: providing a substrate; forming a tunneling dielectric layer over the substrate; forming a nanoparticle group over the tunneling dielectric layer; forming a A thin layer of nitride is on the nanoparticle group; a control dielectric layer is formed on the nanoparticle group; and a conductive layer is formed on the control dielectric layer. 8. The method according to item 7 of the patent application range, wherein the nitride of the thin layer is formed on the nanoparticle group by flowing at least one of ammonia gas, N20 and NO, and it does not require other reagents. 9. A method of forming a storage device, comprising the steps of: providing a substrate; forming a tunneling dielectric layer over the substrate; forming a nanoparticle group over the tunneling dielectric layer; forming a control A dielectric layer is on the nanoparticle group, wherein the control dielectric layer comprises at least one of zirconia, hafnium oxide, alumina, lanthanum oxide, silicon-rich silicon oxide and titanium oxide; and a conductive layer is formed on Over the control dielectric layer. 10. The method according to item 9 of the patent application scope, further comprising a step of nitriding the surface of the nanoparticle group without nitriding the tunneling dielectric layer. 11. A storage device comprising: O: \ 71 \ 71076.ptd Page 44 494572 6. The scope of patent application: a substrate; a dielectric layer on the substrate; a nanoparticle group on the tunneling dielectric layer; a control dielectric A layer on top of the nanoparticle group, wherein the control dielectric layer includes at least one of zirconia, hafnium oxide, alumina, lanthanum oxide, silicon-rich oxide fragments and oxidative convergence; and a conductive layer on the control medium Above the electrical layer. 12. For example, the storage device according to the scope of the patent, further comprising a thin layer of nitride on the nanoparticle group. 1 3 · A method for forming a group of nano particles in Shixi, comprising the following steps: providing a substrate; forming a 1¾ through dielectric layer on the substrate; placing the substrate with the tunnel dielectric layer on a substrate In a chemical vapor deposition reaction chamber; heating the substrate with a hidden dielectric layer to a temperature not exceeding 600 ° C, and forming a silicon nanoparticle group by flowing a silicon-containing gas in the tunnel Above the dielectric layer, its rate is greater than or equal to about 50 SCCM, its partial pressure is less than or equal to about 200 mTorr ·, and its time is greater than 30 seconds. 14. The method according to item 13 of the scope of patent application, wherein the tunneling dielectric layer and the m group are formed in a cluster tool, and the substrate is located in a controlled environment, which is continuously From the step of forming the tunneling; I electrical layer, until the step of forming the silicon nanoparticle group Page 45 494572 VI. Patent application scope '~ 15_ — A method for forming a semiconductor nanoparticle group, which includes the following steps to provide a formation and place in the application chamber; forming a group of the semiconductive gas by flow only A substrate of a conductive gas; a tunneling dielectric layer moving a mixed gas into the nanoparticle group at the tunneling dielectric layer, the group comprising: a semiconductor-containing gas; and the substrate above the substrate being inserted into the chemistry The gas-mixing system mixed in a chemical vapor deposition reverse vapor deposition reaction chamber is selected from a mixed semiconductor gas only combined with an inert flow rate greater than or equal to about 50 and a force less than or equal to about 200 mTorr. 1 6 · A method for forming a nanoparticle group, comprising the following steps: providing a substrate; forming a tunneling dielectric layer in the gas having a tunneling dielectric layer, wherein the semi-SCCM-containing gas, and a portion thereof The partial pressure is placed in the chamber; and the substrate on the substrate flows a gas into the first stage to form a plurality of key crystal nuclei; the gas flows in the second stage as the nanoparticle group. 1 7 · If the method of applying for patent No. 6 and the method for growing during the first stage, the chemical vapor phase in a chemical vapor deposition anti-chemical vapor deposition reaction chamber, the plurality of key crystal nuclei are formed into: The deposition reaction chamber operates at Page 46 494572 VI. Patent application scope First temperature; and during the second stage, the chemical vapor deposition reaction chamber is operated at a second temperature, wherein the first temperature is less than the second temperature. 18. The method according to item 16 of the patent application scope, wherein: during the first stage, the chemical vapor deposition reaction chamber is operated at a first partial pressure; and during the second stage, the chemical gas The phase deposition reaction chamber is operated at a second partial pressure, wherein the first partial pressure is greater than the second partial pressure. 19. The method according to item 18 of the scope of patent application, wherein: during the first phase, the chemical vapor deposition reaction chamber is operated at the first temperature; and during the second phase, the chemical vapor deposition The deposition reaction chamber is operated at a second temperature, wherein the first temperature is lower than the second temperature. Page 47