WO2001059573A1 - Dispositif de traitement de l'information et circuit integre a semi-conducteurs - Google Patents

Dispositif de traitement de l'information et circuit integre a semi-conducteurs Download PDF

Info

Publication number
WO2001059573A1
WO2001059573A1 PCT/JP2000/000648 JP0000648W WO0159573A1 WO 2001059573 A1 WO2001059573 A1 WO 2001059573A1 JP 0000648 W JP0000648 W JP 0000648W WO 0159573 A1 WO0159573 A1 WO 0159573A1
Authority
WO
WIPO (PCT)
Prior art keywords
memory
access
data
master
circuit
Prior art date
Application number
PCT/JP2000/000648
Other languages
English (en)
Japanese (ja)
Inventor
Seiji Miura
Kazushige Ayukawa
Takao Watanabe
Hiromi Watanabe
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to JP2001558836A priority Critical patent/JP4549001B2/ja
Priority to PCT/JP2000/000648 priority patent/WO2001059573A1/fr
Priority to AU2000223268A priority patent/AU2000223268A1/en
Publication of WO2001059573A1 publication Critical patent/WO2001059573A1/fr

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G06F13/1631—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests through address comparison
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Definitions

  • the present invention relates to an information processing apparatus including a memory block having a plurality of memory banks shared by a plurality of masters, and to a semiconductor integrated circuit including a memory control circuit which receives access from the plurality of masters and controls the memory block.
  • a typical information processing device includes a 3 'CPU (Central Processing Unit) and a DRAM (Dynamic Random Access Memory) connected to the CPU via a DRAM control circuit to store desired data. ing.
  • the CPU sends a read command to the DRAM control circuit, and the DRAM control circuit decodes the command and controls reading of desired data from the DRAM.
  • SDRAM sink DRAM
  • a read line in the DRAM is selected, and data of one row on this word line is transferred to a sense amplifier, amplified, and held.
  • a read instruction and a column address are sent (READ).
  • the column switch is selected by this instruction and the column address, and the data held by the sense amplifier is read.
  • the operation of selecting a word line requires a relatively long time, but once data on the read line is held in the sense amplifier, access to the same read line, that is, within the same page When data is accessed, data can be read in a short time.
  • the currently selected word line is once deselected and a new word line is deselected. Since it is necessary to select a word line, it takes a long time to read data.
  • a subject accessing the DRAM is not limited to the CPU described above, and may include a hard disk controller, an MPEG decoder, a graphics processing circuit, and the like.
  • the hard disk controller, including the CPU can be the main unit for accessing the DRAM, and each is called a master.
  • [Reference 1] and [Reference 2] are known as references indicating an information processing apparatus including a plurality of masters.
  • [Reference 1] describes a technique for allocating a specific memory bank to a specific master in order to increase the efficiency when multiple masters (CPU and I / O controller IOC) access multiple memory banks.
  • [Reference 2] is to hold data for read / write between each master and each memory bank in order to arbitrate access competition between multiple masters and multiple memory banks.
  • a technique of providing a buffer is described.
  • the inventors of the present application focused on not only arbitration of access competition but also the importance of control according to the characteristics of the master. In other words, even if the access from the CPU to the DRAM is random, is there. In other words, the CPu access has the property that the currently accessed address and the addresses near it are likely to be accessed again frequently in the near future. Therefore, access from the CPU to the DRAM frequently occurs within the same page.
  • the access address of the hard disk controller has less locality.
  • an interrupt from the keyboard or mouse causes access to the DRAM from the hard disk controller, reads the data in the DRAM, and stores it in the hard disk. Once the data in the DRAM is saved, there is no need to read the data from the DRAM again unless an interrupt from the keyboard or mouse occurs. Therefore, it is extremely unlikely that the hard disk controller will frequently access the same address again and read data in the near future.
  • the MPEG decoder sequentially expands the data compressed on a CD-ROM or the like within a certain time and writes the data to the DRAM. Once the compressed data has been decompressed, there is no need to decompress the same data again, so it is extremely unlikely that the MPEG decoder itself will frequently access the same address again in the near future.
  • the typical means of the present invention are as follows.
  • the control mode is switched to control the memory corresponding to the master, and the memory is controlled. More specifically, based on the identification signal of each master, the power of closing the memory page at the beginning of access and the switching operation of whether or not to close it are performed, and according to this, the page opening / closing operation is performed at the end of access. Control the memory.
  • a page means one of a plurality of word lines in a specific memory bank, and a page open means one page while a word line in a specific memory bank is selected. This corresponds to the fact that the data of (1) is held in the sense amplifier (bank active state).
  • page closing means that the word lines in a memory bank are not selected and any word line can be selected immediately when a word line selection request is issued to the memory bank. Yes (bank precharge state).
  • FIG. 1 shows a memory control circuit MCTL according to one embodiment of the present invention.
  • FIG. 2 is an overall configuration diagram of an information processing apparatus to which the present invention is applied.
  • Figure 3 shows an example of the instruction set of each master.
  • FIG. 4 is an example of a block diagram of the memory block MEM of FIG.
  • FIG. 5 is an example of a configuration diagram in a bank constituting the block diagram of FIG.
  • FIG. 6 is a diagram illustrating an example of control of the memory block MEM in FIG.
  • FIG. 7 is a diagram illustrating an example of control for setting data in the shift register of FIG.
  • FIG. 8 is a flowchart showing the operation of the control mode switching circuit of FIG. FIG.
  • FIG. 9 is an example of a diagram showing an address selection signal and an address corresponding to each memory bank set by the intra-page access determination circuit of FIG.
  • FIG. 10 is a flowchart showing operations of the instruction generation circuit and the address generation circuit of FIG. 1 at the time of read and store instructions.
  • FIG. 11 is a flowchart showing the operation of the instruction generation circuit and the address generation circuit of FIG. 1 at the time of a refresh instruction.
  • FIG. 12 is a diagram showing the latency of DRAM for each access.
  • FIG. 13 is a diagram showing an example of a temporal transition of a master accessing the DRAM.
  • FIG. 14 is a waveform chart showing an example of an operation for access from the CPU.
  • FIG. 15 is a waveform chart showing an example of an operation for an access from the CPU.
  • FIG. 16 is a waveform diagram showing an example of an operation for access from the hard disk controller HDC.
  • FIG. 17 is a waveform chart showing an example of an operation for access from the refresh control circuit.
  • FIG. 18 is a diagram showing another embodiment of the memory control circuit of the present invention.
  • FIG. 19 is a diagram showing another embodiment of the information processing apparatus of the present invention.
  • FIG. 20 is a diagram showing another embodiment of the information processing apparatus of the present invention.
  • FIG. 21 shows another embodiment of the information processing apparatus of the present invention.
  • circuit elements constituting each functional block of the embodiment are not particularly limited, they are formed on one semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as CMOS (Complementary MOS Transistor). You.
  • CMOS Complementary MOS Transistor
  • FIG. 2 is a basic configuration diagram of an information processing apparatus using the present application. This consists of a first master CPU4, a second master hard disk controller (HDC) 5, an access arbitration circuit (ARB) 2 for arbitrating access from the CPU and HDC, and a plurality of Controls the refresh operation of the memory block (MEM) 3 composed of banks, the memory control circuit (MCTL) 1 that controls MEM by signals from the ARB, the hard disk (HD) 50, and the memory block 3. It consists of a refresh control circuit (RFC) 6. RFC is the third master.
  • the hard disk controller HDC controls data transfer between the hard disk 50 and the memory block MEM.
  • the MEM is composed of four memory macros, the 0th memory macro 3M0 and the third memory macro 3M3. Each memory macro is composed of four memory banks, and each memory bank has a sense amplifier. This information processing device operates in synchronization with the clock CLK.
  • Fig. 3 (a) shows the instruction set of the CPU.
  • the instructions from the CPU to the access arbitration circuit ARB are the CPU instruction signals RW 0 [0] to RWO [3] (corresponding to RWO (4 bits) in Fig. 2). ).
  • the load instruction LD is an instruction for reading data from the DRAM.
  • the store instruction ST is an instruction for writing data to the DRAM.
  • the set register SR is an instruction for setting data in shift registers 1a, lb, and 1c in the DRAM control circuit 1 in FIG. 1 described later.
  • Reserve RV is a reserve instruction to add a new instruction. No operation NO P is an instruction that does nothing.
  • FIG. 3B shows the instruction set of the hard disk controller HDC, which is represented by the HDC instruction signals RW 1 [0] to RWO [2] (corresponding to RW 1 (2 bits) in FIG. 2).
  • LD, ST, and NOP are instructions having the same role as that described in FIG.
  • Fig. 3 (c) shows the instruction set of the access arbitration circuit ARB.
  • the instructions from the ARB to the memory control circuit MCTL are ARB instruction signals I COM [0] to I COM [3] (IC OM in Fig. 2). (Corresponding to (4 bit)).
  • R and W are a read instruction and a write instruction, respectively, and are issued corresponding to the LD and ST of the CPU and HDC.
  • the access end instruction EOA is an instruction indicating the end of access.
  • the refresh instruction RF is an instruction for performing a MEM refresh operation. RF is issued in response to a refresh request from the refresh control circuit RFC, which is the third master.
  • S R and NO P are instructions having the same role as the instruction already described with reference to FIG.
  • FIG. 3 (d) shows the instruction set of the memory control circuit MCTL.
  • the instruction from MCTL to MEM is MC TL instruction signals MC OM [0] to MC OM [2] (M COM (3 bit
  • ⁇ BA is a memory block of MEM's special memory bank ⁇ This is an instruction to select a line.
  • the column read instruction RD is an instruction to read data on a selected memory cell of a specific memory bank of MEM.
  • the c column write instruction WT is an instruction to write data on a selected memory cell of MEM.
  • the precharge command PRE deselects the selected word line and closes the page.
  • NOP is an instruction that means do nothing as in Fig. 3 (a).
  • the access request signal REQ0 is set to Low.
  • a load instruction from RW0, a CPU identification signal from MAD0, and an address from ADD0 are output to the access arbitration circuit ARB.
  • the hard disk controller HDC has a 512-byte buffer inside, and when loading data of the memory block MEM into this buffer, the access request signal REQ 1 is set to Low. At the same time as this access request, a load instruction is output from RW1, an identification signal of HDC is output from MAD1, and an address is output from AADD to ARB.
  • the data stored in the memory block MEM is likely to be lost unless a refresh operation is performed when DRAM is used.Therefore, the refresh request is periodically sent from the refresh control circuit RFC. There is a need to do.
  • REG 2 is set to Low, and at the same time, a refresh command, MAD 2 power, etc. are output from RW 2 to the RFC identification signal, and ADD 2 is output to address ARB.
  • Access arbitration circuit The ARB monitors whether an access request from the CPU, an access request from the HDC, and an access request from the RFC have been received, and prioritizes the access requests from each master. And allow access from one master. The priority can be changed according to the type and number of masters constituting the information processing device. This In the case of, the access from the RFC is the first priority because it is the control of the refresh. Access from the HDC is interrupt processing, so it has the second priority, and access from the CPU has the last third priority.
  • Access arbitration circuit When the ARB sets ACK 0 to Low and permits an access request for a load instruction from the CPU, the CPU identifies the CPU identification signal from I MAD, the read instruction from I COM, and the address from I ADD. Output to The MCTL receives the signal from the ARB and controls the MEM.
  • FIG. 4 is a configuration example of a memory block MEM used in the present invention.
  • 3MO, 3M1, 3M2, and 3M3 indicate memory macros, respectively.Each memory macro consists of four memory marks 3B0, 3B1, 3B2, and 3B3. It is configured.
  • the data input buffer circuit IBUF and the output buffer circuit OBUF are shared between the four macros, and that the macros are integrated on one chip, although not particularly limited.
  • MEMs can also be configured with memory modules that use a well-known SDRAM or similar command at each of the memory mask ports and operate using multiple memory modules.
  • Fig. 5 shows an example of the configuration of DRAM in one memory bank
  • Fig. 6 shows the operation of MEM.
  • Bank instructions BA and MAD from MC OM row address RW 0 (10 bits of MADD [13: 4]), macro address MC 0 (2 bits of ADD [1: 0]), bank address
  • RW 0 10 bits of MADD [13: 4]
  • macro address MC 0 (2 bits of ADD [1: 0]
  • bank address When dress BK 0 (two bits of MADD [3: 2]) is input, one of 16 banks is selected by macro address MC 0 and bank address BK 0, and low address RW 0
  • the selected memory van One of the row and line WLs in the row decoder of the row decoder is selected, and the data of the memory cell for one page of 4096 bits is read out.
  • the data is transferred to the sense amplifier 303 via the two bit line pairs (BL0-0 and BLB0-0 and BL256-15 and BLB256-15), and is held.
  • the sense amplifier is a latch-type sense amplifier in which two CMOS inverters are cross-coupled, and has an amplification and a latch function. In this sense, the sense amplifier can be regarded as a data latch circuit.
  • the sense amplifier is not limited to the above-mentioned latch type sense amplifier, and may be a circuit for separating the amplification section and the latch section of the sense amplifier.
  • the read command RD from MCOM and the column address CAO (4 bits of MAD D [7: 4]) from MADD and the macro address MCO for the bankactive instruction are used.
  • FIG. 1 shows a memory control circuit MCTL of the present invention.
  • This circuit identifies the master that accesses the memory block MEM, and switches the control mode for controlling the MEM corresponding to the master to the master or the MEM.
  • the control mode switching circuit (C REG) 101 that dynamically performs when these accesses occur.
  • an in-page access judgment circuit (PH) 102 for judging whether the already selected row address matches the address of the currently generated access, and a control instruction to the MEM are generated.
  • an input / output data control circuit (DQB) 105 for controlling input / output data is included.
  • the control mode switching circuit CREG outputs the output signal Id from the shift register la, the output signal 1e from the register 1b, and the output signal 1e from the register lc according to the shift registers la, lb, and lc, and the master identification signal I MAD. It comprises a selection circuit 1 g for selecting the output signal 1 f and a latch circuit 1 i for latching the output signal 1 h of the selection circuit 1 g.
  • Each of the shift registers 1a to 1d is a shift register for setting a necessary flag signal to select a control mode for each master.
  • 1 a can set the flag signal of the CPU
  • 1 b can set the flag signal of the hard disk controller HDC
  • 1 c can set the flag signal of the refresh control circuit RFC
  • 1 d can set the flag signal of other masters.
  • Figure 7 shows the operation of setting the CREG shift registers 1a to 1d and the flag.
  • the CPU flag signal High to the shift register la the HDC flag signal Low to the shift register 1b
  • the RFC flag signal Low to the shift register 1c and other masters This shows the operation when the flag signal ow is set to the shift register 1d.
  • the set register instruction SR is input to the memory control circuit 1 through ICOM.
  • the ICOM The 0th bit signal is the flag data FLAG-D set in the shift register.
  • the first set register instruction sets the flag data to high, the second set register instruction sets low, and the third set register instruction sets low.
  • the fourth set register instruction it is set to Low and input to the memory control circuit.
  • High is set to 1 d.
  • the data of I d is transferred to lc, 1 c is set to High, and I d is set to Low.
  • 1 c is set at the next rising edge of the clock.
  • Data is transferred to 1b, 1b is set to High, 1d data is transferred to 1c, 1.
  • Is set to ow and la is set to Low. By shifting the flag data in this way, 1 & 111111, lb is Low, and 1 finally. Is set to 1 ⁇ 0, and 1 d is set to Low.
  • FIG. 8 is a flowchart showing the operation of the control mode switching circuit CREG.
  • I NPUT M-ID enclosed by a square indicates an operation for inputting a master identification number
  • WAITM-ID indicates an operation for waiting for input of a master identification number. . ?
  • the explanation is given with 11 as the identification number, 0 for the hard disk controller HDC, 1 for the refresh control circuit RFC, and 3 for the other masters.
  • the flag signal High of the shift register 1a passes through the output signal 1e, and the selection circuit 1 i is selected, output to the output signal 1 j of the selection circuit 1 i, is latched by the latch circuit 1 k, and the output LMS becomes H igh.
  • HD C identification signal 1 is When input to the MCTL through AD, the flag signal Low of the shift register 1b passes through the output signal 1f, is selected by the selection circuit 1i, is output to the output signal 1j of the selection circuit 1i, and is output to the latch circuit 1k. Low is latched at this time, and its output LMS becomes Low.
  • the lag signal Low of the shift register 1c passes through the output signal 1g, and the selection circuit 1i Is output to the output signal 1 j of the selection circuit 1 i, and Low is latched by the latch circuit 1 k, and the output LMS becomes Low.
  • the values of shift register 1a, lb, lc, and Id can also be set by providing dedicated setting terminals externally. Also, the values of the shift registers la, 1b, 1c, and 1d can be set by connecting to the power supply or ground with a metal layer or diffusion layer when integrated on a silicon. This is a so-called metal option.
  • Figure 9 shows the row address selection PS signal (PS) and row address (ROW-ADD) corresponding to each memory bank bank number (BANK NO.) Of each memory macro number (MACRO NO.) Set in PH. ).
  • PS row address selection
  • ROW-ADD row address selection signal
  • HT is an intra-page access determination signal indicating whether or not the current access has occurred with respect to the selected row address, that is, whether or not the access is to the same page.
  • the access judgment signal in the HT page When the access judgment signal in the HT page is High, it indicates an access within the same page as the selected address, and when Low, the access or the row of a page different from the selected row address is performed. Indicates that the access has not been selected.
  • HT Low, selected by current access 1
  • the already set row address of one bank is always replaced with the row address of the current access.
  • HT High, the lower address does not change.
  • I ADD is composed of an 18-bit address, and is not particularly limited.
  • the 17th to 8th bits of the highest order are the MEM low address and the 7th bit.
  • the 6th to 6th bits are the MEM memory non-address
  • the 5th to 4th bits are the MEM memory macro address
  • the 3rd to 0th bits are the MEM column address.
  • the memory macro address, memory bank address and row address in the I ADD address are input to the in-page access determination circuit PH.
  • a PS signal corresponding to one memory bank selected by the memory macro address and the memory bank address is output to the instruction generation circuit CGEN and the address generation circuit AGEN.
  • the PS signal is Low, it is set to 1 at the next rising edge of the clock.
  • the access end command is input from ICOM and LMS is 0, the selected PS signal is set to 0.
  • HT intra-page access determination signal
  • Figure 10 shows an example of the operation of the instruction generator CGEN and the address generator AGEN when a read instruction is input.
  • ⁇ For £ 1 ⁇ and 0 £ ⁇ , read command from 1 COM, address from IADD, access judgment
  • the intra-page access determination signal HT and the row address selection signal PS, and the LMS from the control mode switching circuit 101 are input from the path 102.
  • CGEN and AGEN first perform a row operation. Specifically, CGEN first outputs a bank active instruction B A, and AGEN outputs a row address, a memory macro address, and a memory bank address to MEM. After two cycles, perform column operation. Specifically, CGEN outputs the read instruction RD, and AGEN outputs the column address, memory macro address, and memory bank address to MEM, and reads the data.
  • the current access is to access a row address different from the already selected row address, that is, to a different page. Indicates access. To access a different page, first perform a precharge operation, deselect the previously selected row address, then perform a row operation and select a new row address. After two cycles, perform column operation and read data.
  • the current access indicates an access within the already selected low address, that is, an access within the same page. In this case, no row operation is required, and a column operation is performed to read data.
  • FIG. 11 shows an example of the operation of the instruction generation circuit CGEN and the address generation circuit AGEN when a refresh instruction is input.
  • CGEN and AGEN refresh command from ICOM, address from IADD, in-page access determination circuit 102 From in-page access determination signal HT, row address selection signal PS, and control mode switching circuit 101 LMS is entered.
  • CGEN and AGEN When the row address selection signal PS is Low, CGEN and AGEN perform a row operation first in normal access. Specifically, CGEN first outputs a bank active instruction BA to AMEM, and AGEN outputs a row address, a memory macro address, and a memory bank address to MEM.
  • the current access is to access a row address different from the already selected row address, that is, an address to a different page. Indicates access. To access a different page, first perform a precharge operation, deselect the previously selected row address, then perform a row operation and select a new row address.
  • the current access indicates an access within the already selected row address, that is, an access within the same page. At this time, do nothing.
  • Figure 12 shows the latencies for the same page access, normal access, and different page access described above.
  • 3 for write latency 1 for write latency, 5 for normal access
  • 3 for write latency 7 for different page access
  • 7 for read latency 7 for write latency .
  • FIG 13 shows that after power-on (Tl (INIT)), access from the CPU (T2 (CPU)), access from the hard disk controller HDC (T3 (HDC)), and access from the CPU (T3 (HDC))
  • Tl (INIT) after power-on
  • T2 (CPU) access from the CPU
  • HDC hard disk controller
  • T3 (HDC) access from the CPU
  • PW in the Tl (INIT) period indicates power-on and initial operation after power-on.
  • Each of C O to C m in the T 2 (CPU) period indicates one access from the CPU
  • H 0 in the T 3 (HDC) period indicates one access from the HDC.
  • the access from the CPU keeps the MEM read line selected at the end of the access, that is, keeps the page open, and the access from the HDC and the refresh control circuit MCTL
  • the flag data was set in the shift registers la, lb, 1c, and 1d so that the page was closed at the end of the access.
  • FIGS. 14 to 17 show specific examples of the operation.
  • I MAD is the identification number of the master
  • I COM corresponds to the instruction in FIG. 3 (c).
  • the NO P instruction is abbreviated as N.
  • I ADD represents an access address
  • AD 0 represents a state where a predetermined address signal is input
  • DC (Don't Care) represents a state where an address is undefined.
  • MADD also indicates the access address to MEM.
  • the CPU access is not performed by closing the page at the end of the access, and the page is kept open.
  • the read latency is 3, and the MEM can operate faster than normal operation.
  • Figure 16 shows the H0 access during the T3 (HDC) period when the access is changed from the CPU to the hard disk controller HDC.
  • HDC T3
  • FIG. 16 shows the operation when a page error occurs in the first access of H0. Since each memory bank of the memory block MEM has a page opened for access by the CPU, access from the HDC will almost always be to a different page.
  • the read latency of the first access in Figure 16 is 7. Thereafter, the access by the hard disk controller HDC occurs within the same page, and a total of 16 accesses are performed to read 512 bytes, and the latency becomes 22.
  • the precharge operation is performed and the page is closed.
  • the initial data read latency is two latencies, that is, 20 ns' slower, but when the HDC writes 512 bytes of data to the hard disk, it takes several ms. The delay of 20 ns is not a problem in operation.
  • the page is kept open by the access from the hard disk controller HDC, and if the access to the bank holding this state occurs by the CPU, Mostly access to different pages.
  • the read latency of the access from the CPU becomes 7, which is two latencies slower than the normal access, and this latency directly affects the operation of the CPU. Therefore, according to the present invention, for an access from the HDC, by closing the page at the end of the access, an access from the CPU after this access occurs in a memory bank previously accessed by the HDC. Also, latency does not increase.
  • FIG. 17 shows an operation timing diagram when a refresh request is issued from the refresh control circuit RF.
  • RF refresh control circuit
  • MCOM terminates with PRE. That is, the same address is not accessed in the next access of RFC after 4 ⁇ s, so it is preferable to close the page.
  • the latency does not increase.
  • the specific form of the information processing apparatus of the present invention applied to a semiconductor chip is as follows. First, CPU, HDC, RFC, etc. There is a form in which each of the master and the ARB, MCTL, and MEM are formed on individual semiconductor chips.
  • MEM there are two types of MEM: a case in which all DRAMs are formed on one chip, and a case in which MEMs are formed by a plurality of DRAM chips.
  • a well-known SDRAM or the like can be used for the DRAM chip.
  • a second mode there is a mode in which three functional blocks of RFC, ARB, and MCCTL are integrated on one chip as a memory control chip.
  • Other CPUs are formed on individual semiconductor chips as in the first embodiment.
  • MCTL and MEM are formed on one chip. Others are the same as in the first embodiment.
  • integrating the CPU, RFC, ARB, MCCTL, and MEM on a single semiconductor chip is also effective for small-scale systems. Even in this case, there is no particular limitation, but the master to be an external option such as HDC is a separate chip. If HDC is the most essential system, it can be integrated as needed.
  • FIG. 18 shows an embodiment of the memory control circuit 100 of the present invention, which is obtained by adding a refresh counter 106 for generating a refresh address to the embodiment shown in FIG.
  • the address selection circuit 107 selects an address from the refresh counter and outputs the address to the in-page access determination circuit 102 and the address generation circuit.
  • the refresh counter performs a refresh address renewal every time a refresh instruction is input.
  • FIG. 19 shows an information processing device using the memory control circuit 100. It arbitrates access from CPU, HDC, CPU and HDC
  • the arbitration circuit 2 includes a memory control circuit 1 for controlling the MEM in accordance with a signal from the arbitration circuit 2, a hard disk 50, and a refresh control circuit 6 for controlling a refresh operation of the MEM.
  • the CPU, HDC, and refresh control circuit 6 do not have the MAD identification signal shown in FIG. 2, and the ports REQ0, REQ1, and REQ2 are connected to the access arbitration circuit.
  • the access arbitration circuit identifies the master at the REQ O, REQ 1, and REQ 2 ports, receives requests from each master, and when access is granted, converts the port information to the master identification signal I MAD I do.
  • a refresh counter 106 is provided inside the memory control circuit 100, there is no need to input a refresh address from the refresh control circuit 6, and the refresh request signal REQ 2 and the refresh enable signal AC K 0 Only need to be connected.
  • the present invention can be realized and the number of terminals can be reduced, which can contribute to cost reduction.
  • FIG. 20 shows an embodiment in which the CPU 4, the MPEG decoder (MPEG DEC) 5001, the video interface circuit (VIF) 600, and the RFC become masters and access the memory block MEM.
  • the MEM is shared by the CPU, the MPEGDEC and the VIF.
  • the access of the CPU opens the page even after the access is completed, and the access of the MPEG decoder, the video interface, and the refresh control circuit 6 ends at the end of the access. Let's consider switching control so that is closed.
  • the MPEG decoder decompresses the compressed data stored in a CD-ROM or the like and temporarily stores it in the MEM. Video to view The data in the MEM is read from the interface. At this time, the data transfer rate required for the MEM in order for the MPEG decoder to expand the data is about 160 MByte / sec.
  • one frame is composed of 720 x 480 pixels for NTS C. Since one pixel is composed, the luminance signal Y is 8 bits and the color difference signal Cr is If Cb is 8 bits each, the total number of bits in one frame is about 4 Mbit. Assuming that 60 frames are read out per second, a display requires a data transfer rate of about 30 MB yte / sec. Therefore, a transfer rate of 190 MB yte / sec is required.
  • the MPEG decoder 501 and the display interface circuit 600 communicate with the memory block (MEM) 50 through the access arbitration circuit 201 and the memory control circuit 101 to form a 512-bit memory block. Connected by data bus.
  • the access to the memory block 351 at which the data transfer rate of the MPEG decoder 501 becomes the lowest is access to a different page and is performed only once.
  • 7 latencies, ie, 70 ns power, power, and data transfer rate are (5 1 2,8) Byte X (1 X 100 00) to output 512 bits of data.
  • MH z 9 1 1 MB yt eZ sec.
  • the access from the MPEG decoder, the display interface circuit 701, and the refresh control circuit 600 according to the present invention can be achieved by closing the page at the end of these accesses.
  • the access from the CPU after this access is as follows. Even if it occurs in the memory bank accessed by either the MPEG decoder or the video interface before, the latency of DRAM does not increase and the speed can be increased.
  • FIG. 21 shows an embodiment in which the CPU 4, the graphics processing circuit (GC) 502, and the display interface circuit (VIF) 702 access the DRAM by the master and the refresh control circuit (RFC) 602. is there.
  • the memory block (MEM) 352 is shared by the GC, VIF, and CPU.
  • CPU access is controlled by opening a page even after the access is terminated, and by GC, VIF, and RFC access, switching control to close the page at the end of the access. Do.
  • the data transfer speed required for graphics processing by the graphics processing circuit 502 and the data transfer speed required by the display interface circuit 702 for display are obtained as follows.
  • the number of bits per pixel is 24 bits for R, G, and B representing color, 16 bits for Z value for depth, and 8 bits for ⁇ value for transparency, for a total of 48 bits.
  • the transfer rate required for drawing is about 884 MB yte / sec
  • the transfer rate required for display is about 11 OMB yte / sec. Requires a total transfer rate of 1 GB yte / sec.
  • the transfer rate of 3.6 GB yte / sec is + min. Even if the remaining transfer rate is used for the CPU, there is no problem in the operation of the graphics processing circuit. Therefore, also in the third embodiment, the operation of the DRAM can be sped up by the present invention.
  • the DRAM used in the above-described embodiment shows an example in which a plurality of memory ports are integrated on one chip, but this is not a limitation.
  • the present invention can be realized by treating the DRAM of each chip as a memory map.
  • control mode can be switched to control the DRAM corresponding to the plurality of masters.
  • DRAM can be operated at high speed.
  • the present invention can be applied to an information processing device, particularly a computer device represented by a personal computer device.
  • This information processing device may be versatile or may be incorporated as a part of the control device.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

Cette invention concerne un circuit intégré à semi-conducteurs qui permet de réduire la durée d'accès totale, lors de la commande d'accès (lecture/écriture) à partir d'une pluralité de sources de demande d'accès (sources-maîtres), à une mémoire comportant une pluralité de blocs de mémoire. En exploitant les propriétés des sources-maîtres, on utilise pour chaque source principale un circuit de commande de mémoire permettant de modifier le contenu de la commande d'accès. Plus précisément, lorsqu'une première source-maître ayant comme caractéristique d'accéder itérativement à la même page (canal mot) dans le même bloc de mémoire fait une demande d'accès, ce circuit de commande de mémoire met fin à l'accès, avec la page ouverte (bloc actif). A l'inverse, lorsqu'une seconde source-maître dont la probabilité d'accéder de façon répétée à la même page est faible fait une demande d'accès, le circuit ferme la page ouverte et met fin à l'accès. Cette commande d'accès convient tout particulièrement pour placer rapidement un canal mot DRAM en état de sélection ou de non sélection.
PCT/JP2000/000648 2000-02-07 2000-02-07 Dispositif de traitement de l'information et circuit integre a semi-conducteurs WO2001059573A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2001558836A JP4549001B2 (ja) 2000-02-07 2000-02-07 情報処理装置及び半導体集積回路
PCT/JP2000/000648 WO2001059573A1 (fr) 2000-02-07 2000-02-07 Dispositif de traitement de l'information et circuit integre a semi-conducteurs
AU2000223268A AU2000223268A1 (en) 2000-02-07 2000-02-07 Information processor and semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2000/000648 WO2001059573A1 (fr) 2000-02-07 2000-02-07 Dispositif de traitement de l'information et circuit integre a semi-conducteurs

Publications (1)

Publication Number Publication Date
WO2001059573A1 true WO2001059573A1 (fr) 2001-08-16

Family

ID=11735662

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2000/000648 WO2001059573A1 (fr) 2000-02-07 2000-02-07 Dispositif de traitement de l'information et circuit integre a semi-conducteurs

Country Status (3)

Country Link
JP (1) JP4549001B2 (fr)
AU (1) AU2000223268A1 (fr)
WO (1) WO2001059573A1 (fr)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01163849A (ja) * 1987-12-21 1989-06-28 Hitachi Micro Comput Eng Ltd 半導体集積回路
US5301278A (en) * 1988-04-29 1994-04-05 International Business Machines Corporation Flexible dynamic memory controller
JPH0784866A (ja) * 1993-06-30 1995-03-31 Toshiba Corp メモリ制御回路
JPH07129500A (ja) * 1993-11-08 1995-05-19 Canon Inc バススイッチ回路
US5634112A (en) * 1994-10-14 1997-05-27 Compaq Computer Corporation Memory controller having precharge prediction based on processor and PCI bus cycles
JPH1097788A (ja) * 1996-09-20 1998-04-14 Hitachi Ltd 情報処理装置
US5774409A (en) * 1996-04-22 1998-06-30 Mitsubishi Denki Kabushiki Kaisha Multi-bank dRAM suitable for integration with processor on common semiconductor chip
JPH1153252A (ja) * 1997-07-30 1999-02-26 Nec Niigata Ltd メモリ制御回路

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0212541A (ja) * 1988-04-29 1990-01-17 Internatl Business Mach Corp <Ibm> コンピユーテイング・システム及びその動作方法
JPH11345165A (ja) * 1997-12-05 1999-12-14 Texas Instr Inc <Ti> アクセス待ち時間を減少するため優先度とバースト制御を使用するトラフィック・コントローラ

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01163849A (ja) * 1987-12-21 1989-06-28 Hitachi Micro Comput Eng Ltd 半導体集積回路
US5301278A (en) * 1988-04-29 1994-04-05 International Business Machines Corporation Flexible dynamic memory controller
JPH0784866A (ja) * 1993-06-30 1995-03-31 Toshiba Corp メモリ制御回路
JPH07129500A (ja) * 1993-11-08 1995-05-19 Canon Inc バススイッチ回路
US5634112A (en) * 1994-10-14 1997-05-27 Compaq Computer Corporation Memory controller having precharge prediction based on processor and PCI bus cycles
US5774409A (en) * 1996-04-22 1998-06-30 Mitsubishi Denki Kabushiki Kaisha Multi-bank dRAM suitable for integration with processor on common semiconductor chip
JPH1097788A (ja) * 1996-09-20 1998-04-14 Hitachi Ltd 情報処理装置
JPH1153252A (ja) * 1997-07-30 1999-02-26 Nec Niigata Ltd メモリ制御回路

Also Published As

Publication number Publication date
JP4549001B2 (ja) 2010-09-22
AU2000223268A1 (en) 2001-08-20

Similar Documents

Publication Publication Date Title
US6381190B1 (en) Semiconductor memory device in which use of cache can be selected
JP2000021160A (ja) 半導体集積回路及びデータ処理システム
JP2006190402A (ja) 半導体装置
JPH1031886A (ja) ランダムアクセスメモリ
US20120155200A1 (en) Memory device, memory system including the same, and control method thereof
CN101169772A (zh) 用于传送命令和地址信号的方法和设备
KR100890381B1 (ko) 반도체 메모리 소자
KR20220127601A (ko) 인터페이스를 이용하여 내부 프로세싱을 수행하는 메모리 시스템, 메모리 장치 및 메모리 장치의 동작 방법
US6091667A (en) Semiconductor memory device and a data reading method and a data writing method therefor
JP4229958B2 (ja) メモリ制御システムおよびメモリ制御回路
US6829195B2 (en) Semiconductor memory device and information processing system
EP1248267A2 (fr) Dispositif de mémoire à semiconducteurs et système de traitement de l&#39;information
KR20080114406A (ko) 컬럼 어드레스 제어 회로
JP2010092261A (ja) メモリモジュール、および、メモリ用補助モジュール
US7898880B2 (en) Dual port memory device, memory device and method of operating the dual port memory device
JPH08328949A (ja) 記憶装置
JP4549001B2 (ja) 情報処理装置及び半導体集積回路
JP5363060B2 (ja) メモリモジュール、および、メモリ用補助モジュール
JPH08138377A (ja) 半導体記憶装置
JPH0863969A (ja) 半導体記憶装置
TW200423129A (en) Semiconductor memory device for enhancing refresh operation in high speed data access
JP2007095146A (ja) メモリ、メモリ・アクセス制御方法
US20230266893A1 (en) Memory system including memory device and memory controller, and operating method thereof
US20210208878A1 (en) Processing-in-memory(pim) device
KR100773065B1 (ko) 듀얼 포트 메모리 장치, 메모리 장치 및 듀얼 포트 메모리장치 동작 방법

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AL AU BA BB BG BR CA CN CU CZ EE GD GE HR HU ID IL IN IS JP KP KR LC LK LR LT LV MG MK MN MX NO NZ PL RO SG SI SK TR TT UA US UZ VN YU ZA

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase