WO2001054184A1 - Methode d'elimination de residus par gravure a l'oxyde reduite - Google Patents

Methode d'elimination de residus par gravure a l'oxyde reduite

Info

Publication number
WO2001054184A1
WO2001054184A1 PCT/US2001/001401 US0101401W WO0154184A1 WO 2001054184 A1 WO2001054184 A1 WO 2001054184A1 US 0101401 W US0101401 W US 0101401W WO 0154184 A1 WO0154184 A1 WO 0154184A1
Authority
WO
WIPO (PCT)
Prior art keywords
plasma ashing
ashing environment
environment
substantially remove
recited
Prior art date
Application number
PCT/US2001/001401
Other languages
English (en)
Other versions
WO2001054184A9 (fr
Inventor
Edward K. Yeh
Calvin Todd Gabriel
Tammy Zheng
Linda Leard
Original Assignee
Philips Semiconductors, Inc.
Koninklijke Philips Electronics N.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Semiconductors, Inc., Koninklijke Philips Electronics N.V. filed Critical Philips Semiconductors, Inc.
Priority to JP2001553576A priority Critical patent/JP2003520446A/ja
Priority to KR1020017011972A priority patent/KR20010112355A/ko
Priority to EP01906565A priority patent/EP1171908A1/fr
Publication of WO2001054184A1 publication Critical patent/WO2001054184A1/fr
Publication of WO2001054184A9 publication Critical patent/WO2001054184A9/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/42—Stripping or agents therefor
    • G03F7/427—Stripping or agents therefor using plasma means only

Definitions

  • the present disclosure relates to the field of semiconductor device fabrication. More specifically, the present disclosure relates to the removal or ashing of sidewall polymer material. In particular, a method for removing residues with reduced etching of oxide after gate etch using H 2 0 and CF 4 chemistries is disclosed.
  • Prior Art Figure 1A a side sectional view of a semiconductor substrate 100 having a gate oxide layer 102, a polysilicon layer 104, and a portion of photoresist 106 disposed thereover is shown.
  • portion of photoresist 106 defines the location at which a polysilicon gate will be formed.
  • polysilicon layer 104 is subjected to a plasma etch process. The plasma etch process removes polysilicon layer 104, except for the portion of polysilicon layer 104 which is covered, and, hence protected from the plasma etching proces s, by portion of photoresist 106.
  • Prior Art Figure IB is subjected to an aggressive chemical strip (e.g. a wet acid dip such as an HF acid dip) to remove residues 108.
  • a wet acid dip such as an HF acid dip
  • plasma-exposed gate oxide such as gate oxide layer 102, etches rapidly in HF acid. Specifically, plasma-exposed gate oxide can etch 20-40 Angstroms or more during even a brief dip in dilute HF acid.
  • Such a problem is further exacerbated by the fact that some present fabrication processes now form gate oxides with -thicknesses of 30 Angstroms or less.
  • the thickness of gate oxide.layer 102 is measured after residues 108 and portion of photoresist 106 have been removed.
  • Prior Art Figure 1C a side sectional view illustrates an example wherein, after an HF dip, gate oxide layer 102 has been deleteriously etched.
  • gate oxide layer 102 due to overetching of gate oxide layer 102, portions of semiconductor substrate 100 are no longer covered by gate oxide layer 102. Hence, regions of semiconductor substrate 100 are not adequately protected during subsequent process steps.
  • the present invention provides a method which effectively removes plasma etching-induced residues without deleteriously and substantially attacking gate oxide.
  • the present invention provides a novel and advantageous plasma ashing environment. Specifically, in this embodiment, the present invention introduces CF4 into the plasma ashing environment. Next, the present embodiment introduces H2O vapor into the plasma ashing environment. In this embodiment, the ratio by volume of the CF4 to the H2O is in the range of from 0.1:1 to 10:1. Next, the present embodiment uses the plasma ashing environment to substantially remove polysilicon etch-induced residues without requiring an aggressive chemical strip. In so doing, the etching of the gate oxide is significantly suppressed such that a sufficient amount of the gate oxide layer remains above the underlying semiconductor substrate.
  • the gate oxide layer is clean and enough gate oxide remains such that the thickness of the remaining gate oxide layer can be accurately and reliably measured and the silicon substrate is not exposed to environments that might attack or contaminate it.
  • the present invention provides a method for concurrently removing photoresist and residual polymers after a plasma etch of polysilicon.
  • the present invention provides a novel and advantageous plasma ashing environment. Specifically, in this embodiment, the present invention introduces CF4 into the plasma ashing environment. Next, the present embodiment introduces H2O vapor into the plasma ashing environment. In this embodiment, the ratio by volume of the CF4 to the H2O is in the range of from 0.1:1 to 10:1. Then, the present embodiment introduces O2 into the plasma ashing environment.
  • the present embodiment uses the plasma ashing environment to both substantially remove polysilicon etch-induced residues and to remove remaining portions of photoresist without requiring an aggressive chemical strip.
  • the etching of the gate oxide is significantly suppressed such that a sufficient amount of the gate oxide layer remains above the underlying semiconductor substrate.
  • the gate oxide layer is clean and enough gate oxide remains such that the thickness of the remaining gate oxide layer can be accurately and reliably measured and the silicon substrate is not exposed to environments that might attack or contaminate it. Furthermore, all remaining regions of photoresist have already been removed.
  • FIGURES 1A-1C are cross sectional views illustrating steps associated with prior art polysilicon gate formation and residue removal methods.
  • FIGURES 2A-2D are cross sectional views illustrating a residue removal process in accordance with one embodiment of the present claimed invention.
  • FIGURE 3 is a flow chart of steps performed in accordance with one embodiment of the present claimed invention.
  • FIGURE 4 is a flow chart of steps performed in accordance with one embodiment of the present claimed invention.
  • FIGURES 5A-5C are cross sectional views illustrating a residue removal process in accordance with another embodiment of the present claimed invention.
  • FIGURE 6 is a flow chart of steps performed in accordance with one embodiment of the present claimed invention.
  • FIGURE 7 is a flow chart of steps performed in accordance with one embodiment of the present claimed invention.
  • FIGURE 8 is a table of CF4/H2O and O2 plasma ashing recipes in accordance with one embodiment of the present claimed invention.
  • FIG. 2A a cross sectional view of a semiconductor substrate 200 haying a gate oxide layer 202, a polysilicon layer 204, and a portion of photoresist 206 disposed thereover is shown.
  • portion of photoresist 206 defines the location at which a polysilicon gate will be formed.
  • polysilicon layer 204 is subjected to a plasma etch process.
  • the plasma etch process removes polysilicon layer 204, except for that portion of polysilicon layer 204 which is covered, and, hence protected from the plasma etching process, by portion of photoresist 206.
  • residues e.g. residual polymer materials
  • residues typically shown as 208, are formed on portions of photoresist 206, the remaining regions of polysilicon layer 204, and the surface of gate oxide layer 202.
  • FIG. 2C a side sectional view illustrates an example of the present embodiment wherein residues 208 of Figure 2C have been removed without the removal of gate oxide layer 202. Additionally, unlike the prior art, the present embodiment removes residues 208 without the need for subjecting the gate oxide layer 202 to an aggressive chemical strip. The process used in the present embodiment to remove residues 208 will be described in detail below in conjunction with Figures 3 and 4.
  • FIG. 2D a side sectional view illustrates an example of the present embodiment after the removal of residues 208 of Figure 2C and after the removal of portion of photoresist 206 of Figure 2C.
  • only polysilicon gate region 204 and, gate oxide layer 202 remain disposed above semiconductor substrate 200.
  • gate oxide layer 202 is now clean and can be measured to verify that gate oxide layer 202 is of a requisite thickness.
  • a flow chart 300 of steps performed in accordance with one embodiment of the present invention is shown.
  • a plasma etch of a polysilicon layer is performed to define the location of the polysilicon gate.
  • this process results in the formation of residues on the portion of photoresist, the remaining regions of the polysilicon layer, and the surface of gate oxide layer all of which reside above the semiconductor substrate.
  • conventional processes employ an aggressive chemical strip in an attempt to remove these residues. This prior art aggressive chemical strip deleteriously attacks and significantly etches the gate oxide layer.
  • the present embodiment then subjects the semiconductor substrate and overlying features to a plasma ashing environment to remove the residues which resulted from the plasma etching of the polysilicon layer.
  • the present embodiment eliminates the need to subject the semiconductor substrate and overlying features (including the gate oxide layer) to a deleterious aggressive chemical strip.
  • the precise chemistry of the ashing environment used in the step 304 of the present embodiment to remove residues 208 will be described in detail below in conjunction with Figure 4.
  • the present invention proceeds to step 306.
  • the present embodiment removes remaining portions of photoresist (e.g. the photoresist residing above the polysilicon gate). This photoresist removal process insures that the gate oxide layer is now clean and easily measured.
  • the present embodiment enables an accurate and reliable measurement of the thickness of the gate oxide layer. That is, in the present embodiment, it is possible to measure the thickness of the gate oxide layer without obtaining substantially flawed measurements associated with measuring prior to strip (because residues may be falsely measured as oxide by the measurement tool) or the use of an aggressive chemical strip (which removes a significant amount of oxide).
  • a flow chart 400 of steps performed to generate the plasma ashing environment recited in step 304 of Figure 3 is shown.
  • the present embodiment After the performance of step 302 and in accordance with step 402 of Figure 4, the present embodiment generates a plasma ashing environment. More particularly, in one embodiment, the present invention introduces CF4 into a plasma ashing environment.
  • present embodiment introduces H2O vapor into the plasma ashing environment such that the ratio by volume of the CF4 to the H2O is in the range of from 0.1:1 to 10:1.
  • the present embodiment uses this plasma ashing environment to substantially remove polysilicon etch-induced residues without requiring an aggressive chemical strip. Hence, the present embodiment eliminates the need for the deleterious aggressive chemical strip of the prior art.
  • the aforementioned plasma ashing environment is created by introducing the CF4 at a flow rate of approximately 5-5000 standard cubic centimeters per minute (SCCM).
  • SCCM standard cubic centimeters per minute
  • the H2O is introduced into the plasma ashing environment at a flow rate of approximately 5-5000 standard cubic centimeters per minute (SCCM).
  • SCCM standard cubic centimeters per minute
  • the plasma ashing environment used to substantially remove polysilicon etch-induced residues without requiring the aggressive chemical strip is at a pressure in the range of 50 mTorr to 5 Torr; is at a power in the range of 50 Watts to 5000 Watts; is performed for a duration in the range of 3 seconds to 300 seconds; and is performed at a temperature in the range of 20 degrees Celsius to 350 degrees Celsius.
  • the presence of the CF4 is used to remove residues, while the presence of H2O is used to suppress etching of the gate oxide layer.
  • conventional prior art processes which expose the gate oxide layer to an aggressive chemical strip often show a loss of more than 40 Angstroms in the thickness of the oxide layer.
  • the present embodiment limits the loss of thickness in the gate oxide layer to less than 10 Angstroms.
  • step 404 Upon the completion of step 404, the present embodiment returns to step 306 of Figure 3.
  • FIG. 5A a cross sectional view of a semiconductor substrate 500 having a gate oxide layer 502, a polysilicon layer 504, and a portion of photoresist 506 disposed thereover is shown.
  • portion of photoresist 506 defines the location at which a polysilicon gate will be formed.
  • polysilicon layer 504 is subjected to a plasma etch process.
  • the plasma etch process removes polysilicon layer 504, except for that portion of polysilicon layer 504 which is covered, and, hence protected from the plasma etching process, by portion of photoresist 506.
  • residues e.g. residual polymer materials
  • 508 are formed on portion of photoresist 506, the remaining regions of polysilicon layer 504, and the surface of gate oxide layer 502.
  • FIG. 5C a side sectional view illustrates an example of the present embodiment wherein both residues 508 of Figure 5C and the remaining portions of photoresist 506 of Figure 5C have been removed. Additionally, unlike the prior art, the present embodiment removes residues 508 without subjecting gate oxide layer 502 to an aggressive chemical strip. The process used in the present embodiment to remove both residues 508 and photoresist 506 will be described in detail below in conjunction with Figures 6 and 7. Furthermore, gate oxide layer 502 is now clean and can be measured to verify that gate oxide layer 502 is of a requisite thickness.
  • a flow chart 600 of steps performed in accordance with one embodiment of the present invention is shown.
  • a plasma etch of a polysilicon layer is performed to define the location of the polysilicon gate.
  • this process results in the formation of residues on the photoresist, the remaining regions of the polysilicon layer, and the surface of gate oxide layer all of which reside above the semiconductor substrate.
  • conventional processes employ an aggressive chemical strip in an attempt to remove these residues. This prior art aggressive chemical strip deleteriously attacks and significantly etches the gate oxide layer.
  • the present embodiment then subjects the semiconductor substrate and overlying features to a plasma ashing environment to remove both the residues which resulted from the plasma etching of the polysilicon layer and the remaining portions of photoresist.
  • the present embodiment eliminates the need to subject the semiconductor substrate and overlying features (including the gate oxide layer) to a deleterious aggressive chemical strip.
  • the precise chemistry of the ashing environment used in the step 604 of the present embodiment to remove residues 508 will be described in detail below in conjunction with Figure 7. This residue and photoresist removal process ensures that the gate oxide layer is now clean and easily measured.
  • the present disclosure proceeds to step 606.
  • step 606 after the performance of steps 602 and 604, the present embodiment enables an accurate and reliable measurement of the thickness of the gate oxide layer.
  • a flow chart 700 of steps performed to generate the plasma ashing environment recited in step 604 of Figure 6 is shown.
  • the present embodiment After the performance of step 602 and in accordance with step 702 of Figure 7, the present embodiment generates a plasma ashing environment. More particularly, in one embodiment, the present disclosure introduces CF 4 into a plasma ashing environment. At step 704, present embodiment, introduces H2O vapor i ⁇ £o the plasma ashing environment such that the ratio by volume of the CF4 to the H2O is in the range of from 0.1:1 to 10:1.
  • present embodiment introduces O2 vapor into the plasma ashing environment.
  • the present embodiment uses this plasma ashing environment to substantially remove both polysilicon etch-induced residues and photoresist without requiring an aggressive chemical strip. Hence, the present embodiment eliminates the need for the deleterious aggressive chemical strip of the prior art.
  • the aforementioned plasma ashing environment is created by introducing the CF4 at a flow rate of approximately 5-5000 standard cubic centimeters per minute (SCCM).
  • SCCM standard cubic centimeters per minute
  • the H2O is introduced into the plasma ashing environment at a flow rate of approximately 5-5000 standard cubic centimeters per minute (SCCM).
  • SCCM standard cubic centimeters per minute
  • the O2 is introduced into the plasma ashing environment at a flow rate of . approximately 10-10,000 standard cubic centimeters per minute (SCCM).
  • the plasma ashing environment used to substantially remove both polysilicon etch-induced residues and remaining portions of photoresist without requiring the aggressive chemical strip is at a pressure in the range of 5 mTorr to 5 Torr; is at a power in the range of 50 Watts to 5000 Watts; is performed for a duration in the range of 3 seconds to 300 seconds; and is performed at a temperature in the range of 20 degrees Celsius to 350 degrees Celsius.
  • the present invention is well suited to varying the parameters, conditions, and components of the plasma ashing environment.
  • the presence of the CF4 is used to remove residues, while the presence of H2O is used to suppress etching of the gate oxide layer, and the presence of 02 is used to remove remaining portions of photoresist material.
  • conventional prior art processes which expose the gate oxide layer to an aggressive chemical strip often show a loss of more than 40 Angstroms in the thickness of the oxide layer.
  • the present embodiment however, limits the loss of thickness in the gate oxide layer to less than 10 Angstroms.
  • step 706 Upon the completion of step 706, the present embodiment returns to step 606 of Figure 6.
  • a table 800 reciting CF4 H2O and O2 plasma ashing recipes in accordance with one embodiment of the present claimed invention. Although such parameters are recited in table 800, the present invention is well suited to varying the parameters, conditions, and components of the plasma ashing environment.
  • the present invention provides a method which effectively removes plasma etching-induced residues without deleteriously and substantially attacking gate oxide.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Plasma & Fusion (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

L'invention concerne un procédé d'élimination de résidus induits par gravure au plasma. Dans un mode de réalisation, après utilisation d'une partie de matière photorésistante pour former une grille en polysilicium, ledit procédé de cette invention produit un nouvel environnement d'incinération au plasma avantageux. Notamment, dans ce mode de réalisation, ledit procédé introduit du CF4 dans cet environnement, puis de la vapeur d'H20. Dans ce mode de réalisation, le taux par volume de CF4 par rapport à H20 se situe entre 0,1:1 et 10:1. Dans ce mode de réalisation, le procédé a recours à l'environnement d'incinération au plasma pour éliminer les résidus induits par gravure au polysilicium sans dépouillage chimique agressif. Ainsi, la gravure de l'oxyde de grille est considérablement supprimée, de telle manière qu'une quantité suffisante de la couche d'oxyde de grille reste au-dessus du substrat semi-conducteur sous-jacent. Par ailleurs, après élimination desdits résidus, la couche d'oxyde de grille est propre et il reste suffisamment d'oxyde de grille pour que l'épaisseur de la couche d'oxyde de grille restante puisse être mesurée de manière précise et fiable.
PCT/US2001/001401 2000-01-19 2001-01-17 Methode d'elimination de residus par gravure a l'oxyde reduite WO2001054184A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2001553576A JP2003520446A (ja) 2000-01-19 2001-01-17 酸化物がエッチングされないようにした残渣除去方法
KR1020017011972A KR20010112355A (ko) 2000-01-19 2001-01-17 산화물의 에칭이 감소된 잔사의 제거 방법
EP01906565A EP1171908A1 (fr) 2000-01-19 2001-01-17 Methode d'elimination de residus par gravure a l'oxyde reduite

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US48775700A 2000-01-19 2000-01-19
US09/487,757 2000-01-19

Publications (2)

Publication Number Publication Date
WO2001054184A1 true WO2001054184A1 (fr) 2001-07-26
WO2001054184A9 WO2001054184A9 (fr) 2002-10-10

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PCT/US2001/001401 WO2001054184A1 (fr) 2000-01-19 2001-01-17 Methode d'elimination de residus par gravure a l'oxyde reduite

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EP (1) EP1171908A1 (fr)
JP (1) JP2003520446A (fr)
KR (1) KR20010112355A (fr)
CN (1) CN1358328A (fr)
WO (1) WO2001054184A1 (fr)

Cited By (1)

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Publication number Priority date Publication date Assignee Title
EP1469510A2 (fr) * 2003-04-17 2004-10-20 Applied Materials, Inc. Méthode de fabrication d'une structure de grille d'un transistor à effet de champ

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KR100981673B1 (ko) * 2003-02-03 2010-09-13 매그나칩 반도체 유한회사 반도체 소자의 게이트 형성 방법
US7094613B2 (en) * 2003-10-21 2006-08-22 Applied Materials, Inc. Method for controlling accuracy and repeatability of an etch process
CN100342497C (zh) * 2004-05-21 2007-10-10 中国科学院微电子研究所 一种纳米线宽多晶硅栅刻蚀掩膜图形的形成方法
CN100372070C (zh) * 2004-12-10 2008-02-27 上海宏力半导体制造有限公司 可控制栅极结构长度的刻蚀工艺
US7667820B2 (en) * 2006-01-17 2010-02-23 Asml Netherlands B.V. Method for chemical reduction of an oxidized contamination material, or reducing oxidation of a contamination material and a conditioning system for doing the same
EP3646116B1 (fr) * 2017-06-29 2023-12-13 ASML Netherlands B.V. Système, appareil lithographique et procédé de réduction d'oxydation ou d'élimination d'oxyde sur un support de substrat
CN108010839B (zh) * 2017-12-06 2021-08-06 信利（惠州）智能显示有限公司 薄膜晶体管与薄膜晶体管的制作方法及膜层刻蚀工艺
CN113725221B (zh) * 2021-08-30 2024-04-26 上海华虹宏力半导体制造有限公司 闪存器件的制造方法

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US5382316A (en) * 1993-10-29 1995-01-17 Applied Materials, Inc. Process for simultaneous removal of photoresist and polysilicon/polycide etch residues from an integrated circuit structure
US5814155A (en) * 1996-06-26 1998-09-29 Vlsi Technology, Inc. Plasma ashing enhancement
US5925577A (en) * 1997-02-19 1999-07-20 Vlsi Technology, Inc. Method for forming via contact hole in a semiconductor device
JP2000012514A (ja) * 1998-06-19 2000-01-14 Hitachi Ltd 後処理方法

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US5382316A (en) * 1993-10-29 1995-01-17 Applied Materials, Inc. Process for simultaneous removal of photoresist and polysilicon/polycide etch residues from an integrated circuit structure
US5814155A (en) * 1996-06-26 1998-09-29 Vlsi Technology, Inc. Plasma ashing enhancement
US5925577A (en) * 1997-02-19 1999-07-20 Vlsi Technology, Inc. Method for forming via contact hole in a semiconductor device
JP2000012514A (ja) * 1998-06-19 2000-01-14 Hitachi Ltd 後処理方法

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1469510A2 (fr) * 2003-04-17 2004-10-20 Applied Materials, Inc. Méthode de fabrication d'une structure de grille d'un transistor à effet de champ
EP1469510A3 (fr) * 2003-04-17 2005-04-13 Applied Materials, Inc. Méthode de fabrication d'une structure de grille d'un transistor à effet de champ

Also Published As

Publication number Publication date
CN1358328A (zh) 2002-07-10
EP1171908A1 (fr) 2002-01-16
KR20010112355A (ko) 2001-12-20
JP2003520446A (ja) 2003-07-02
WO2001054184A9 (fr) 2002-10-10

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