Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
  • G06F12/02—Addressing or allocation; Relocation
  • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
  • G06F12/12—Replacement control
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
  • G06F12/02—Addressing or allocation; Relocation
  • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
  • G06F12/12—Replacement control
  • G06F12/121—Replacement control using replacement algorithms
  • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
  • G06F12/02—Addressing or allocation; Relocation
  • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
  • G06F12/10—Address translation
  • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]

Definitions

• the invention relates to cache replacement schemes. More specifically, the invention relates to combined round robin cache replacement and cache line locking schemes.
• LRU least recently used
• CAM content addressable memory
• caches without separate decoders, high set-associativity is achieved, and identifying where to write fill data becomes increasingly problematic.
• One possible solution that has been employed is a round robin replacement scheme in which a circular shift register loops through identifying the line to be loaded. This has the effect of throwing away the oldest information in the cache, but the replacement is completely independent of the frequency of use. Thus, it can result in a greater amount of cache thrashing.
• a first plurality of latches are daisy chained together, forming a register, with each latch associated with a particular cache line.
• a second plurality of latches are daisy chained together with each latch associated with a cache line.
• the first register defines a fill order of cache lines and the second register defines a lock order for the cache lines.
• Figure 1 is a block diagram of one embodiment of the invention.
• Figure 2 is a block diagram of the round robin lock logic in one embodiment of the invention.
• Figure 3 shows an exemplary series of loads during an eight cycle period.
• Figure 4 is a timing diagram for a subset of signals in one embodiment of the invention.
• FIG. 1 is a block diagram of one embodiment of the invention.
• a content addressable memory array (CAM) 102 is used to address into a random access memory unit (RAM) 104.
• RAM random access memory
• the combination of CAM 102 and RAM 104 may typically be, for example, a cache and more particularly in one embodiment, a level zero cache, or possibly in an alternate embodiment, a translation lookaside buffer (TLB).
• TLB translation lookaside buffer
• the CAM 102 contains the addresses corresponding to the corresponding entry, which is a line of code or data in the former case, and a page table entry in the latter.
• the data contained within the CAM entry is referred to as the "tag" entry in either case.
• a control logic unit, such as round robin and lock logic 100 is coupled to the CAM 102.
• the control logic unit controls the replacement scheme employed by the CAM addressed cache when data is to be written into the CAM 102 and RAM 104, e.g., which line is to be replaced on a cache fill operation.
• Both circuits, the CAM 102 and the RAM 104 may be written through means well known to those skilled in the art.
• the CAM 102 is accessed to determine the matching entry (if there is one) via the content- addressable nature of the CAM 102. If a match is found, data is read from RAM 104 as output through sense amp 106, which is coupled thereto, or a write operation to the RAM 104 may be performed through the same circuitry as used to write data into the RAM 104 during the aforementioned fill operation.
• this form of cache circuit architecture has more favorable low-power characteristics as compared to more typical architectures utilizing RAM cells to store the tag data.
• Round robin and lock logic 100 in addition to receiving load requests, receives a number of control signals, including a lock clock, a lock select, a lock clear, and a round robin clear.
• the lock clock when asserted indicates that the load request is a lock.
• the load is a fill.
• lock is a load into a line that is to be locked, so as not to be overwritten by subsequent loads.
• a fill is a load that may be freely overwritten as part of the usual cache replacement scheme.
• Lock clear clears the lock register (discussed further below) to permit the subsequent overwriting of the previous loaded locks.
• Round robin clear resets the round robin register (also discussed further below) to a predetermined value.
• the lock select signal used as the mode select for a set of multiplexers that choose between signals from the round robin registers and the lock registers for word line enablement.
• FIG. 2 is a block diagram of the round robin lock logic in one embodiment of the invention.
• the plurality of round robin latches 212, 214, 216, 210 are each associated with one line of a cache. In the shown embodiment, it is presumed that there are 32 lines in the array. However, more or fewer lines (and therefore, latches) are within the scope and contemplation of the invention. Accordingly, 32 round robin latches are provided, comprising the round robin register 200.
• a second plurality of latches, 230, 232, 234 comprising the lock register 202, also have one latch associated with each of a plurality of cache lines.
• lock latches which permit the locking of up to 31 of the 32 cache lines. By preventing one or more lines from being locked, the system avoids a deadlock condition in which new data needs to be loaded in the cache, but all lines are locked, preventing such a load.
• the lock latches are daisy chained together as are the round robin latches . In this manner, the lock register forces an ordered series of locks from top to bottom in the array responsive to the lock clock.
• the round robin register 200 cause circular fills beginning with a bottom line in the array followed by the highest unlocked line in the array and proceeding downward to the bottom and then circularly.
• Combinational logic 204 ensures that fills do not overwrite locked lines.
• registers 200 and 204 are pulsed latches, and in an alternate embodiment, they are master slave flip-flops.
• the pulsed latches are more area efficient, but tend to be more susceptible to such issues as insufficient hold times over process skews.
• the lock registers include the start latch 230 which corresponds to word line 31 of the array in operation has its input coupled to a positive power supply. Thus, when the lock clock is asserted, a high value appears at the output of register 230, and therefore, correspondingly on the input of register 232 which is daisy chained as shown.
• One issue that arises in an embodiment in using pulsed latches rather than master-slave flipflops is that sufficient delay must be built into the circuit to avoid both latches 230 and 232 (or more in the chain) from being set when lock clock is asserted.
• lock clock is a short pulse timed to be sufficiently long to allow one latch in the lock register to receive its input value, but sufficiently short to avoid the latch connected to output of the intended target latch from receiving the same data.
• a high value will appear at the output of register 232, as well as 230.
• the high value cycles down through the lock register 202 until it reaches lock latch 234 after 31 assertions of the lock clock.
• all 31 latches in the lock register 202 will have logical one's stored therein.
• Round robin register 200 latches are coupled such that after assertion of the round robin reset signal, all latches except latch 210 are cleared.
• Latch 210 is the round robin start bit and is set responsive to a round robin clear signal. This signal is also asserted on a full-chip reset to initialize the cache: When latch 210 is set, that necessitates that fills will begin at word line zero. In addition to startup, the round robin reset signal is asserted responsive to a lock occurring. This ensures that a lock bit cannot be set coincident with the round robin bit which would constitute a logically illegal condition, i.e., that a locked line was selected to be the next target for a line fill. This scheme of setting the bottom, unlockable location for replacement when a lock operation is performed requires a minimum of logic. The implications of this scheme on the cache efficiency is addressed subsequently.
• the next fill line is identified to be the highest line that is not locked.
• the output of latch 230 will be a zero, which will be inverted by inverter 310 causing AND gate 312 to output a "1,” which causes AND gate 314 to also output a "1" to OR gate 316 which will then drive register 212 to output a high value, thereby selecting word line 31.
• Multiplexers 208 employ the lock select signal to determine whether the round robin register or the lock register selects the word lines.
• the word line (WL) select is chosen to be taken from the output of gate 312, via the multiplexors 208 and 209.
• the WL to be asserted, indicating the line to be filled on a lock is based on the coincidence of the previous lock latch being set to logical one and the present one being a logical zero.
• the lock clock is asserted after each lock operation WL assertion.
• the multiplexor 208 asserts the WL by passing the logical one contained in the corresponding round robin latch to the WL SELECT node via multiplexor 209.
• Multiplexor 209 selects between the output of multiplexor 208 and a CAM match signal which permits the CAM to assert the WL select during cache read and write operations that utilize the CAM for addressing.
• a decoder output may provide the second input to multiplexor 209.
• start register 210 is the only register of the round robin registers with high fanout.
• "high" fanout is deemed to be more than three inputs to be driven by the output of the device experiencing the fanout.
• Buffer 206 is used to buffer up the signal to accommodate the fanout as register 210 must drive an input signal for each of the other round robin registers.
• the other round robin registers drive inputs only to their nearest neighbors. Consequently, they can be kept very small. This is desirable since there are two latches (in the pulsed-latch embodiment) per line in the cache, a number typically 32 in TLB's, but numbering into the thousands in the case of caches.
• Figure 3 shows an exemplary series of loads during an eight cycle period.
• fill one is loaded into word line zero, and the fill pointer advances to point to word line 31.
• fill two is loaded into word line 31, and the fill pointer is advanced to point to word line 30.
• fill three is loaded into word line 30.
• lock one is loaded into the lock starting line (word line 31), kicking out fill two and the fill pointer is reset to point to word line zero.
• lock two is loaded into the next lock line (word line 30), kicking out fill three and again, the fill pointer is reset to point to word line zero.
• FIG 4 shows a timing diagram of a subset of signals of one embodiment of the invention.
• the pulse clock signal 410 is used in the pulse latch embodiment described above.
• the pulse should be short enough that it will have gone back low before the signal from an adjacent latch can propagate to it neighbor.
• the output of round robin latch (212 of Figure 2) is shown as signal 412. This output goes high responsive to the pulse clock 410.
• the pulse clock 410 must be low before the output of OR gate (336 of Figure 1) represented by signal 414 is asserted high based on the application of signal 412 to the OR gate.
• CAMs each with an associated round robin and lock logic unit, are used to form a larger cache having a plurality of banks.
• Each bank implements the round robin and lock scheme within the bank and independent of all other banks.

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• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Memory System Of A Hierarchy Structure (AREA)
• Bus Control (AREA)
• Materials For Photolithography (AREA)
• Pharmaceuticals Containing Other Organic And Inorganic Compounds (AREA)
• Accessory Devices And Overall Control Thereof (AREA)

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• 1999
  • 1999-12-30 US US09/476,444 patent/US6516384B1/en not_active Expired - Lifetime
• 2000
  • 2000-11-27 CN CNB008180415A patent/CN1308841C/zh not_active Expired - Lifetime
  • 2000-11-27 JP JP2001550561A patent/JP2004538536A/ja active Pending
  • 2000-11-27 GB GB0215661A patent/GB2374178B/en not_active Expired - Lifetime
  • 2000-11-27 KR KR10-2002-7008325A patent/KR100476446B1/ko not_active Expired - Lifetime
  • 2000-11-27 CN CN200710084018.4A patent/CN101008924B/zh not_active Expired - Lifetime
  • 2000-11-27 WO PCT/US2000/042305 patent/WO2001050269A2/en not_active Ceased
  • 2000-11-27 AU AU37936/01A patent/AU3793601A/en not_active Abandoned
• 2001
  • 2001-01-09 TW TW089128436A patent/TW518464B/zh not_active IP Right Cessation

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