TW518464B - A method and apparatus to perform a round robin and locking cache replacement scheme - Google Patents

A method and apparatus to perform a round robin and locking cache replacement scheme Download PDF

Info

Publication number
TW518464B
TW518464B TW089128436A TW89128436A TW518464B TW 518464 B TW518464 B TW 518464B TW 089128436 A TW089128436 A TW 089128436A TW 89128436 A TW89128436 A TW 89128436A TW 518464 B TW518464 B TW 518464B
Authority
TW
Taiwan
Prior art keywords
line
lock
patent application
cache
latches
Prior art date
Application number
TW089128436A
Other languages
English (en)
Chinese (zh)
Inventor
Lawrence T Clark
Matthew M Clark
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of TW518464B publication Critical patent/TW518464B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Accessory Devices And Overall Control Thereof (AREA)
  • Materials For Photolithography (AREA)
  • Pharmaceuticals Containing Other Organic And Inorganic Compounds (AREA)
  • Bus Control (AREA)
TW089128436A 1999-12-30 2001-01-09 A method and apparatus to perform a round robin and locking cache replacement scheme TW518464B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/476,444 US6516384B1 (en) 1999-12-30 1999-12-30 Method and apparatus to perform a round robin and locking cache replacement scheme

Publications (1)

Publication Number Publication Date
TW518464B true TW518464B (en) 2003-01-21

Family

ID=23891874

Family Applications (1)

Application Number Title Priority Date Filing Date
TW089128436A TW518464B (en) 1999-12-30 2001-01-09 A method and apparatus to perform a round robin and locking cache replacement scheme

Country Status (8)

Country Link
US (1) US6516384B1 (enExample)
JP (1) JP2004538536A (enExample)
KR (1) KR100476446B1 (enExample)
CN (2) CN1308841C (enExample)
AU (1) AU3793601A (enExample)
GB (1) GB2374178B (enExample)
TW (1) TW518464B (enExample)
WO (1) WO2001050269A2 (enExample)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6694408B1 (en) * 2000-05-01 2004-02-17 Javier Villagomez Scalable replacement method and system in a cache memory
US6772199B1 (en) * 2000-09-14 2004-08-03 International Business Machines Corporation Method and system for enhanced cache efficiency utilizing selective replacement exemption
US6889349B2 (en) * 2001-08-22 2005-05-03 Hewlett-Packard Development Company, L.P. Digital event sampling circuit and method
WO2005050455A1 (ja) * 2003-11-18 2005-06-02 Matsushita Electric Industrial Co., Ltd. キャッシュメモリ及びその制御方法
US7650466B2 (en) 2005-09-21 2010-01-19 Qualcomm Incorporated Method and apparatus for managing cache partitioning using a dynamic boundary
US7523260B2 (en) 2005-12-22 2009-04-21 International Business Machines Corporation Propagating data using mirrored lock caches
JP4712863B2 (ja) * 2006-02-28 2011-06-29 富士通株式会社 アドレス排他制御システムおよびアドレス排他制御方法
US8694737B2 (en) 2010-06-09 2014-04-08 Micron Technology, Inc. Persistent memory for processor main memory
US9448938B2 (en) 2010-06-09 2016-09-20 Micron Technology, Inc. Cache coherence protocol for persistent memories
US8613074B2 (en) 2010-09-30 2013-12-17 Micron Technology, Inc. Security protection for memory content of processor main memory
EP2466451A1 (en) * 2010-12-14 2012-06-20 STMicroelectronics Srl Method for controlling operation of a memory, corresponding system, and computer program product
TWI489344B (zh) * 2013-02-25 2015-06-21 Pixart Imaging Inc 觸控方法以及觸控裝置
CN105515565B (zh) * 2015-12-14 2018-07-13 天津光电通信技术有限公司 一种硬件逻辑资源复用模块及复用实现的方法
US9933947B1 (en) * 2015-12-30 2018-04-03 EMC IP Holding Company LLC Maintaining write consistency on distributed multiple page writes
FR3086409A1 (fr) * 2018-09-26 2020-03-27 Stmicroelectronics (Grenoble 2) Sas Procede de gestion de la fourniture d'informations, en particulier des instructions, a un microprocesseur et systeme correspondant
CN110727463B (zh) * 2019-09-12 2021-08-10 无锡江南计算技术研究所 一种基于动态信用的零级指令循环缓冲预取方法及装置
US11030104B1 (en) * 2020-01-21 2021-06-08 International Business Machines Corporation Picket fence staging in a multi-tier cache

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4783735A (en) * 1985-12-19 1988-11-08 Honeywell Bull Inc. Least recently used replacement level generating apparatus
US5029072A (en) 1985-12-23 1991-07-02 Motorola, Inc. Lock warning mechanism for a cache
IL96808A (en) * 1990-04-18 1996-03-31 Rambus Inc Introductory / Origin Circuit Agreed Using High-Performance Brokerage
US5353425A (en) * 1992-04-29 1994-10-04 Sun Microsystems, Inc. Methods and apparatus for implementing a pseudo-LRU cache memory replacement scheme with a locking feature
US5408629A (en) * 1992-08-13 1995-04-18 Unisys Corporation Apparatus and method for controlling exclusive access to portions of addressable memory in a multiprocessor system
GB2284911A (en) 1993-12-16 1995-06-21 Plessey Semiconductors Ltd Flexible lock-down cache.
US5761712A (en) * 1995-06-07 1998-06-02 Advanced Micro Devices Data memory unit and method for storing data into a lockable cache in one clock cycle by previewing the tag array
US5928352A (en) 1996-09-16 1999-07-27 Intel Corporation Method and apparatus for implementing a fully-associative translation look-aside buffer having a variable numbers of bits representing a virtual address entry
US5787431A (en) * 1996-12-16 1998-07-28 Borland International, Inc. Database development system with methods for java-string reference lookups of column names
US5913224A (en) * 1997-02-26 1999-06-15 Advanced Micro Devices, Inc. Programmable cache including a non-lockable data way and a lockable data way configured to lock real-time data
US5937429A (en) * 1997-04-21 1999-08-10 International Business Machines Corporation Cache memory having a selectable cache-line replacement scheme using cache-line registers in a ring configuration with a token indicator
US6044478A (en) * 1997-05-30 2000-03-28 National Semiconductor Corporation Cache with finely granular locked-down regions
US6098152A (en) * 1997-10-17 2000-08-01 International Business Machines Corporation Method and apparatus for miss sequence cache block replacement utilizing a most recently used state
JPH11184695A (ja) * 1997-12-19 1999-07-09 Nec Corp キャッシュメモリ及びキャッシュメモリへのアクセス方法
US6151655A (en) * 1998-04-30 2000-11-21 International Business Machines Corporation Computer system deadlock request resolution using timed pulses
US6073182A (en) * 1998-04-30 2000-06-06 International Business Machines Corporation Method of resolving deadlocks between competing requests in a multiprocessor using global hang pulse logic
US6240489B1 (en) * 1999-02-24 2001-05-29 International Business Machines Corporation Method for implementing a pseudo least recent used (LRU) mechanism in a four-way cache memory within a data processing system

Also Published As

Publication number Publication date
AU3793601A (en) 2001-07-16
GB2374178A (en) 2002-10-09
WO2001050269A3 (en) 2001-12-13
JP2004538536A (ja) 2004-12-24
CN101008924B (zh) 2015-05-13
GB0215661D0 (en) 2002-08-14
KR100476446B1 (ko) 2005-03-16
KR20020097145A (ko) 2002-12-31
CN101008924A (zh) 2007-08-01
WO2001050269A2 (en) 2001-07-12
US6516384B1 (en) 2003-02-04
GB2374178B (en) 2004-08-25
CN1415093A (zh) 2003-04-30
CN1308841C (zh) 2007-04-04

Similar Documents

Publication Publication Date Title
TW518464B (en) A method and apparatus to perform a round robin and locking cache replacement scheme
US7296143B2 (en) Method and system for loading processor boot code from serial flash memory
US9971647B2 (en) Apparatus and method for programming ECC-enabled NAND flash memory
US7372735B2 (en) Non-volatile semiconductor memory device
CN101495968B (zh) 用于软件事务存储器系统的硬件加速
US8171281B2 (en) Microprocessor boot-up controller connected to a processor and NAND flash memory for controlling the boot-up of a computer device
CN100456272C (zh) 利用快闪存储器引导的系统和方法
US6772276B2 (en) Flash memory command abstraction
US7778074B2 (en) System and method to control one time programmable memory
US7379334B2 (en) Memory card, semiconductor device, and method of controlling memory card
US20070156949A1 (en) Method and apparatus for single chip system boot
US7278001B2 (en) Memory card, semiconductor device, and method of controlling semiconductor memory
US7558152B2 (en) Address counter for nonvolatile memory device
US20060271729A1 (en) Memory card, nonvolatile semiconductor memory, and method of controlling semiconductor memory
US3339183A (en) Copy memory for a digital processor
US20130135007A1 (en) Logic circuit for a semiconductor memory device, and method of managing an operation in the semiconductor memory device
JPH0362243A (ja) 情報処理システムにおいてメモリアクセスを速くする装置
KR100246864B1 (ko) 제2캐시 메모리를 위한 캐시 플러시 방법 및 캐시 메모리를 갖춘 컴퓨터 메모리 시스템
US10522201B2 (en) Methods and systems for serial memory device control
CN101512496A (zh) 用于监控闪存操作的设备和方法
US20020166036A1 (en) Multiple memory block disable function
CN101383186A (zh) 与非门型闪速存储器的编程方法与装置以及读取方法
HK1110404A (en) A method and apparatus to perform a round robin and locking cache replacement scheme

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees