GB2374178B - A method and apparatus to perform a round robin and locking cache replacement scheme - Google Patents

A method and apparatus to perform a round robin and locking cache replacement scheme

Info

Publication number
GB2374178B
GB2374178B GB0215661A GB0215661A GB2374178B GB 2374178 B GB2374178 B GB 2374178B GB 0215661 A GB0215661 A GB 0215661A GB 0215661 A GB0215661 A GB 0215661A GB 2374178 B GB2374178 B GB 2374178B
Authority
GB
United Kingdom
Prior art keywords
perform
round robin
replacement scheme
cache replacement
locking cache
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
GB0215661A
Other languages
English (en)
Other versions
GB2374178A (en
GB0215661D0 (en
Inventor
Lawrence T Clark
Matthew M Clark
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of GB0215661D0 publication Critical patent/GB0215661D0/en
Publication of GB2374178A publication Critical patent/GB2374178A/en
Application granted granted Critical
Publication of GB2374178B publication Critical patent/GB2374178B/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Accessory Devices And Overall Control Thereof (AREA)
  • Materials For Photolithography (AREA)
  • Pharmaceuticals Containing Other Organic And Inorganic Compounds (AREA)
  • Bus Control (AREA)
GB0215661A 1999-12-30 2000-11-27 A method and apparatus to perform a round robin and locking cache replacement scheme Expired - Lifetime GB2374178B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/476,444 US6516384B1 (en) 1999-12-30 1999-12-30 Method and apparatus to perform a round robin and locking cache replacement scheme
PCT/US2000/042305 WO2001050269A2 (en) 1999-12-30 2000-11-27 A method and apparatus to perform a round robin and locking cache replacement scheme

Publications (3)

Publication Number Publication Date
GB0215661D0 GB0215661D0 (en) 2002-08-14
GB2374178A GB2374178A (en) 2002-10-09
GB2374178B true GB2374178B (en) 2004-08-25

Family

ID=23891874

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0215661A Expired - Lifetime GB2374178B (en) 1999-12-30 2000-11-27 A method and apparatus to perform a round robin and locking cache replacement scheme

Country Status (8)

Country Link
US (1) US6516384B1 (enExample)
JP (1) JP2004538536A (enExample)
KR (1) KR100476446B1 (enExample)
CN (2) CN1308841C (enExample)
AU (1) AU3793601A (enExample)
GB (1) GB2374178B (enExample)
TW (1) TW518464B (enExample)
WO (1) WO2001050269A2 (enExample)

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* Cited by examiner, † Cited by third party
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US6694408B1 (en) * 2000-05-01 2004-02-17 Javier Villagomez Scalable replacement method and system in a cache memory
US6772199B1 (en) * 2000-09-14 2004-08-03 International Business Machines Corporation Method and system for enhanced cache efficiency utilizing selective replacement exemption
US6889349B2 (en) * 2001-08-22 2005-05-03 Hewlett-Packard Development Company, L.P. Digital event sampling circuit and method
WO2005050455A1 (ja) * 2003-11-18 2005-06-02 Matsushita Electric Industrial Co., Ltd. キャッシュメモリ及びその制御方法
US7650466B2 (en) 2005-09-21 2010-01-19 Qualcomm Incorporated Method and apparatus for managing cache partitioning using a dynamic boundary
US7523260B2 (en) 2005-12-22 2009-04-21 International Business Machines Corporation Propagating data using mirrored lock caches
JP4712863B2 (ja) * 2006-02-28 2011-06-29 富士通株式会社 アドレス排他制御システムおよびアドレス排他制御方法
US8694737B2 (en) 2010-06-09 2014-04-08 Micron Technology, Inc. Persistent memory for processor main memory
US9448938B2 (en) 2010-06-09 2016-09-20 Micron Technology, Inc. Cache coherence protocol for persistent memories
US8613074B2 (en) 2010-09-30 2013-12-17 Micron Technology, Inc. Security protection for memory content of processor main memory
EP2466451A1 (en) * 2010-12-14 2012-06-20 STMicroelectronics Srl Method for controlling operation of a memory, corresponding system, and computer program product
TWI489344B (zh) * 2013-02-25 2015-06-21 Pixart Imaging Inc 觸控方法以及觸控裝置
CN105515565B (zh) * 2015-12-14 2018-07-13 天津光电通信技术有限公司 一种硬件逻辑资源复用模块及复用实现的方法
US9933947B1 (en) * 2015-12-30 2018-04-03 EMC IP Holding Company LLC Maintaining write consistency on distributed multiple page writes
FR3086409A1 (fr) * 2018-09-26 2020-03-27 Stmicroelectronics (Grenoble 2) Sas Procede de gestion de la fourniture d'informations, en particulier des instructions, a un microprocesseur et systeme correspondant
CN110727463B (zh) * 2019-09-12 2021-08-10 无锡江南计算技术研究所 一种基于动态信用的零级指令循环缓冲预取方法及装置
US11030104B1 (en) * 2020-01-21 2021-06-08 International Business Machines Corporation Picket fence staging in a multi-tier cache

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5029072A (en) * 1985-12-23 1991-07-02 Motorola, Inc. Lock warning mechanism for a cache
EP0568221A1 (en) * 1992-04-29 1993-11-03 Sun Microsystems, Inc. Methods and apparatus for implementing a pseudo-LRU cache memory replacement scheme with a locking feature
GB2284911A (en) * 1993-12-16 1995-06-21 Plessey Semiconductors Ltd Flexible lock-down cache.
US5913224A (en) * 1997-02-26 1999-06-15 Advanced Micro Devices, Inc. Programmable cache including a non-lockable data way and a lockable data way configured to lock real-time data
US5928352A (en) * 1996-09-16 1999-07-27 Intel Corporation Method and apparatus for implementing a fully-associative translation look-aside buffer having a variable numbers of bits representing a virtual address entry
US5937429A (en) * 1997-04-21 1999-08-10 International Business Machines Corporation Cache memory having a selectable cache-line replacement scheme using cache-line registers in a ring configuration with a token indicator

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Publication number Priority date Publication date Assignee Title
US4783735A (en) * 1985-12-19 1988-11-08 Honeywell Bull Inc. Least recently used replacement level generating apparatus
IL96808A (en) * 1990-04-18 1996-03-31 Rambus Inc Introductory / Origin Circuit Agreed Using High-Performance Brokerage
US5408629A (en) * 1992-08-13 1995-04-18 Unisys Corporation Apparatus and method for controlling exclusive access to portions of addressable memory in a multiprocessor system
US5761712A (en) * 1995-06-07 1998-06-02 Advanced Micro Devices Data memory unit and method for storing data into a lockable cache in one clock cycle by previewing the tag array
US5787431A (en) * 1996-12-16 1998-07-28 Borland International, Inc. Database development system with methods for java-string reference lookups of column names
US6044478A (en) * 1997-05-30 2000-03-28 National Semiconductor Corporation Cache with finely granular locked-down regions
US6098152A (en) * 1997-10-17 2000-08-01 International Business Machines Corporation Method and apparatus for miss sequence cache block replacement utilizing a most recently used state
JPH11184695A (ja) * 1997-12-19 1999-07-09 Nec Corp キャッシュメモリ及びキャッシュメモリへのアクセス方法
US6151655A (en) * 1998-04-30 2000-11-21 International Business Machines Corporation Computer system deadlock request resolution using timed pulses
US6073182A (en) * 1998-04-30 2000-06-06 International Business Machines Corporation Method of resolving deadlocks between competing requests in a multiprocessor using global hang pulse logic
US6240489B1 (en) * 1999-02-24 2001-05-29 International Business Machines Corporation Method for implementing a pseudo least recent used (LRU) mechanism in a four-way cache memory within a data processing system

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5029072A (en) * 1985-12-23 1991-07-02 Motorola, Inc. Lock warning mechanism for a cache
EP0568221A1 (en) * 1992-04-29 1993-11-03 Sun Microsystems, Inc. Methods and apparatus for implementing a pseudo-LRU cache memory replacement scheme with a locking feature
GB2284911A (en) * 1993-12-16 1995-06-21 Plessey Semiconductors Ltd Flexible lock-down cache.
US5928352A (en) * 1996-09-16 1999-07-27 Intel Corporation Method and apparatus for implementing a fully-associative translation look-aside buffer having a variable numbers of bits representing a virtual address entry
US5913224A (en) * 1997-02-26 1999-06-15 Advanced Micro Devices, Inc. Programmable cache including a non-lockable data way and a lockable data way configured to lock real-time data
US5937429A (en) * 1997-04-21 1999-08-10 International Business Machines Corporation Cache memory having a selectable cache-line replacement scheme using cache-line registers in a ring configuration with a token indicator

Also Published As

Publication number Publication date
AU3793601A (en) 2001-07-16
GB2374178A (en) 2002-10-09
WO2001050269A3 (en) 2001-12-13
JP2004538536A (ja) 2004-12-24
CN101008924B (zh) 2015-05-13
GB0215661D0 (en) 2002-08-14
KR100476446B1 (ko) 2005-03-16
KR20020097145A (ko) 2002-12-31
CN101008924A (zh) 2007-08-01
WO2001050269A2 (en) 2001-07-12
US6516384B1 (en) 2003-02-04
CN1415093A (zh) 2003-04-30
CN1308841C (zh) 2007-04-04
TW518464B (en) 2003-01-21

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Legal Events

Date Code Title Description
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)
PE20 Patent expired after termination of 20 years

Expiry date: 20201126