WO2001022659A2 - Procede et appareil pour signal de synchronisation reparti - Google Patents

Procede et appareil pour signal de synchronisation reparti Download PDF

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Publication number
WO2001022659A2
WO2001022659A2 PCT/US2000/026336 US0026336W WO0122659A2 WO 2001022659 A2 WO2001022659 A2 WO 2001022659A2 US 0026336 W US0026336 W US 0026336W WO 0122659 A2 WO0122659 A2 WO 0122659A2
Authority
WO
WIPO (PCT)
Prior art keywords
synchronization signal
bus
data
signal
synchronization
Prior art date
Application number
PCT/US2000/026336
Other languages
English (en)
Other versions
WO2001022659A3 (fr
Inventor
Donald W. Moses
Robert W. Moses
Original Assignee
Digital Harmony Technologies, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Harmony Technologies, Inc. filed Critical Digital Harmony Technologies, Inc.
Priority to JP2001525899A priority Critical patent/JP2003524947A/ja
Priority to AU76142/00A priority patent/AU7614200A/en
Publication of WO2001022659A2 publication Critical patent/WO2001022659A2/fr
Publication of WO2001022659A3 publication Critical patent/WO2001022659A3/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40052—High-speed IEEE 1394 serial bus
    • H04L12/40071—Packet processing; Packet format
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0652—Synchronisation among time division multiple access [TDMA] nodes, e.g. time triggered protocol [TTP]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40052—High-speed IEEE 1394 serial bus
    • H04L12/40117—Interconnection of audio or video/imaging devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/436—Interfacing a local distribution network, e.g. communicating with another STB or one or more peripheral devices inside the home
    • H04N21/4363—Adapting the video stream to a specific local network, e.g. a Bluetooth® network
    • H04N21/43632—Adapting the video stream to a specific local network, e.g. a Bluetooth® network involving a wired protocol, e.g. IEEE 1394

Definitions

  • the present invention relates generally to bus system architecture and, more particularly, to a method and apparatus for distributing a synchronization clock signal.
  • Today's consumer electronic devices are increasingly being implemented as special-purpose computer systems, complete with processor, memory, and I/O functionality.
  • the various companies who design and manufacture these devices may have their own particular interconnect technology and communication protocols. Consequently, compatibility problems can occur when connecting devices made by different manufacturers.
  • a DVD player manufactured by one company may be incompatible with an audio surround sound decoder manufactured by another company.
  • the IEEE 1394 standard for a High Performance Serial Bus (also known as the "1394" bus) has been established to facilitate the development of compatible consumer electronics devices.
  • the 1394 bus architecture also provides for standard connections, with each interconnected device being able to communicate with every other such device without requiring individual point-to-point connections between the various devices.
  • the IEEE 1394 standard (IEEE 1394-1995 and IEEE 1394a supplement) is entitled “Standard for a High Performance Serial Bus,” and is based on the ISO/IEC 13213 (ANSI/IEEE 1212) specification, entitled “Information technology — Microprocessor systems — Control and Status Registers (CSR) Architecture for microcomputer buses.”
  • a typical home entertainment system 100 is depicted.
  • the system includes a high speed bus, such as an IEEE 1394 bus 102, that interconnects a variety of electronic devices.
  • the particular configuration depicted is intended solely to show the functional interconnection of representative devices.
  • the 1394 bus architecture supports tree and daisy chain connection configurations.
  • a DVD player 104 is included for playing DVD disks and correspondingly outputting MPEG audio/video data streams on the 1394 bus 102.
  • the audio and video data streams are transported over an isochronous channel of the 1394 bus 102, to an MPEG decoder 108 which demultiplexes the MPEG transport stream and transmits the audio elementary stream to the surround sound decoder 106.
  • the MPEG decoder 106 simultaneously decodes the video elementary stream to a video signal which is typically output to a video monitor (not shown in the diagram).
  • a cable or satellite set- top box 110 receives media from a cable or satellite television provider and outputs an audio/video MPEG data stream on an isochronous channel of the 1394 bus 102.
  • the MPEG decoder 108 demultiplexes this data and sends the audio to the surround decoder 106 and decodes and outputs the video signal.
  • the surround sound decoder 106 receives compressed audio signals from other devices connected to the 1394 bus 102 and decodes the audio.
  • the decoded audio data is then output on the 1394 bus 102 to an amplifier/speaker subsystem 112.
  • the MPEG decoder 108 decodes MPEG transport streams received from various source devices on the 1394 bus 102 and demultiplexes the audio and video.
  • the audio is typically transmitted over the 1394 bus 102 to the surround sound decoder 106.
  • the video is decoded and output to a video monitor for presentation.
  • a controller 114 provides a point of control for all devices in the system 100.
  • the controller 1 14 may also provide a user interface to configure the system when various devices are added or removed.
  • the controller typically includes a user interface for adjusting audio volume, turning devices on and off, selecting channels on the set-top box 110, etc. Indeed, the controller may be the only device a user interacts with (other than inserting disks into the DVD player 104).
  • Each of the interconnected devices shown in the system 100 Figure 1 includes interface circuitry connecting the 1394 bus 102 to the particular application circuitry included in the devices.
  • Such interface circuitry includes both the physical electrical connections (known as the PHY layer) and the data format translation interface (known as the Link layer).
  • PHY layer physical electrical connections
  • Link layer data format translation interface
  • 1394 bus architecture supports transmission of isochronous data packets including time stamp information that can be used to recover the sample rate clock, such as in accordance with the IEC 61883 standard, entitled "Digital Interface for Consumer Audio/Video Equipment.” Because there is no requirement that different data streams be frequency related (i.e., isochronous streams may have free-running sample rates), each receiving device or node must implement a separate clock recovery circuit for each received isochronous channel of the 1394 bus.
  • a functional block diagram depicts the prior art approach of providing time stamps and correspondingly recovering a sample rate clock.
  • the interface circuitry included within a transmitting device or node 200 is depicted, as is a portion of the interface circuitry included within the receiving device or node 202.
  • the transmitting node 200 includes a latch 204 that latches a lower portion of the value stored in a cycle time register 206 included within the Link layer of the interface circuitry.
  • the cycle time register is clocked by oscillator 201.
  • the latch 204 latches the cycle time value every predetermined number of cycles of the sample rate clock (such as a digital audio word clock in the case of audio data transmission).
  • a transfer delay value is added to the latched cycle time register value, and the resulting time stamp is inserted into the header of the corresponding isochronous data packet 208.
  • the value of the transfer delay is determined at system initialization or bus reset.
  • the received time stamp is compared with the corresponding lower portion of the value stored in the receiving node's cycle time register 210, clocked by oscillator 211.
  • a comparator 212 produces a pulse signal in the event of equality, which is then input to a phase-locked loop (PLL) circuit 214 to recover the sample rate clock signal.
  • PLL phase-locked loop
  • the receiving node's cycle time register value is synchronized to the transmitting node's cycle register value by sending periodic updates to the each register from a "cycle master" node. These updates are sent every 125 microseconds, and oscillators 201 and 211 are specified to have frequency accuracy within 100 parts per million, thereby guaranteeing that the values of cycle time registers 206 and 210 are synchronized to less than one least significant bit (LSB) of the cycle time register. Therefore, this method recovers a sample rate clock signal with average frequency equal to the transmitter's sample rate clock signal, and adjustable resolution of 40.9ns (one LSB of the cycle time register).
  • LSB least significant bit
  • sample rate clock degradation is the retiming that data packets undergo in each node, introducing significant delay to the packets as they are transmitted over a heavily populated bus, and different delay to data packets transmitted over different paths in the system topology. This introduces significant, and different, delays to the time stamps and cycle time register updates, thereby introducing significant sample rate clock misalignment between nodes in the system. These degradations may render the resulting sample rate clock signals unsuitable for high performance systems.
  • This synchronization signal 302 is generated by a master device 304, and is received by a number of devices 306.
  • the format of synchronization signal 302 may be a longitudinal time code such as the SMPTE (Society of Motion Picture and Television Engineers) Time Code; or a square wave "word clock" with frequency equal to the sample rate of the digital audio/video signal; or a "black" digital audio or video signal.
  • This separate synchronization signal requires a separate connection means, thereby reducing the ease of installation and cost advantages of the all-in-one-cable IEEE 1394 serial bus.
  • the standard IEEE 1394 serial bus cable does not contain unused conductors, therefore it cannot carry a separate synchronization signal. Furthermore, the low driving impedance of the circuitry interfacing to the IEEE 1394 cable signals precludes adding a voltage carrier to the existing signals using conventional signal coupling means.
  • a method for distributing a synchronization signal in a system of data exchanging node circuits interconnected by a bus.
  • the method includes generating the synchronization signal and coupling the synchronization signal to a portion of the bus that carries another signal, such as a power or data signal.
  • the synchronization signal may include a periodic signal having a frequency proportional to a sampling rate of the data exchanged by the node circuits.
  • the synchronization signal may include a longitudinal time code signal or a data packet carrying a coded message corresponding to the data sample rate.
  • a system having a data source coupled by a bus with a data receiver.
  • the system includes a synchronization signal generator that is connected to a first portion of the bus by coupling circuitry.
  • the synchronization signal generator generates a synchronization signal that is coupled to the first portion of the bus by the coupling circuitry, where the first portion of the bus also carries another signal.
  • the system also includes decoupling circuitry that connects a synchronization signal detector with the first portion of the bus and decouples the synchronization signal from the other signal to provide the synchronization signal to the synchronization signal detector.
  • One or both of the decoupling circuitry and synchronization signal detector may be included in the data receiver.
  • Figure 1 is a functional block diagram that depicts a typical IEEE 1394 system.
  • Figure 2 is a functional block diagram that depicts circuitry for producing time stamps by a transmitting device and circuitry for sample rate clock recovery in a prior art receiving device in an IEEE 1394 system.
  • Figure 3 is a functional block diagram depicting a typical system with a distributed synchronization signal.
  • Figures 4-7 are functional block diagrams depicting the standard methods of coupling a DC power signal to a conductor in an IEEE 1394 serial bus cable.
  • FIGS. 8-11 are functional block diagrams depicting a synchronization signal coupled to the power conductor in an IEEE 1394 serial bus cable by transmitter nodes, in accordance with an embodiment of the present invention.
  • FIGS. 12-15 are functional block diagrams depicting a synchronization signal coupled from the power conductor in an IEEE 1394 serial bus cable by receiver nodes, in accordance with an embodiment of the present invention.
  • Figure 16 is a functional block diagram depicting an electrical circuit which performs Frequency Shift Keying modulation and demodulation, and which constitutes a preferred embodiment of the present invention.
  • Figure 17 is a functional block diagram illustrating the connection of a transmitter and a receiver node.
  • Figure 18 is a functional block diagram illustrating the method of regenerating signal currents.
  • Figure 19 is a functional block diagram of a system arbitrating for automatic selection of a synchronization signal generator.
  • circuitry and methods for recovering a data sample clock from an isochronous data packet stream are conformable to the applicable IEEE 1394, ISO/IEC
  • FIGs 4-7 show the conventional methods of coupling a power signal to a pair of conductors in the IEEE 1394 cable.
  • a typical IEEE 1394 node 400 provides one or more bus connectors 402.
  • pin 1 of the bus connector 402 is fed with DC power via diode 404 and voltage source 406.
  • Capacitor 408 provides filtering and reserve energy. This voltage is carried over the IEEE 1394 bus cable, to other nodes.
  • no power signal is provided.
  • Pin 2 of bus connector 402 provides a ground return path for the DC current:
  • Voltage regulator 410 receives the DC voltage from pin 1 of bus connector 402, and supplies this power to the physical layer interface circuitry.
  • FIGS 8-11 show how the Transmitter Nodes add a synchronization signal to the power conductors in the IEEE 1394 cable.
  • Transformer 512 has been added to the Transmitter Nodes to allow a current, ib, to be modulated onto this DC voltage.
  • the Transmitter Nodes illustrated contain a synchronization signal generator 518 that is buffered by 516 and connected to the primary winding of transformer 512.
  • Capacitors 514 provides DC blocking to prevent the transformer coil from saturating.
  • Capacitors 515 provide DC blocking to isolate power regions on the IEEE 1394 bus.
  • Buffer 516 induces a current, ic, into the transformer 512 primary winding. The current added alternates proportional to the synchronization signal 518.
  • IEEE 1394 connector 502 pin 1 therefore has a combination of DC voltage and current received via diode 504 and alternating current ib received via transformer 512 secondary winding.
  • FIGS. 12-15 show how the Receiver Nodes detect the synchronization signal.
  • the signal is connected to pin 1 of IEEE 1394 bus connector.
  • Transformer 542 has been added to the Receiver Nodes to allow a current, ib, to be demodulated.
  • the Receiver Nodes illustrated contain a synchronization signal detector 548 that is buffered by 546 and connected to the primary winding of transformer 542.
  • Capacitor 544 provides DC blocking to prevent the transformer coil from saturating
  • the current ib from the Transmitter Node energizes the primary winding of transformer 542, causing a current ic to appear in the secondary winding of transformer 542.
  • Current to voltage converter/buffer 546 converts current ic to a voltage, and outputs this to synchronization signal detector 548.
  • Figure 16 depicts an electrical circuit which performs Frequency Shift Keying modulation and demodulation, and which constitutes a preferred embodiment of the present invention.
  • Alternative means of modulating and demodulating the synchronization signal may be employed, such as Amplitude Shift Keying, Minimum Shift Keying, Gaussian Minimum Shift Keying, direct coupling of the baseband signal, or others known to those skilled in the art.
  • the functional blocks required to accomplish the generation and detection of the signal may be composed of discrete logic devices, as in Figure 16, or of logic blocks in a Field Programmable Gate Array or an Application Specific Integrated Circuit. Microprocessors or Digital Signal Processors may also be employed to generate or detect the signals, using algorithms embodied in their firmware.
  • Nodes 500 and 530 exchange a DC voltage and the AC synchronization current over the IEEE 1394 bus cable 520 as described in Figure 17.
  • node A 500 is the synchronization signal transmitter
  • node B 530 is the synchronization signal receiver.
  • the current generated by the Transmitter Node is reflected by a corresponding current, ib, in the secondary winding of transformer 512 in the Receiver Node.
  • the synchronization signal received by 548 is exactly proportional to the synchronization signal transmitted by 518. Therefore, this system has exchanged a synchronization signal between nodes that can be used to represent digital audio, digital video, and other clocks between nodes.
  • this method provides a means to share a synchronization signal amongst a number of nodes.
  • synchronization current ib is degraded by splitting it between many nodes, it could be regenerated at each node before being passed on to the next node, using the method illustrated in Figure 18. This method may also be used to minimize electrical noise propagation between nodes, as an alternative to that illustrated in Figure 8.
  • a protocol for manually or automatically selecting the node in the system to serve as the synchronization signal generator could be introduced to simplify system operation.
  • One method to automatically select this generator node is to designate the node with the lowest bus identification number.
  • an operator could input command to the system specifying the identity of the synchronization signal generator node.
  • FIG 19 shows an example system 600 with five nodes 601- 605.
  • each node is assigned an identification number sequentially from 0 to N-l, where N is equal to the number of nodes on the bus.
  • N is equal to the number of nodes on the bus.
  • Each node on the bus that is capable of generating a synchronization signal advertises its capability at a known address within its address space. Any node 601-605 on the bus can, with a single memory read, determine if other nodes are capable of serving as a synchronization signal generator.
  • each potential synchronization generator 603 and 605 queries other nodes on the network to discover if a synchronization generator with a lower node number exists.
  • the synchronization signal generator node 603 with the lowest node number will not find another synchronization generator with a lower identification number, and will therefore automatically become the synchronization signal generator.
  • the node 605 with a higher node number than the other synchronization generator node 603 will automatically become a synchronization receiver.
  • not all synchronization generators may have the same capability. People configuring the network may wish to select a different synchronization generator than the one that would be selected automatically. This may be done by polling the complete network, and requesting all other nodes, apart from the one desired, to no longer advertise their synchronization generator capability on the network. Causing a bus reset will then move the clock source to the remaining node.
  • a hub device could be implemented that serves as the synchronization signal generator node, with receive-only nodes connected to it.
  • each node could be configured to serve as sender or receiver of the synchronization signal by swapping buffer 516 for buffer 546 and synchronization signal generator 518 for synchronization signal receiver 548 with a simple switching network.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Multimedia (AREA)
  • Small-Scale Networks (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

La présente invention concerne un procédé et un appareil permettant de répartir un signal de synchronisation de façon à calculer des horloges de cadence d'échantillonnage dans des données transmises entre des noeuds dans un système tel qu'un système à bus IEEE 1394 interconnecté. Ce signal de synchronisation est couplé à un conducteur du bus IEEE 1394 par un noeud maître d'horloge, et il est reçu par tous les autres noeuds. Ce signal de synchronisation est couplé au conducteur de bus sans brouiller un signal, tel qu'un signal électrique ou un signal de donnée, porté par ce conducteur. Chaque noeud peut calculer ses horloges de cadence d'échantillonnage en utilisant des moyens horodateurs conventionnels, ou éventuellement en référençant ses horloges de cadence d'échantillonnage pour le signal de synchronisation en vue d'améliorer les résultats. Le format de ce signal de synchronisation peut virtuellement être de n'importe quel type d'horloge de travail ou de code temporel longitudinal, que ces éléments soient standards ou non.
PCT/US2000/026336 1999-09-23 2000-09-25 Procede et appareil pour signal de synchronisation reparti WO2001022659A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2001525899A JP2003524947A (ja) 1999-09-23 2000-09-25 分散同期信号のための方法および装置
AU76142/00A AU7614200A (en) 1999-09-23 2000-09-25 Method and apparatus for distributed synchronization signal

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15573299P 1999-09-23 1999-09-23
US60/155,732 1999-09-23

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WO2001022659A2 true WO2001022659A2 (fr) 2001-03-29
WO2001022659A3 WO2001022659A3 (fr) 2001-12-13

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005076507A1 (fr) * 2004-02-05 2005-08-18 Koninklijke Philips Electronics, N.V. Procede et appareil de synchronisation sur 802.3af
EP1267506A3 (fr) * 2001-06-15 2006-02-15 Nec Corporation Téchnique de synchronisation de réseau

Citations (3)

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Publication number Priority date Publication date Assignee Title
EP0051332A1 (fr) * 1980-10-31 1982-05-12 Koninklijke Philips Electronics N.V. Système de bus à deux fils comprenant un fil d'horloge et un fil de données pour l'interconnexion d'un nombre de stations
US5819051A (en) * 1995-12-29 1998-10-06 Compaq Computer Corporation Low speed serial bus protocol and circuitry
WO1999035587A1 (fr) * 1997-12-30 1999-07-15 Koninklijke Philips Electronics N.V. Procede et appareil de repartition d'un signal d'horloge a une pluralite de noeuds de bus dans un pont de bus

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0051332A1 (fr) * 1980-10-31 1982-05-12 Koninklijke Philips Electronics N.V. Système de bus à deux fils comprenant un fil d'horloge et un fil de données pour l'interconnexion d'un nombre de stations
US5819051A (en) * 1995-12-29 1998-10-06 Compaq Computer Corporation Low speed serial bus protocol and circuitry
WO1999035587A1 (fr) * 1997-12-30 1999-07-15 Koninklijke Philips Electronics N.V. Procede et appareil de repartition d'un signal d'horloge a une pluralite de noeuds de bus dans un pont de bus

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Title
"TRANSMISSION OF AN MPEG ENCODED INFORMATION SIGNAL USING TIME STAMPS" July 1995 (1995-07) , RESEARCH DISCLOSURE,KENNETH MASON PUBLICATIONS, HAMPSHIRE,GB, NR. 375, PAGE(S) 508 XP000524830 ISSN: 0374-4353 the whole document *
BLOKS R H J: "The IEEE-1394 high speed serial bus" 1996 , PHILIPS JOURNAL OF RESEARCH,ELSEVIER, AMSTERDAM,NL, VOL. 50, NR. 1, PAGE(S) 209-216 XP004008212 ISSN: 0165-5817 the whole document *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1267506A3 (fr) * 2001-06-15 2006-02-15 Nec Corporation Téchnique de synchronisation de réseau
US7055050B2 (en) 2001-06-15 2006-05-30 Nec Corporation Network synchronization technique
WO2005076507A1 (fr) * 2004-02-05 2005-08-18 Koninklijke Philips Electronics, N.V. Procede et appareil de synchronisation sur 802.3af
US7885250B2 (en) 2004-02-05 2011-02-08 Koninklijke Philips Electronics N.V. Method and apparatus for synchronization over 802.3AF

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JP2003524947A (ja) 2003-08-19
AU7614200A (en) 2001-04-24
WO2001022659A3 (fr) 2001-12-13

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