WO2001004953A1 - Procede de fabrication de dispositif a semiconducteur presentant une couche metallique flottant au-dessus d'un substrat - Google Patents

Procede de fabrication de dispositif a semiconducteur presentant une couche metallique flottant au-dessus d'un substrat Download PDF

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Publication number
WO2001004953A1
WO2001004953A1 PCT/KR2000/000737 KR0000737W WO0104953A1 WO 2001004953 A1 WO2001004953 A1 WO 2001004953A1 KR 0000737 W KR0000737 W KR 0000737W WO 0104953 A1 WO0104953 A1 WO 0104953A1
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WO
WIPO (PCT)
Prior art keywords
metal layer
layer
metal
forming
masking
Prior art date
Application number
PCT/KR2000/000737
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English (en)
Inventor
Jun Bo Yoon
Chul Hi Han
Eui Sik Yoon
Choong Ki Kim
Original Assignee
Korea Advanced Institute Of Science And Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1019990027603A external-priority patent/KR20000011585A/ko
Application filed by Korea Advanced Institute Of Science And Technology filed Critical Korea Advanced Institute Of Science And Technology
Priority to AU57110/00A priority Critical patent/AU5711000A/en
Publication of WO2001004953A1 publication Critical patent/WO2001004953A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a semiconductor device having 3- dimensional structure and a method for manufacturing the semiconductor device, and more particularly, to a semiconductor device wherein passive elements, such as, inductors, capacitors, micro-switches, and waveguides, are formed over an integrated circuit (IC) which is arranged on the substrate.
  • passive elements such as, inductors, capacitors, micro-switches, and waveguides
  • inductors Even manufactured by the conventional integrated circuit technology, resistors and capacitors may satisfy the requirements of present IC applications.
  • the integration of inductors has been unsuccessful for a long time.
  • Conventional integrated inductors were mainly planar-type spiral inductors.
  • the spiral inductors occupy large area on a substrate.
  • the area of an inductor, whose inductance value satisfies the requirement for general high-frequency devices, should be larger than any other passive elements and even larger than active devices such as a transistor.
  • the conventional spiral inductor inevitably has substrate loss, which stems from parasitic effects due to the contact with a substrate.
  • the thickness of a metal line which can be formed by the conventional integration technique, cannot exceed 5 ⁇ m. Therefore, the conventional spiral inductor has high series resistance and small capacity of current flow. Large series resistance and substrate loss decreases the quality (Q) factor, which is one of the most important characteristics for an inductor, and reduces the frequency where maximum Q factor occurs.
  • the 773 patent suggested that resistance of an inductor could be reduced by using copper of several ⁇ m thickness as material for the inductor.
  • the 773 patent suggested that the polyimide may have thickness of 1 ⁇ m or greater. Contrary to the 773 patent, however, it is expected that a thickness of several tens ⁇ m is required, in order to prevent the inductor from affecting the integrated circuit therebelow. Further, the 773 patent has limitation that temperature of the process for forming the dielectric layer should not affect the integrated circuit therebelow.
  • the method should form a seed metal layer on each and every layer in order to plate upper surface of every polyimide material by using the seed metal layer. This increases the number of processes. Also, the polyimide layer is easily deformed by upper layer processes, such as, processes of seed metal deposition and upper layer lithography. Further, because of seed metal layers which remain between inductors and supporting members, the inductors are not so tightly adhered to the supporting member.
  • a passive element such as, an inductor
  • a method for manufacturing a semiconductor device having a substrate and a metal layer formed over the substrate comprises the steps of forming a first metal layer on the substrate; forming a second metal layer on a portion of the first metal layer such that side surfaces of the second metal layer and an upper surface of other portion of the first metal layer on which the second metal layer is not formed define a recess; forming a third metal layer on the first and second metal layers such that a portion of the third metal layer is located on a predetermined portion of the second metal layer and other portion of the third metal layer fills the recess; removing the second metal layer; and removing a portion of the first metal layer which is not covered by the third metal layer.
  • a method for manufacturing a semiconductor device having a substrate and a metal layer formed over the substrate comprises the steps of: forming a first metal layer on the substrate; forming a first masking layer on a portion of the first metal layer; forming a second metal layer on other portion of the first metal layer on which the first masking layer is not formed; forming a second masking layer on the first masking layer and the second metal layer; removing the first masking layer and a portion of the second masking layer which includes a portion which covers the first masking layer; forming a third metal layer on portions of the first and second metal layers which are exposed by the step of removing the first masking layer and the portion of the second masking layer; removing the second masking layer; removing the second metal layer; and removing the first metal layer except a portion which the third metal layer covers.
  • a method for manufacturing a semiconductor device having a substrate and a metal layer formed over the substrate comprises forming a first metal layer 203 on the substrate 101 ; forming a first masking layer 204 on a portion of the first metal layer 203; forming a second metal layer 205 on other portion of the first metal layer 203 on which the first masking layer 204 is not formed; removing the first masking layer 204 to expose side surfaces of the second metal layer 205 and a surface of the portion of the first metal layer 203, such that the exposed surfaces define a recess; forming a third metal layer 102 on the first and second metal layers 203 and 205 such that the recess is filled with the third metal layer 102; removing a portion of the third metal layer 102 such that the portion which fills the recess is remained; forming a second masking layer 206 on the second and third metal layers 205 and 102; removing a portion of the second masking layer
  • Fig. 1 shows a perspective view of a semiconductor device manufactured in accordance with the present invention
  • Figs. 2a-2f illustrate the method of manufacturing the semiconductor device in accordance with the first embodiment of the present invention
  • Figs. 3a-3f illustrate the method of manufacturing the semiconductor device in accordance with the second embodiment of the present invention
  • Figs. 4a and 4b show Scanning Electron Microscope (SEM) photographs of an on-chip inductor fabricated in accordance with the present invention
  • Figs. 5a and 5b show RF characteristics of the inductors of Figs. 4a and 4b, respectively;
  • Fig. 6 shows resistance and temperature of the inductor manufactured in accordance with the present invention
  • Fig. 7 shows perspective views of various passive semiconductor devices manufactured in accordance with the present invention.
  • Figs. 8a-8i show a process for making various passive elements in accordance with the present invention.
  • Fig. 1 shows a perspective view of a semiconductor device manufactured in accordance with the present invention.
  • the semiconductor device of Fig. 1 comprises a substrate 101 which contains integrated circuits and an inductor floating over the substrate.
  • the inductor may comprise a pillar portion 102 connected to the integrated circuit on the substrate 101 and a spiral portion 104 supported by the pillar portion 102.
  • the semiconductor device may further comprise a supporting member 103.
  • the three portions 101 , 102 and 103 are made by a single step, e.g., a plating step.
  • Figs. 2a-2f illustrate the method of manufacturing the semiconductor device in accordance with the first embodiment of the present invention.
  • a protective layer 201 is formed over a substrate 101 which contains integrated circuits.
  • the protective layer 201 protects and electrically isolates the integrated circuits in the substrate 101.
  • the portion 202 which is not covered by the protective layer 201 will form a contact for connecting the integrated circuit to an element to be formed over the contact.
  • a seed metal layer 203 is deposited over the protective layer 201 and the portion of the substrate 202.
  • the seed metal layer 203 may be deposited using vapor- deposition of TiW and Cu, which are generally used to prevent diffusion of Cu.
  • Ti and Cu was vapor-deposited with the thickness of 0.02 ⁇ m and 0.2 ⁇ m, respectively.
  • first photoresist mold 204 is formed on the seed metal layer 203.
  • the first photoresist mold 204 is formed on a predetermined portion of the seed metal layer 203 where a contact for the integrated circuit in the substrate 101 will be located later.
  • the first photoresist mold 204 may be formed by using conventional lithography technique.
  • the height and width of the first photoresist mold 204 may be selected according to the application of the semiconductor device. In an embodiment, the height and diameter of the first photoresist mold 204 was 55 ⁇ m and 20 ⁇ m, respectively.
  • sacrificial metal mold 205 is formed on a portion of the first metal layer 203.
  • the sacrificial metal mold 205 should not be formed on the predetermined area on which the photoresist mold 204 is formed.
  • the sacrificial metal mold 205 may be formed by using conventional metal plating techniques, such as, nickel plating process.
  • the sacrificial metal mold 205 will be eliminated later.
  • the height of the metal mold 205 determines the height of the passive element to be formed.
  • a second photoresist mold 206 is formed on the first photoresist mold 204 and the sacrificial metal mold 205.
  • the second photoresist mold 206 was formed with the thickness of 20 ⁇ m, by using the same method as that for the first photoresist mold 204.
  • the first photoresist mold 204 and a portion of the second photoresist mold 206 which covers the first photoresist mold 204 are removed. This may be done by conventional development processes.
  • the portion of the second photoresist mold 206, which is to be removed at this step, may be defined by exposing to ultraviolet radiation. As described above, if the first photoresist mold 204 was previously exposed to ultraviolet radiation, then it is possible to remove the portion of the second photoresist mold 206 and the whole first photoresist mold 204 at a single development step.
  • Fig. 2d shows the resulting shape of the device after this removing step.
  • the portion of the second photoresist mold 206 remained on the top surface of the sacrificial metal mold 205 defines the shape of the upper spiraling portion 104 of the inductor.
  • metal is plated on the surfaces of the sacrificial metal mold 205 which were exposed by removing the first and second photoresist molds 204 and 206.
  • copper was plated with the thickness of 15 ⁇ m.
  • copper grows from the top and side surfaces of the sacrificial metal mold 205 that were exposed by removing the first and second photoresist mold 204.
  • the copper growing from the top surface of the sacrificial metal mold 205 forms the spiraling portion of the spiral inductor 104.
  • the copper growing from the side surface of the sacrificial metal mold 205 fills the space where the removed first photoresist mold (204) was located, and covers the predetermined area of the seed metal layer on which the first photoresist mold (204) was formed. In this way, the copper which fills the space where the first photoresist mold 204 was located forms the pillar for supporting the spiraling portion of the spiral inductor 104.
  • Fig. 2e shows the resulting shape of the device after the second photoresist mold 206 was removed.
  • the steps of Fig. 2b through 2e may be repeated to form a passive element having a layered structure. By merely repeating the steps of Fig. 2b through 2e, a passive element having any number of layers may be produced.
  • the sacrificial metal mold 205 is selectively removed, as shown in Fig. 2f.
  • the spiraling portion of the spirial inductor 104 floats over the substrate by relying on the pillar 102 and the supporting member 103.
  • the sacrificial metal mold 205 may be removed by conventional selective etching.
  • an etchant which selectively etches nickel with the etching selectivity of 400:1 was used.
  • the etchant used in this embodiment may include an etchant entitled TOP RIP C-150 manufactured by OKUNO Chemical Industries, Co., Ltd.
  • electro-chemical selective etching may be used.
  • the seed metal layer 203 except the predetermined area which the pillar 102 covers, is etched. In this way, an inductor in accordance with the present invention is manufactured, as shown in Fig. 2f.
  • Figs. 3a-3f illustrate the method of manufacturing the semiconductor device in accordance with the second embodiment of the present invention.
  • the second embodiment is different from the first embodiment in the steps of forming pillar portion 102 of the inductor.
  • a protective layer 201 , a seed metal layer 203, a first photoresist mold 204, and a sacrificial metal mold 205 are formed over the substrate 101 , in the same way as shown in Figs. 2a and 2b.
  • the photoresist mold In the second embodiment of the invention, the photoresist mold
  • the photoresist mold may be removed by using conventional development process as the first embodiment.
  • metal is plated on the top and side surfaces of the sacrificial metal mold 205 which were exposed by removing the photoresist mold 204, as shown in Fig. 3c.
  • copper grows from the top and side surfaces of the sacrificial metal mold 205.
  • the portion of the metal which was formed on the top surface of the sacrificial metal mold 205 is removed. In this way, only the pillar portion 102 is remained, as shown in Fig. 3d. This may be done by using conventional polishing or etching techniques.
  • a second photoresist mold 206 is formed on the remained pillar portion 102 and the sacrificial metal mold 205.
  • the portion of the second photoresist mold 206 formed on the sacrificial metal mold 205 defines the spiraling portion of the inductor.
  • metal is plated on the top surfaces of the sacrificial metal mold 205 which is not covered by the second photoresist mold 206, as shown in Fig. 3c. The metal growing from the top surface of the sacrificial metal mold
  • the spiraling portion of the spiral inductor 104 floats over the substrate by relying on the pillar portion 102.
  • the spiral inductor manufactured according to the second embodiment has substantially the same shape as that of the first embodiment.
  • Figs. 4a and 4b show Scanning Electron Microscope (SEM) photographs of an on-chip inductor fabricated in accordance with the present invention.
  • Bottom conductor 301 which was provided for the purpose of RF measurement in this example, may serve as a shelter for preventing external electro-magnetic effect when it is connected to ground.
  • the bottom conductor 301 may be formed by additional lithography and copper plating steps after the step of Fig. 2a.
  • the spiral inductor 104 comprises a 2.5-turn spiraling portion of 15 ⁇ m in thickness and 20 ⁇ m in width.
  • the spiral inductor 104 floats over the substrate by 50 ⁇ m.
  • Fig. 4b shows a spiral inductor having stacked structure manufactured by repeating the steps of Figs. 2b-
  • the gap between the upper and lower spiraling inductors was 45 ⁇ m.
  • Fig. 5a shows RF characteristics of the inductors of Fig. 4a, which are fabricated on a glass substrate and a silicon substrate.
  • the glass substrate was made of product number #7740 produced by Corning, Co.
  • the silicon substrate had (100) direction and was diffused by Boron with the resistivity of 1-20 ⁇ cm.
  • a photoresist having thickness of 10 m was deposited as an insulator.
  • Fig. 5a illustrates variation of resistance, inductance, and Q value for the inductor at the frequency band of 0.5-10GHz.
  • the solid line represents the result measured by experiment, while the dashed line represents simulation result by using equivalent circuit.
  • the inductor on the glass substrate showed 1.8 nH inductance and maximum Q value of 57 at 10 GHz.
  • the inductor on the silicon substrate showed 1.9 nH inductance and maximum Q value of 35 at 4 GHz.
  • Fig. 5b shows RF characteristics of the inductor of Fig. 4b.
  • the inductor of Fig. 4b has 5nH inductance and maximum Q value of 38 at 5 GHz.
  • an inductor having stacked structure may have an inductance of more than twice larger than a non-stacked inductor with the same area. Therefore, the present invention becomes more advantageous in view of its inductance value per unit area, when a stacked structure is employed.
  • Figs. 5a and 5b the electrical characteristic of the inductor in accordance with the present invention is superior to any inductors manufactured according to the conventional integration technique. Moreover, the present invention has additional merit in that the electrical characteristic of the inductor can be anticipated almost accurately by using simulation of equivalent circuit.
  • Fig. 6 shows resistance and temperature of the inductor in response to current variation. Temperature of the inductor was evaluated by using general relationship between temperature and resistance of a conductor. For temperature coefficient of resistivity for copper, 0.00393/°C was used. As shown in Fig.
  • current density of the inductor is 6 x 10 4 A/cm 2 , when current is 180 mA at 50 °C and width and thickness of the inductor is 20 and 15 ⁇ m, respectively.
  • the current density is 100 times larger than that of a general macroscopic inductor, as described in Transformer and Inductor Design Handbook, New York Marcel Dekker, Inc., pp. 84-89, 1988. Therefore, it can be appreciated that the inductor of first embodiment of the present invention, which was made of copper having thickness of more than 10 ⁇ m, shows large limit of current flow.
  • Fig. 7 shows perspective views of various passive semiconductor devices manufactured in accordance with the present invention.
  • Substrate 101 may also contain integrated circuits as the first embodiment of the present invention.
  • Capacitor 2 is formed by floating upper and lower planar electrodes 603 and 601 over substrate 101 in accordance with the present invention.
  • the capacitor 2 occupies small area and shows low substrate loss, resistance loss, and large Q value.
  • Micro-switch 3 comprises upper and lower plates 606 and 604 manufactured in accordance with the present invention such that they float over the substrate.
  • the lower plate 604 is fixed to the substrate.
  • the micro-switch 3 further comprises control plate 607 fixed to the substrate and dielectric substance located between the upper and control plates 606 and 607 to prevent the upper plate 606 from contacting the control plate 607. If a voltage is driven between the upper and control plates 606 and 607, then the upper plate 606 moves toward the control plate 606 due to the electro-stactic attraction between them. If the upper plate 606 contacts the lower plate 604, current flows between the upper and lower plates 606 and 604. When a dielectric substance, such as the one which is generally used for capacitors, is located between the upper and lower plates 606 and 604, then high frequency signal may flow between the two plates even when the upper plate 606 is not in contact with the lower plate 604.
  • a dielectric substance such as the one which is generally used for capacitors
  • Waveguide 3 comprises signal line 609, bottom plate 610, two side plates 611 , and supporting member 612 for supporting the signal line, manufactured in accordance with the present invention such that the signal line 609 floats over the substrate.
  • the bottom plate 610 and side plates 611 are electrically connected to a ground.
  • wide band wave may be transmitted through the signal line 609 with small loss.
  • the waveguide 3 may further comprise a plurality of additional supporting members 612, when the waveguide 3 is long.
  • Figs. 8a-8i show a process for making various passive elements in accordance with the present invention.
  • the steps of Figs. 8a-8e are basically identical to the steps of Figs. 2a-2e.
  • the process further comprises steps of depositing dielectric substances for the capacitor and switch, and patterning and etching the deposited dielectric substances.
  • the process further comprises steps of depositing seed metal layer 203 over the dielectric substances, from which plating is performed.
  • Fig. 8e shows the shape of the device after the above steps are completed. Then, the steps of Figs. 2b-2e are repeated to form upper electrode 603 of a capacitor, upper plate 606 of a switch, and side plates 611 of a waveguide, as shown in Fig. 8h.
  • sacrificial metal mold 205 is selectively removed and a portion of the seed metal layer 203, which covers the substrate, is etched to isolate the passive elements from each other, in the same way as the step of Fig. 2f.
  • the bottom ground plate 610 of waveguide 3 may be formed by additional lithography process. In this way, at least four kinds of passive elements may be formed on a substrate containing integrated circuits, by one manufacturing process.
  • the specification has described the idea of the present invention by using exemplary passive elements, i.e., inductor 1 , capacitor 2, micro switch 3, and waveguide 4. However, the application of the present invention should not be restricted to those exemplary passive elements.
  • passive electrical elements may be formed over a substrate which contains integrated circuits.
  • the area for integrating various passive elements can be saved and the overall area for the semiconductor device including the integrated circuit and the passive elements may be reduced.
  • passive elements are formed over a substrate, parasitic effect from the substrate can be significantly decreased. It is possible to make a metal line having a thickness which is larger than a metal line which can be manufactured by the conventional integration technique. Therefore, series resistance of passive elements is reduced and capacity of the current flow can be increased. Since the method in accordance with the present invention is composed of semiconductor lithography and plating processes, the method can be easily and accurately performed.
  • the present invention can be applied to any kind of semiconductor devices which comprise passive elements, such as, inductors, capacitors, and resistors. Especially, the present invention can be applied to high- frequency devices, such as, RF ICs which require large inductance value.
  • the present invention can be advantageously applied to various RF monolithic microwave ICs (MMICs) which require high-current inductor loads for RF power amplifiers.
  • MMICs monolithic microwave ICs

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

La présente invention concerne un procédé de fabrication de dispositif à semiconducteur où un élément passif, tel qu'un inducteur (104), flotte au-dessus d'un substrat (101); un circuit intégré étant formé, de façon à réduire la surface globale du dispositif à semiconducteur de manière importante. Selon cette invention, une première couche métallique (203) est formée sur le substrat (101). Une première couche de masquage est formée sur une partie de la première couche métallique (203). Une deuxième couche métallique (205) est formée sur une autre partie de la première couche métallique (203) sur laquelle n'est pas formée la première couche de masquage. Une seconde couche de masquage est formée sur la première couche de masquage et sur la deuxième couche métallique (205). Puis, la première couche de masquage et une partie de la seconde couche de masquage qui comprend une partie recouvrant la première couche de masquage sont enlevées. Une troisième couche métallique (102) est formée sur certaines parties de la première (203) couche métallique et de la deuxième (205) couche métallique exposées lors de l'élimination de la première couche de masquage et de la partie de la seconde couche de masquage. Enfin, la seconde couche de masquage, la deuxième couche métallique (205), et la première couche métallique (203), à l'exception d'une partie recouverte par la troisième couche métallique (102) sont enlevées. Ainsi, on peut ménager la surface d'intégration d'éléments passifs variés et réduire la surface globale du dispositif à semiconducteur comprenant le circuit intégré et les éléments passifs.
PCT/KR2000/000737 1999-07-08 2000-07-07 Procede de fabrication de dispositif a semiconducteur presentant une couche metallique flottant au-dessus d'un substrat WO2001004953A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU57110/00A AU5711000A (en) 1999-07-08 2000-07-07 Method for manufacturing a semiconductor device having a metal layer floating over a substrate

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Application Number Priority Date Filing Date Title
KR1019990027603A KR20000011585A (ko) 1998-07-28 1999-07-08 반도체소자및그제조방법
KR1999/27603 1999-07-08

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WO2001004953A1 true WO2001004953A1 (fr) 2001-01-18

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2833411A1 (fr) * 2001-12-11 2003-06-13 Memscap Procede de fabrication d'un composant electronique incorporant un micro-composant inductif

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US5095357A (en) * 1989-08-18 1992-03-10 Mitsubishi Denki Kabushiki Kaisha Inductive structures for semiconductor integrated circuits
US5111169A (en) * 1989-03-23 1992-05-05 Takeshi Ikeda Lc noise filter
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US5539241A (en) * 1993-01-29 1996-07-23 The Regents Of The University Of California Monolithic passive component
JPH08330517A (ja) * 1995-05-31 1996-12-13 Sanyo Electric Co Ltd 集積回路装置および共振回路
WO1997045873A1 (fr) * 1996-05-31 1997-12-04 Telefonaktiebolaget Lm Ericsson Conducteurs pour circuits integres
US5773870A (en) * 1996-09-10 1998-06-30 National Science Council Membrane type integrated inductor and the process thereof
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US6008102A (en) * 1998-04-09 1999-12-28 Motorola, Inc. Method of forming a three-dimensional integrated inductor
WO2000007218A2 (fr) * 1998-07-28 2000-02-10 Korea Advanced Institute Of Science And Technology Procede permettant de fabriquer un dispositif a semi-conducteur avec une couche flottant au-dessus d'un substrat

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US5111169A (en) * 1989-03-23 1992-05-05 Takeshi Ikeda Lc noise filter
US5095357A (en) * 1989-08-18 1992-03-10 Mitsubishi Denki Kabushiki Kaisha Inductive structures for semiconductor integrated circuits
US5539241A (en) * 1993-01-29 1996-07-23 The Regents Of The University Of California Monolithic passive component
US5478773A (en) * 1994-04-28 1995-12-26 Motorola, Inc. Method of making an electronic device having an integrated inductor
US5446311A (en) * 1994-09-16 1995-08-29 International Business Machines Corporation High-Q inductors in silicon technology without expensive metalization
JPH08330517A (ja) * 1995-05-31 1996-12-13 Sanyo Electric Co Ltd 集積回路装置および共振回路
WO1997045873A1 (fr) * 1996-05-31 1997-12-04 Telefonaktiebolaget Lm Ericsson Conducteurs pour circuits integres
US5773870A (en) * 1996-09-10 1998-06-30 National Science Council Membrane type integrated inductor and the process thereof
US5805043A (en) * 1996-10-02 1998-09-08 Itt Industries, Inc. High Q compact inductors for monolithic integrated circuit applications
US6008102A (en) * 1998-04-09 1999-12-28 Motorola, Inc. Method of forming a three-dimensional integrated inductor
WO2000007218A2 (fr) * 1998-07-28 2000-02-10 Korea Advanced Institute Of Science And Technology Procede permettant de fabriquer un dispositif a semi-conducteur avec une couche flottant au-dessus d'un substrat

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Title
JAE Y. PARK AND MARK G. ALLEN: "Micromachined high Q inductors for high frequency applications", PART OF THE SPIE CONFERENCE ON MICROMACHINED DEVICES AND COMPONENTS IV, PROC. SPIE, vol. 3514, September 1998 (1998-09-01), SANTA CLARA, CALIFORNIA, pages 218 - 228 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2833411A1 (fr) * 2001-12-11 2003-06-13 Memscap Procede de fabrication d'un composant electronique incorporant un micro-composant inductif
EP1320123A1 (fr) * 2001-12-11 2003-06-18 Memscap Procédé de fabrication d'un composant électronique incorporant un micro-composant inductif

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