WO2001003178A1 - Procede pour produire un ensemble electrode - Google Patents

Procede pour produire un ensemble electrode Download PDF

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Publication number
WO2001003178A1
WO2001003178A1 PCT/DE2000/002094 DE0002094W WO0103178A1 WO 2001003178 A1 WO2001003178 A1 WO 2001003178A1 DE 0002094 W DE0002094 W DE 0002094W WO 0103178 A1 WO0103178 A1 WO 0103178A1
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WO
WIPO (PCT)
Prior art keywords
substrate
embossing
electrode
layer
embossing element
Prior art date
Application number
PCT/DE2000/002094
Other languages
German (de)
English (en)
Inventor
Hans-Jörg BEUTEL
Frank Katzenberg
Hubert Schulz
Thomas Hoffmann
Original Assignee
Fraunhofer Gesellschaft zur Förderung der angewandten Forschung e.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fraunhofer Gesellschaft zur Förderung der angewandten Forschung e.V. filed Critical Fraunhofer Gesellschaft zur Förderung der angewandten Forschung e.V.
Publication of WO2001003178A1 publication Critical patent/WO2001003178A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors

Definitions

  • the invention relates to a method for producing an electrode arrangement in a substrate, in which individual electrode regions have a lateral spacing and / or vertical offset from one another, according to the preamble of patent claim 1.
  • Such an electrode arrangement plays an essential role in the field of nanotechnology, the main area of application of the present method.
  • Nanostructuring of electrode arrangements is used, for example, to produce biochemical sensors, with the aid of which impedimetric molecular binding events such as the hybridization of DNA with special oligonucleotides or the binding of antibodies to antigens can be detected.
  • a substrate with an interdigital electrode arrangement is used.
  • the corresponding oligonucleotides or antigens are bound between the electrodes on the substrate.
  • the ratio of the electrode spacing to the layer thickness of the dielectric is close to or less than one. Since the thickness of the binding layer, which in the present application example is composed of a monolayer of oligonucleotides or antigens oriented perpendicular to the surface, is only a few 100 nm, the electrode spacing must accordingly be selected in the same or a smaller dimension.
  • the sensitivity of these methods depends crucially on the electrode spacing of the measuring arrangement used.
  • the electrode arrangements previously used in these methods have distances between the electrodes which are considerably larger than the dimensions of the molecular species to be detected, which are immobilized as a dielectric interaction layer between the electrodes.
  • methods of microstructuring were therefore used in order to be able to produce electrode structures with smaller mutual spacings between the electrodes. For example, from K. Reimer et al. , Sensors & Actuators A46-47 (1995), pp. 66-70 known to produce the required fine electrode structures with the help of electron beam lithography.
  • Another method for producing nano-structured electrode arrangements is known from M.
  • a silicon wafer with a layer structure is provided, in which the structures for the electrodes are first defined by means of photolithography and a subsequent etching step by creating areas of different heights on the surface The height difference of these areas, which corresponds to the later vertical spacing of the electrodes, is predetermined by the thickness of an etched through insulation layer in the layer structure.
  • a metallization layer is vapor-deposited onto the surface, which sic h on areas of different heights. This results in different electrode areas on different levels of the structured surface.
  • This simplified method creates a vertical offset or a distance between the electrodes, which is defined by the layer thickness of the insulator.
  • the electrode structure becomes three-dimensional. An additional lateral structuring of the electrode areas is not necessary, so that the expensive electron beam technology can be avoided.
  • the method still requires a complex manufacturing process with several Lithography and etching steps that increase the cost of the electrode assembly.
  • Indentations are etched into a substrate surface into which the electrode structure is introduced. In this way, a thin sensitive layer can be applied essentially flat to the substrate surface provided with the electrodes.
  • DE 40 13 593 AI describes a thick-film biosensor, which is composed of several layers of a suitable ceramic material.
  • the uppermost layer has several openings, each of which receives partial electrodes applied using thick-film technology.
  • a further method for producing a microelectrode array for amperometric applications can be found in EP 0 653 629 A2.
  • openings are made by means of photoablation in a thin layer of insulating material on a substrate, through which the electrodes are accessible.
  • the electrodes can either be formed as an intermediate layer between the thin insulating layer and the substrate, or can be introduced as an electrically conductive paste into the openings of the thin insulating layer.
  • EP 0 585 933 A2 discloses a planar electrode arrangement for the electrical measurement of biological activities, in which a close-knit
  • Electrode array is used on a substrate.
  • the electrodes are deposited using a vapor deposition process with subsequent structuring by photolithography and created an etching technique.
  • An insulating layer is then applied to the electrode structure and locally removed again at the locations of the respective electrodes using an etching technique.
  • the object of the present invention is to provide a method with which electrode structures, in particular with dimensions in the micrometer and nanometer range, can be implemented in a cost-effective and simple manner.
  • the present invention deviates from the conventional methods of microstructuring and uses mechanical structuring with the aid of an embossing element to produce the distances between the
  • At least one electrically conductive layer for forming the electrode regions is applied to a surface of a substrate.
  • an embossing element is pressed onto the surface, so that there is a lateral distance and / or a vertical offset between individual electrode areas.
  • an electrode structure is created in which individual electrode areas are offset vertically, i.e. an offset in the direction of the surface normal of the substrate, and / or laterally spaced apart by a gap.
  • the size of the offset or distance is preferably controlled via the contact pressure of the embossing element and / or the temperature of the substrate.
  • a stamp can also be used as the stamping element, in which the height of the stamping structure corresponds to the size of the vertical offset to be produced, so that the stamp is completely pressed on in this case.
  • the embossing structure or topography of the embossing element is of course chosen in accordance with the desired structuring of the electrode arrangement.
  • the embossing element will have, for example, rectangular plateaus protruding from the base of the embossing element, which have the shape of the electrode areas define that should lie in a different plane after the embossing process than the electrode areas remaining in the original plane. If these plateaus lie in one plane, the vertical offset of individual electrode areas is identical. If the embossing element has plateaus of different heights, then different electrode spacings can be achieved in a single embossing process.
  • a suitably shaped embossing stamp is used to generate a lateral or horizontal distance between individual electrode regions.
  • different distances between the electrode areas can be achieved by an elevation (hereinafter referred to as cutting edge) of the embossing structure that tapers at a certain angle in the embossing direction.
  • the electrode layer is cut through with the cutting edge, the shape of the cutting edge, such as the radius of curvature of the cutting edge or the angle forming the edge, and the depth of penetration determining the extent of the cut. Controlled penetration depths can be achieved in that the cutting edge has only a certain height above the base of the embossing element.
  • the pressure and temperature ranges required for the embossing process are identical or lower than in the case of creating a vertical offset, since less material has to flow overall.
  • a combination of embossed structures for vertical offset and lateral is also a matter of course Separation possible in an embossing stamp if such electrode structures are to be produced.
  • an embossing element with an embossing structure is used in which the contours of the plateaus define an interdigital structure, so that an interdigital electrode arrangement can be produced with the technique according to the invention.
  • the embossing element itself only has to be produced once, for example using conventional structuring techniques, such as electron beam lithography, and can subsequently be used for the production of a large number of electrode arrangements in series production.
  • a master can be produced by conventional structuring processes, from which a larger number of embossing dies are reproduced. This can be done, for example, by embossing the master into suitably deformable
  • Layers e.g. polymers
  • fixation or transfer of the structure into harder materials can be achieved. This leads to a significant reduction in manufacturing costs compared to the previously known manufacturing technologies for such electrode structures.
  • non-planar, three-dimensional nanostructured electrodes with height differences or a mutual offset or distance of a few nanometers down to the micrometer range can be produced without any problems.
  • the production of flat electrode structures with lateral distances in the Nanometer to micrometer range is possible with the method in a very simple way.
  • the method according to the invention thus enables the production of electrode structures in the micrometer and nanometer range in a surprisingly simple manner and very inexpensively, so that nothing stands in the way of the use of sensors based on this technology as single use products in the biomedical field.
  • embossing element it is not necessary for the embossing element to come into direct contact with the conductive layer. Rather, another layer or layer sequence, for example one, can be applied to the conductive layer before the embossing process is carried out
  • Insulation layer as long as the desired result of the embossing is still achieved.
  • the present method is not limited to the stamping of a single electrically conductive layer. Rather, a multi-layer System of alternating electrically conductive and insulating layers can be provided on the substrate or applied thereon. Completely different materials can be used for both the conductive and the insulating layers, depending on the desired function.
  • the subsequent embossing process allows individual areas of this entire layer system to be displaced vertically with respect to one another. For example, a
  • Electrode region of an initially lying electrically conductive layer comes into contact with a lower lying electrically conductive layer, so that lower lying layer regions can be contacted through the opening created.
  • a substrate made of plastic for example, can be used as the carrier for the electrically conductive layer or the layer system.
  • a carrier substrate of any hardness can be used, on which a layer with a lower hardness than that of the at least one electrically conductive layer is applied
  • Embossing element is applied.
  • the thickness of this layer must be greater than the vertical offset of the electrode areas to be generated.
  • Figure 2 shows an example of the implementation of the
  • FIG. 3 shows an example of different embossing structures that can be used on an embossing stamp.
  • FIG. 1 shows a substrate 1 with an electrically conductive layer 2 applied thereon to form the electrodes.
  • a stamp 3 is used which has a topography of the embossing surface in the form of rectangular plateaus 4 which have the same height.
  • a substrate made of polymethylacrylate (PMMA) was used as substrate 1.
  • PMMA polymethylacrylate
  • the PMMA surface was then vapor-deposited with a 20 nm thick layer 2 of silver as the electrically conductive layer to be structured.
  • a silicon wafer in the submicrometer range was structured by means of electron beam lithography with lines at a distance of 500 nm to 2 ⁇ m.
  • This stamp was then embossed with a pressure of approx. 100 * 10 5 Pa and at a temperature of approx. 200 ° C through the metallization layer 2 into the PMMA layer 1.
  • the metal layer was sheared off at the edges of the structures 4 of the stamp and offset by approximately 100 nm.
  • the penetration depth of the stamp and thus the offset of the metallization layer in the depth can be controlled.
  • FIG. 2 shows a substrate 1 with an applied layer sequence of an electrically conductive first layer 2 to form first electrodes, an insulating intermediate layer 5 and an electrically conductive second layer 6 to form second electrodes.
  • a stamp 7 is also used, which has a topography of the embossing surface in the form of rectangular plateaus 8, the plateaus in this case having different heights.
  • the layers subjected to the embossing process are displaced in accordance with the topography of the embossing element in the direction of the surface normal of the layers, so that there is a height offset between individual regions of the electrodes formed by the layers.
  • Offset can occur via the topography or the profile of the embossing structures (height and spacing of the structures) of the embossing element, the process parameters (pressure, temperature, time, embossing depth) and the material properties (plasticity, rigidity, etc.) and the thickness of the various layers to be controlled.
  • the process parameters pressure, temperature, time, embossing depth
  • the material properties plasticity, rigidity, etc.
  • FIG. 3 shows various examples of embossed structures that can be used alone or in combination in the method according to the invention.
  • pointed shapes 9-11 are also shown.
  • a horizontal spacing or a lateral separation between individual electrode regions can be produced by means of these cutting-shaped elevations or cutting edges 9-11, depending on the shape and penetration depth of the latter Structures in the electrically conductive layers and the underlying material depends and can be controlled specifically.
  • Layer 2 are generated by which the electrode regions are spaced apart.
  • Such a stamp for cutting through the electrode layers for generating a lateral distance can be produced, for example, by anisotropic wet etching of silicon. With this etching technique, tapered shapes can be easily achieved in the silicon, which act like a cutting tool and when stamped on

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Investigating Or Analyzing Materials By The Use Of Electric Means (AREA)
  • Micromachines (AREA)

Abstract

L'invention concerne un procédé pour produire, dans un substrat (1), un ensemble électrode dans lequel des zones d'électrodes individuelles (2a, 2b, 6a, 6b) sont placées avec un écart latéral et/ou un décalage vertical les unes par rapport aux autres. Selon le procédé de l'invention, au moins une couche électroconductrice (2, 6) servant à former les zones d'électrodes est placée sur une surface d'un substrat (1). Lors d'une autre étape, un élément d'estampage (3, 7) est appliqué sur la surface de façon à former un écart latéral et/ou un décalage vertical entre les zones d'électrodes individuelles (2a, 2b, 6a, 6b). Le retrait de l'élément d'estampage laisse apparaître une structure d'électrode dans laquelle les zones d'électrodes individuelles sont séparées par un écart latéral et/ou un décalage vertical. Ce procédé permet de produire, de manière étonnamment simple et de façon très économique, des structures d'électrodes de l'ordre du micron et du nanomètre.
PCT/DE2000/002094 1999-07-01 2000-06-26 Procede pour produire un ensemble electrode WO2001003178A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19930104A DE19930104C1 (de) 1999-07-01 1999-07-01 Verfahren zur Herstellung einer Elektrodenanordnung
DE19930104.2 1999-07-01

Publications (1)

Publication Number Publication Date
WO2001003178A1 true WO2001003178A1 (fr) 2001-01-11

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PCT/DE2000/002094 WO2001003178A1 (fr) 1999-07-01 2000-06-26 Procede pour produire un ensemble electrode

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DE (1) DE19930104C1 (fr)
WO (1) WO2001003178A1 (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003080502A1 (fr) * 2002-03-25 2003-10-02 Matvice Ehf. Procede et dispositif permettant de traiter des structures nanoscopiques
DE102006030267A1 (de) * 2006-06-30 2008-01-03 Advanced Micro Devices, Inc., Sunnyvale Nano-Einprägetechnik mit erhöhter Flexibilität in Bezug auf die Justierung und die Formung von Strukturelementen
US8460256B2 (en) 2009-07-15 2013-06-11 Allegiance Corporation Collapsible fluid collection and disposal system and related methods
US8500706B2 (en) 2007-03-23 2013-08-06 Allegiance Corporation Fluid collection and disposal system having interchangeable collection and other features and methods relating thereto
US9889239B2 (en) 2007-03-23 2018-02-13 Allegiance Corporation Fluid collection and disposal system and related methods

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102009018849B4 (de) * 2009-04-24 2013-06-06 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Masterstruktur zum Prägen und/oder Bedrucken eines Grundmaterials, Vorrichtung zum kontinuierlichen Prägen und/oder Bedrucken eines Grundmaterials und Verfahren zum Herstellen einer Masterstruktur zum Prägen und/oder Bedrucken eines Grundmaterials

Citations (3)

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Publication number Priority date Publication date Assignee Title
US5173442A (en) * 1990-07-23 1992-12-22 Microelectronics And Computer Technology Corporation Methods of forming channels and vias in insulating layers
US5547902A (en) * 1995-01-18 1996-08-20 Advanced Micro Devices, Inc. Post hot working process for semiconductors
WO1999010929A2 (fr) * 1997-08-22 1999-03-04 Koninklijke Philips Electronics N.V. Procede d'interconnexion verticale entre des dispositifs micro-electroniques a couche mince

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GB8927377D0 (en) * 1989-12-04 1990-01-31 Univ Edinburgh Improvements in and relating to amperometric assays
DE4013593A1 (de) * 1990-04-27 1991-10-31 Biotechnolog Forschung Gmbh Verfahren und sensor fuer amperometrische messprinzipien mit dickschicht-biosensoren
DE4107220A1 (de) * 1991-03-07 1992-09-10 Rump Elektronik Tech Phthalocyaninsensor bei dem die kontaktgebenden flaechen in einer ebene zum substrat angeordnet sind
DE69333945T2 (de) * 1992-09-04 2006-06-29 Matsushita Electric Industrial Co., Ltd., Kadoma Flache Elektrode
US5663399A (en) * 1994-10-28 1997-09-02 Asahi Glass Company Ltd. Method for producing fluorine-containing silicone compound
DE19610115C2 (de) * 1996-03-14 2000-11-23 Fraunhofer Ges Forschung Detektion von Molekülen und Molekülkomplexen

Patent Citations (3)

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Publication number Priority date Publication date Assignee Title
US5173442A (en) * 1990-07-23 1992-12-22 Microelectronics And Computer Technology Corporation Methods of forming channels and vias in insulating layers
US5547902A (en) * 1995-01-18 1996-08-20 Advanced Micro Devices, Inc. Post hot working process for semiconductors
WO1999010929A2 (fr) * 1997-08-22 1999-03-04 Koninklijke Philips Electronics N.V. Procede d'interconnexion verticale entre des dispositifs micro-electroniques a couche mince

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003080502A1 (fr) * 2002-03-25 2003-10-02 Matvice Ehf. Procede et dispositif permettant de traiter des structures nanoscopiques
US7416634B2 (en) 2002-03-25 2008-08-26 Matvice Ehf Method and apparatus for processing nanoscopic structures
DE102006030267A1 (de) * 2006-06-30 2008-01-03 Advanced Micro Devices, Inc., Sunnyvale Nano-Einprägetechnik mit erhöhter Flexibilität in Bezug auf die Justierung und die Formung von Strukturelementen
DE102006030267B4 (de) * 2006-06-30 2009-04-16 Advanced Micro Devices, Inc., Sunnyvale Nano-Einprägetechnik mit erhöhter Flexibilität in Bezug auf die Justierung und die Formung von Strukturelementen
US7928004B2 (en) 2006-06-30 2011-04-19 Advanced Micro Devices, Inc. Nano imprint technique with increased flexibility with respect to alignment and feature shaping
US8500706B2 (en) 2007-03-23 2013-08-06 Allegiance Corporation Fluid collection and disposal system having interchangeable collection and other features and methods relating thereto
US9604778B2 (en) 2007-03-23 2017-03-28 Allegiance Corporation Fluid collection and disposal system having interchangeable collection and other features and methods relating thereto
US9889239B2 (en) 2007-03-23 2018-02-13 Allegiance Corporation Fluid collection and disposal system and related methods
US10252856B2 (en) 2007-03-23 2019-04-09 Allegiance Corporation Fluid collection and disposal system having interchangeable collection and other features and methods relating thereof
US8460256B2 (en) 2009-07-15 2013-06-11 Allegiance Corporation Collapsible fluid collection and disposal system and related methods

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Publication number Publication date
DE19930104C1 (de) 2001-02-15

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