WO2000054259A1 - Electronic device - Google Patents

Abstract

A signal processing system that converts an analog data signal to a digital data signal comprises a current-input/current-output circuit as a filter circuit (FIL), and a current-input circuit as an analog-to-digital converter (ADC). The front stage of the filter circuit includes a voltage-to-current converting circuit or voltage-input/current-output amplifier (VGA) to convert received analog input signals to electric current.

Description

 Details

Technical field

 The present invention relates to an analog signal processing technology and a signal processing system for converting an analog data signal into a digital data signal. For example, the present invention relates to a technology effective for a hard disk drive that processes a signal read from a magnetic disk. In particular, the speed and power consumption of read channels that generate read and write signals are increased, and as shown in Fig. 11, the speed and size of electronic devices, including hard disk devices, are reduced. It relates to technologies that are effective for economic and economic development.

Background art

In response to recent developments in the information society, recording devices for digitizing and recording various kinds of information are required to have higher speeds and larger capacities. A hard disk drive is one of the recording devices that meet such demands. The hard disk drive generates a pulse current to drive the magnetic head HD and write the binarized digital data to the magnetic recording disk as shown in Fig. 12, for example. Read / write execution unit 11 including a write amplifier to read and a read amplifier to amplify the data signal read via the magnetic head HD, and the data read by the read / write execution unit 11 A signal processing unit 12 that performs data collation, a format control unit 13 that has functions such as converting the data into a format suitable for data exchange with external devices, and a disk rotation axis. Driving spindle motor Voice coil motor that moves the arm (big-up) that holds the SPM and magnetic head Servo controller that controls the VCM and adjusts the disk rotation speed and the position of J and H 1 、 Host computer overnight 2 It comprises a disk control unit 15 for connecting to external devices such as 0 and controlling the entire disk device. Among them, the signal processing unit 12 that performs data collation of data read from the disk requires particularly high-speed signal processing because it affects the read / write speed of the disk, so amplifiers, filters, analog / digital conversion, etc. Integrated circuit (hereinafter referred to as read channel LSI) that optimally incorporates an analog signal processing circuit (referred to as a read channel) including a digital signal processor (hereinafter referred to as an A / D converter). Is realized.

 FIG. 13 shows a schematic configuration example on the read processing side of the function blocks built in the read channel LSI.

 The variable gain amplifying circuit V GA is a read signal amplifying circuit, and is a functional circuit that variably amplifies the amplitude of the read signal degraded and attenuated by nonlinear electromagnetic characteristics of a magnetic head or the like to a predetermined amplitude level.

 The filter circuit FIL removes the aliasing noise caused by the A / D conversion operation in the subsequent A / D converter ADC in advance, and also extracts the maximum effective information from the read signal in order to extract the maximum useful information from the read signal. It is required to switch the cutoff frequency frequently, specifically at intervals of about 1 MHz, in accordance with the different data rates between the outer part and the outer part.

 The digital signal processing unit DSP detects the amplitude level of the read signal, the data speed, etc., and performs the above-mentioned variable gain amplification circuit VGA and filter circuit FIL so that the write data can be compared with the read signal. , And the timing information such as the sampling clock of the A / D converter is generated and supplied to the timing control circuit TGC in the same semiconductor integrated circuit or a control LSI such as an external microcomputer, etc. For example, the feedback control of the variable gain amplifier VGA is performed so that the detected level becomes a desired value.

Further, the frequency and phase of the sampling clock of the A / D converter ADC are determined by a synthesizer or a phase locked loop (PLL) circuit provided in the timing control circuit TGC based on the data rate detection signal. It is adjusted by controlling. By the way, in a conventional read channel LSI including the above-described functional circuits, each functional circuit is realized by a circuit configuration of voltage input and voltage output. For example, regarding the A / D conversion circuit, the first document: I'S 'S' 98, Digest to Technical Vapor Paper, 3 papers published in Session 9, 3 A. As shown in 9.6 to 9.8, February 1998 (ISSCC98, Digest of Technical Papers, February 1998, FA 9.6-9.8), both input analog signals are voltages.

 On the other hand, non-sampling (continuous 'time') current-driven filter circuits, which have excellent high-frequency characteristics and can be realized with low power consumption using a low power supply voltage, have been widely used in recent years. However, many of them are so-called gm-C circuits or OTAs (Operational Transconductance) that convert input-voltage to current and charge / discharge the current to / from the capacity C to convert it to voltage.

Amplifier) It is realized by one C circuit. An example of this is the second of the literature; eye I over-I - - I -, journal O blanking Sori' Dosutetosa - Kidzudzu, ₃ 2 Certificates No. 4, 5 12 pages from 499 pages, April 1997 (IEEE Journal of Solid -State Circuits, VOL. 32, NO. 4, April 1997, pp. 499-513).

As another method of the current drive type filter circuit, a circuit using a current mirror circuit as a primary complete integration circuit and a coefficient circuit has been proposed. The input signal and the output signal are current. However, a voltage signal is used as an input signal for the higher-order filter required for a read channel LSI configured by combining these basic circuits, specifically for the 7th-order single-pass filter. A voltage / current conversion circuit is added before the filter. An example of this is the third article; I-II-II-II, Journal of Solid State Circuits, Vol. 33, No. 3, pages 427 to 438, March 1998 (IEEE Journal of Solid-State Circuits, VOL. 33, NO. 3, March 1998, pp. 427-438). Furthermore, although not described in the above-mentioned known documents, the current from the filter circuit In order to supply the output signal to the above-mentioned voltage input type A / D converter, a current / voltage converter is indispensable between the filter circuit and the A / D converter.

 However, the above-described configuration of the conventional analog 'front' end section has the following problems. That is, it is necessary to provide a plurality of voltage-Z current conversion circuits or current / voltage conversion circuits inside each functional circuit or between the circuits, thereby increasing the circuit scale and power consumption. What is even more problematic is that the voltage / current conversion causes deterioration of signal amplitude and frequency band and signal phase shift, and it is necessary to respond to the demand for higher-speed hard disk drive devices, which will increase in the future. It is difficult.

 Furthermore, the complete integration circuit used in the filter circuit has a characteristic that the input / output current gain is inversely proportional to the signal frequency in a range not limited by the power supply voltage, so that the design of the filter circuit is relatively easy. is there. On the other hand, however, the complete integration circuit cannot be used alone as a filter circuit because, for example, if a DC current is input or an unintended input offset occurs, the gain becomes infinite and the output signal is saturated. A separate feedback circuit is required for stabilization. Therefore, since the primary complete current integrator has a feedback path inside it and also has a separate feedback circuit as the primary filter, a larger number of filters are required to realize higher-order filters. It requires transistors and power consumption. An object of the present invention is to realize an electronic device capable of performing analog signal processing by high-speed and low-frequency operation without increasing a circuit scale and power consumption. For example, a high-speed and high-speed processing of a read / write signal of a magnetic disk is realized. An object of the present invention is to provide a low power consumption read channel LSI.

 Further, another object of the present invention is to contribute to the realization of a hard disk drive device that can respond to a demand for high-speed operation in a field by using the above-described high-speed read channel LSI, and furthermore, a hard disk device.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Disclosure of the invention

 The following is a brief description of an outline of a typical invention disclosed in the present application.

 That is, in a signal processing system that converts an analog data signal into a digital data signal, a current input / current output circuit is used as a filter circuit constituting the system, and a current input circuit is used as an A / D converter. And a voltage / current conversion circuit (or voltage input / current output type amplifier) that converts the received analog input signal into a current and outputs the current, in front of the filter circuit. Further, the filter circuit is configured using an incomplete current integration circuit.

 According to the above-described means, high frequency characteristics are improved as compared with a system using a voltage input / voltage output filter circuit and a voltage input A / D converter. In addition, a voltage / current converter is provided before the filter circuit, the filter circuit is a current output type, and the A / D converter is a current input type. There is no need to provide a voltage / current conversion circuit between them, which simplifies the entire system and reduces power consumption. Moreover, in a system using a current input / voltage output type filter circuit as in the past, when a higher-order filter circuit is configured, the primary and secondary low-order filter circuits are combined. In this case, a voltage / current conversion circuit is required between each filter, whereas in the present invention, a current input / current output type filter circuit is used. Since the current conversion circuit is not required, power consumption can be reduced accordingly.

When the present invention is applied to a hard disk drive, as shown in FIG. 1, it is assumed that the output signal of the read amplifier, that is, the input signal to the read channel LSI is a voltage signal. The voltage / current conversion means is provided in the variable gain amplifier VGA provided at the first stage of the analog signal processing unit, and the amplitude of the output current signal of the variable gain amplifier VGA is registered from the external microcomputer and the like described above. Rewriting REG settings And the output current signal of the variable gain amplifier circuit VGA can be directly input to the input terminal of the current input / current output filter circuit at the subsequent stage.

 In addition, the track 'hold circuit (also called sample' hold circuit) required to minimize the conversion accuracy degradation of the high-speed A / D converter circuit is a current signal track-hold circuit, and the current input 'current Output type filter The output current signal of the circuit can be directly input to the AZD conversion circuit. As a result, it is possible to minimize the deterioration of the amplitude and frequency band of the output signal from each of the functional circuits.

 In addition, the current input / current output filter circuit is configured using a first-order imperfect integration circuit having no feedback path as a coefficient circuit. The imperfect integration circuit can realize a stable first-order filter by itself because the output converges to a constant value for DC current input, similar to a single-pass filter consisting of a resistor and a capacitor, which is a passive element. . As a result, the number of transistors is significantly reduced in order to achieve higher-order filtering compared to using a first-order complete integration circuit with a feedback path in the integration circuit as in a conventional filtering circuit. And power consumption can be reduced.

 Specific configuration examples of the variable gain circuit, the voltage / current conversion circuit, the current integration circuit, the filter circuit, and the current signal track / hold circuit included in the description of the above-described means will be described later in the description of the embodiments. Will be revealed in BRIEF DESCRIPTION OF THE FIGURES

 FIG. 1 is a block diagram of a lead channel LSI used in a hard disk drive according to the present invention.

 FIG. 2 is a circuit diagram showing a voltage / current conversion circuit constituting the read channel LSI,

FIG. 3 is a circuit diagram showing an embodiment of a voltage / current conversion circuit constituting a read channel LSI and a bias current circuit, Figure 4 is a circuit diagram showing the current offset compensation circuit of the voltage / current conversion circuit that constitutes the read channel LSI.

 Fig. 5 shows the input / voltage-drain current characteristic diagram showing the simulation results of the voltage / current conversion circuit shown in Fig. 3.

 Figure 6 is a block diagram of a secondary filter circuit using an incomplete current integration circuit.

 Figure 7 shows a block diagram of a primary filter circuit using an incomplete current integration circuit.

 Figure 8 is a block diagram of an equiripple 7th-order low-pass filter circuit configured using an incomplete current integration circuit.

 FIG. 9 is a frequency characteristic diagram of the group delay and current gain showing the analysis simulation result of the seventh-order low-pass filter circuit shown in FIG.

 FIG. 10 is a circuit diagram of a current track / hold circuit for an AZD converter. FIG. 11 is a block diagram of an electronic device according to the present invention.

 FIG. 12 is a block diagram showing a configuration example of a hard disk drive device according to the present invention,

 FIG. 13 is a block diagram showing the function of a conventional read channel for a hard disk.

 FIG. 14 is a circuit diagram showing an example of a conventional voltage / current conversion circuit,

 FIG. 15 is a circuit diagram showing another example of a conventional voltage / current conversion circuit.

 FIG. 16 is a circuit diagram of an incomplete integration circuit used for a current input / current output type filter constituting the device of the present invention.

 FIG. 17 is a circuit diagram showing an example of a conventional complete current integration circuit.

 Fig. 18 is a block diagram of a conventional secondary filter circuit using a complete current integration circuit.

Fig. 19 is a block diagram of a conventional primary filter circuit using a complete current integration circuit. BEST MODE FOR CARRYING OUT THE INVENTION

 FIG. 1 is a block diagram showing an example of the configuration of a read channel LSI 10 used in a hard disk device effective according to the present invention.

 VGA is a variable gain amplifying circuit that amplifies a read signal from a magnetic disk, and has a function of variably amplifying the amplitude of a read signal degraded and attenuated by nonlinear electromagnetic characteristics of a magnetic head or the like to a predetermined amplitude level. FIL is a filter circuit for removing in advance the aliasing noise caused by the AZD conversion operation in the subsequent A / D converter ADC, and for extracting the maximum useful information from the read signal.

 The DSP detects the read signal level and data rate, etc., and controls the variable gain amplifier circuit VGA and filter circuit FIL control information and A / D converter so that the write data can be compared with the read signal. This is a digital signal processing circuit that generates timing information such as the sampling clock of ADC. TGC is a timing control circuit that forms and outputs control signals to the variable gain amplifier circuit VGA, filter circuit FIL, and A / D converter ADC based on control information from the digital signal processing circuit DSP. The variable gain amplifier circuit VGA is feedback-controlled by the control signal so that the detected level becomes a desired value. On the other hand, in the filter circuit FIL, the cut-off frequency is switched at intervals of approximately 1 MHz according to different data rates at the inner and outer peripheral portions of the disk by a control signal from the timing control circuit portion TGC. .

 Further, in the A / D converter ADC, the timing of the sampling clock 0 s is adjusted by the timing control circuit unit TGC to correct the deviation of the sampling point of the read signal waveform.

In this embodiment, a resistor REG is provided in association with the variable gain amplifier circuit VGA. The variable gain amplifier circuit VGA adjusts the amplitude of the output current signal from an external microcomputer or the like. It is configured to be controlled by rewriting the set value of. Similarly, the above filter circuit FIL For this purpose, a register is provided that can rewrite the set value from an external microcomputer, etc., and the frequency characteristics such as the power-off frequency of the filter circuit can be changed by the set value of the register. You may.

 Although not particularly limited, the above-mentioned variable gain amplifier circuit VGA, resistor circuit REG, filter circuit FIL, A / D converter ADC, digital signal processing section DSP, and timing control circuit section TGC are similar to a single crystal silicon substrate. It is formed as a semiconductor integrated circuit on a single semiconductor chip. In addition, although not shown, the read-related circuit described above and the write-related circuit that forms and outputs a write signal to be supplied to a write amplifier that drives the magnetic head HD and writes data to a disk are the same semiconductor. Formed on a chip. In the system shown in Fig. 1, the magnetically recorded information on the disk is converted into an electric signal by a magnetic head (hereinafter referred to as MR head) HD using, for example, a magnetoresistive element, and amplified by a read amplifier 11 Is done. The output signal of the read amplifier 11 is generally a voltage signal.

 In the read channel LSI of this embodiment, the output signal of the read amplifier 11, that is, the input signal of the read channel LSI is a voltage signal, and the variable gain amplifier circuit VGA to which the signal is input corresponds to, for example, Using a voltage input / current output type amplifier circuit as shown in Fig. 2 to Fig. 4, the output current signal of the variable gain amplifier circuit VGA is configured to be directly input to the subsequent filter circuit FIL. A current input / current output type filter circuit as shown in Figs. 6 to 8 is used as the filter circuit FIL.

 Furthermore, the A / D converter ADC uses a current signal track and hold circuit as shown in Figure 10 to minimize the deterioration of the conversion accuracy of the circuit during high-speed operation. It is configured so that the output current signal of the FIL filter circuit can be directly input to the A / D converter ADC.

As described above, by using the current input / current output type amplifier circuit and filter circuit, the amplitude of the output signal from each of the above functional circuits, deterioration of the frequency band, signal Can be minimized.

 In addition, instead of using a voltage input / current output type amplifier circuit as shown in Fig. 2 as a variable gain amplifier circuit VGA, a configuration in which a voltage / current conversion circuit is provided before the variable gain current amplifier circuit It is also possible. By the way, the following conventional techniques are known as voltage / current conversion circuits.

FIG. 14 shows a first example of a conventional voltage / current conversion circuit. In this circuit, the drain terminal is connected to the current mirror circuit CM for positive and negative symmetric voltage input signals Vin ⁺ and Vin_. It combines the drain currents of the two MOS transistors Ml and M3 and the drain currents of M2 and M4, and converts the current flowing through M1 and M3 corresponding to the positive voltage input signal Vin ⁺ to the negative voltage input signal ViiT It is configured to subtract the current flowing through M4 and M2. Thus, a linear current output signal lout with respect to the voltage input signals Vin ⁺ and ViiT can be obtained.

 The amplitude of the current output signal lout is controlled by the value of the bias potential difference VB between the gates of Ml and M3 and between the gates of M2 and M4. Such a circuit is described in the fourth document-IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.26, NO.9, SEPTEMBER 1991, ppl293-1301, and the like.

 FIG. 15 shows a second example of the voltage / current conversion circuit according to the prior art described in the third document.

This circuit has two MOS transistors Ml and M2 that operate in a triode region (non-saturation region) with different bias operation points between the drain and source for positive and negative symmetric voltage input signals Vin + and ViiT. The drain currents of M3 and M4 are combined, and the current flowing to M1 and M4 corresponding to the positive input voltage signal Vin ⁺ is subtracted from the negative input current flowing to M2 and M3 corresponding to the voltage signal ViiT. By subtracting, a linear current output signal I out with respect to the voltage input signal can be obtained. The output current amplitude is in series with the drain side of M1 to M4. It is controlled by the difference between the bias voltage Vwp and V ™ applied to the gate terminals of the inserted MOS transistors M5 to M8.

 However, in each of the conventional voltage / current conversion circuits described above, the linear output current signal is obtained as the difference between the drain current and the positive / negative symmetric voltage input signal, and sufficient linearity is obtained with a single-phase voltage input signal. I can't. In order to obtain the current difference, it is necessary to invert one of the positive and negative current signals and add them. For example, the simplest and most practical circuit for current inversion and addition uses a current mirror circuit, but inverting only one of the signals is an AC signal, especially for signals in the high-frequency region. This causes a delay difference between the positive and negative current signals, making it impossible to obtain an accurate difference between the positive and negative current signals. Therefore, in the circuits of FIGS. 14 and 15, the differential input type is used, which increases the number of constituent elements of the circuit.

When a high-speed, high-frequency circuit is realized by MOS transistors, it is common to use only N-channel transistors that are faster than P-channel transistors as much as possible. Since a P-channel transistor has to be used in a current mirror circuit as an inverting and adding circuit to obtain the value, application in a high frequency region is limited. That is, the operating band of the circuit is limited. FIG. 2 shows a first embodiment of a voltage / current conversion circuit according to the present invention, which has been made to solve the above-mentioned problems of the prior art. A first constant current source (current value IB), a first MOS transistor Ml having a fixed potential (V GC) applied to its gate, and a second MOS transistor Ml having a gate connected to the drain of the MOS transistor Ml. The MOS transistor M2 is connected in series between the power supply potential and the ground potential. Then, in parallel with the first constant current source and the transistors Ml and M2, the same constant potential (VGC) as above is applied to the second constant current source (current value IB) and the gate. A third MOS transistor M3 and a fourth MOS transistor M4 having a gate connected to the gate of the MOS transistor! ^ 2 are connected in series between a power supply potential and a ground potential to form a cascode. A mirror circuit is configured. By providing a fifth MOS transistor M5 connected in parallel with the MOS transistor M2 and having a gate to which the voltage input signal Vin is input, the cascode mirror circuit is provided for the MOS transistor M3. The current signal lout corresponding to the input signal Vin is obtained from the drain. Here, the MOS transistors M1 and M3 with the bias voltage VGC applied to the gate have the function of extending the frequency characteristics of the circuit.

 The above-mentioned cascode-mirror circuit is introduced in the third known document as an application example to a current integration circuit as shown in FIG. 16, for example. That is, in the integrating circuit of FIG. 16, the capacitor C1 is connected between the gate of the transistor M2 corresponding to the MOS transistor M2 of FIG. 2 and the ground potential, and the current I input to the drain of the MOS transistor M1 is in is integrated by the capacitor C1 to obtain a current output lout from the drain of the MOS transistor M3.

 In this conventional current integration circuit, the input current Iin is input to the drain of the MOS transistor Ml, and the change in the input current Iin causes the drain potential of the MOS transistor M1 to rise to, for example, a high value. When the voltage fluctuates, the drain voltage of M2, that is, the source potential of the MOS transistor M1 decreases, and this feed-packing action operates to reduce the change in the drain potential of the MOS transistor M1. The club dance can be made smaller. In other words, the conductance of the input section composed of the MOS transistors Ml and M2 can be increased, thereby improving the high-frequency characteristics. Here, it can be seen that the circuit can be used as a current inverting amplifier except for the integration capacitance C1 of the above circuit.

In the voltage / current conversion circuit of the embodiment of FIG. 2, the source potential of the MOS transistor Ml is maintained at a stable value with a lower impedance than the drain potential. In addition, when used as an integrating circuit as in the known example (FIG. 16), the source potential of the MOS transistor M1 is too low to be used as a current input point. Voltage / current converter is characterized by low source potential Is preferred.

 That is, in the embodiment circuit of FIG. 2, the voltage input signal Vin is input to the gate of the MOS transistor M5 connected in parallel with the MOS transistor M2, and the gate voltage signal of the M〇S transistor M5 is input. Vin requires a relatively high voltage in the range necessary and sufficient to operate the MOS transistor M5 in the unsaturated region (triode region) exhibiting linear characteristics. The lower the voltage, the lower the gate voltage signal can be. Therefore, it is optimal for achieving the object of the present invention. That is, according to the circuit form of FIG. 2, the power supply voltage of the entire voltage-Z current conversion circuit, and furthermore, the entire power supply voltage of the read channel LSI including the voltage-current conversion circuit can be reduced, thereby reducing power consumption. . By the way, the relationship between the drain current ID5, the drain voltage VD5, and the gate voltage Vin of the MOS transistor M5 operating in the unsaturated region is as follows:

-ID5 = K5 {(Vin-Vth5 ) VD5-VD5 2/2}

 = K5VD5Vin-K5VD5 (Vth5 + VD5 / 2) It is expressed by eleven (1). Here, Vth5 is the threshold voltage of transistor M5, and K5 is the transconductance constant of transistor M5. This constant K5 is given by K5 =? O · (W / L), where? 5 is the channel conductance fitting parameter of M5, the gate width is W, and the gate length is L.

 —The drain current ID2 of transistor Μ2 is

 -ID2 = IB-ID5 (2). Since this current ID2 is copied to M4 as a mirror current when M2 and M4 have the same size and have the same characteristics in the transistor area, -ID2 = ID4, and from equation (2)

-Iout = IB-ID4 = ID5 (3) Further, if Vin = VIB + vin (where VIB is a DC bias voltage and vin is an AC signal component), the corresponding current signal ID5 is given by the above equation. From (1), it can be expressed as the following equation.

 ID5B + iD5 = K5VD5 (VIB-Vth5-VD5 / 2) + K5VD5vin (4) Therefore, if the drain voltage VD5 of M5 is constant, the AC signal component iD5 of the drain current ID5 is the AC signal component vin of the gate voltage Vin. It can be seen that it is completely proportional to That is,

 -iD5 = K5VD5vin (5). Also, since the drain voltage VD5 of M5 can be arbitrarily changed by changing the gate potential VGC of M1, the gain of the voltage / current conversion circuit in Fig. 2 can be changed to a desired value by the bias voltage VGC. I can do it.

 As described above, the voltage / current conversion circuit in Fig. 2 can obtain a sufficiently linear current output even with a single-phase voltage input signal without taking the difference between the positive and negative input current signals, and can operate at high speed and high frequency Becomes

 That is, by using the cascode-mirror circuit, the first MO

The source of the S-transistor M1 has a low impedance, that is, a change in potential can be suppressed in response to a change in current, so that the gate voltage signal of the fifth MOS transistor M5 operating in the unsaturated region Can be directly and linearly converted to Vin.

 This eliminates the need for a current mirror circuit or the like for inverting and adding symmetric current signals, and since the signal path transistor is composed of only N-channel MOS transistors, it can be used in high-speed and high-frequency regions. Is easy to apply. Furthermore, since the current / voltage conversion circuit of this embodiment can be constituted only by the MOS transistor, it can be realized by an inexpensive logic-dedicated LSI process.

Although not shown in FIG. 2, means for changing the bias voltage VGC can be easily obtained. For example, it can be configured by using a digital / analog conversion circuit that changes the value of the register by an external control signal and generates a voltage corresponding to the value. Alternatively, the current IB of a plurality of constant current sources is supplied to a predetermined resistance circuit via a selection switch or the like to generate a voltage, and The configuration may be such that the VGC is changed by selecting the value of the current IB in accordance with the set value of the resistor, in addition to the voltage VGC. The gain control of the voltage / current conversion circuit can be realized by changing the bias current IB in addition to the gate voltage VGC of the MOS transistor Ml. FIG. 3 shows a specific example of a circuit configuration capable of obtaining a positive / negative symmetrical voltage / current conversion signal, that is, a differential output current, by applying the basic configuration circuit of FIG. In the basic configuration circuit of FIG. 2, as can be seen from the above equation (4), the output current lout includes a DC component ID5B, and this DC component is obtained by the following equation from equations (4) and (5). ,

 -ID5B = K5VD5 (VIB-Vth5-VD5 / 2) (6) Such a DC component becomes an input offset for the next-stage circuit (the filter circuit in the system of FIG. 1).

 Therefore, in the embodiment of FIG. 3, the bias for generating the bias voltage of the constant current transistors (MB8 to MB11, MB14 to MB17) for flowing the constant current IB of the voltage / current conversion circuit in FIG. By devising the circuit section 21, the DC component of the output current lout is eliminated.

That is, in the embodiment of FIG. 3, a pre-piase stage composed of the MOS transistors MB 1 to MB 3 connected in series between the power supply voltage terminals, and a MOS transistor similarly connected in series between the power supply terminals. A main bias stage comprising transistors MB4 to MB7, wherein the MB1 and MB4 are connected to a current mirror, and a drain voltage of MB4 is applied to an inverting input terminal, and a drain voltage of MB1 is applied to a non-inverting input terminal. The bias circuit 21 is constituted by the differential amplifier AMP B which generates the gate voltage of the MB 5 when applied. A constant current source for supplying a bias constant current IB2 is provided between the drain terminal and the ground terminal of MB1, and a constant current transistor MB2 with VGC applied to the gate and VIB applied to the gate. Due to the cascode configuration of the constant current transistor MB3, the drain potential of the MB3 becomes substantially equal to the drain potential of the input transistor M5. Thus, the DC component represented by the above equation (6) is subtracted from the output currents + Iout and -lout so as to be cancelable.

 The differential amplifier AMPB and the main bias stage (transistors MB4 to MB7) are not particularly limited, but are not limited to variations in the power supply voltage AVDD, changes in the ambient temperature, and input current signals. It is used to stabilize the current values of the constant current sources M8 to M19 of the units 22 and 23 and the offset adjustment units 24 and 25. In this embodiment, the constant current source of the voltage / current conversion circuit shown in FIG. 2 is constituted by two P-channel MS transistors connected in series to improve the constant current characteristics.

 The signal conversion unit includes a positive signal conversion unit 22 and a negative signal conversion unit 23. These signal conversion units each have a configuration corresponding to the above-described voltage / current conversion circuit in FIG. The offset adjusters 24 and 25 are used to cancel the DC component of the output current lout with higher accuracy in combination with a current offset compensating circuit shown in FIG. 4 described later. This cancellation operation will be described in detail below.

 The offset adjuster 24 is composed of four MOS transistors MB12, MB13, M6, and M7 connected in series between the power supply voltage terminals, and each of the MOS transistors constituting the signal converter 22. The same voltage as the gate voltage of the transistors MB 10, MB 11, M 3, and M 4 is applied to the gate, whereby the output current of the positive signal converter 22 from the drain of M 6 + Outputs the same current as Iout. Further, the same current as the output current -lout of the negative signal converter is output from the drain of M16. The offset adjustment unit 25 is composed of four MOS transistors MB 18, MB 19, M 16, and M 17 connected in series between the power supply voltage terminals. The same voltage as the gate voltage of the MOS transistors MB 16, MB 17, M 13, and M 14 constituting the MOS transistor 3 is applied to the gate. Outputs the same current as the output current-lout of the negative signal converter 23.

Both of these outputs are set to the monitor current of the DC offset, + Iofs, and -Iofs. Each is supplied to the current offset compensation circuit of FIG. The offset adjustment signal from the current offset compensation circuit + V〇F, one V0F is provided between the terminal from which each of the output currents + lout, -lout, + Iofs, and -Iofs is output and the ground terminal. O The MOS offset transistors Ml8 to M21 whose gates are controlled by the current o are connected.o The current offset compensation circuit shown in Fig. 4 is a first cascode mirror composed of M0S transistors MC1 to MC7. One circuit 31; a second cascode mirror circuit 32 composed of MCs 8 to 14; a bias circuit 33 composed of a MOS transistor MC 15 and a constant current source IC; And a differential amplifier 34 composed of transistors MC16 to MC20. The differential amplifier 34 is current-mirror-connected to the MOS transistor MC 15 of the bias circuit 33, and is supplied with the same bias current as the current flowing to the constant current source IC by the current mirror IC. It is composed of common source-coupled MOS transistors MC 17 and MC 18 and current mirror-coupled MOS transistors MC 19 and MC 20.

 In the first cascode-mirror circuit 31, the element MC 21 connected between the drain of the transistor MC 3 and the ground potential is a capacitance element using the gate capacitance of the MOS transistor, and is connected to the monitor current. Functions as an element that removes AC signal components included in + Iofs or -Iofs. Also, the first and second cascode mirror circuits 31 and 32 are different from the above-described current integration circuit of FIG. 16 in that the drain voltages VC 5 and VC 12 of MC 5 and MC 12 are different. The output is output to the gate of each of the input MOS transistors MC 17 and MC 18 constituting the differential amplifier 34.

In the circuit of FIG. 3, if the DC offset current is included in the positive and negative output currents + lout and -lout, the outputs + Iofs and -Iofs of the offset adjustment units 24 and 25 become the output currents + Iout and -Iouts. It is the value of the DC offset current included in lout. The first cascode mirror circuit 31 in FIG. 4 has the offset current + Iofs or less. Or −Iofs is input, while the second cascode mirror circuit 32 has no input, that is, the input current is 0, so the input MOS transistors of the differential amplifier 34 are connected to the MS 17 and MS 18. A potential difference occurs between the gates.

 Now, assuming that the offset current + Iofs is positive, the drain voltage of MC5 and MC12 is VC5 <VC12, and the drain potential + V0F of MC19 which is the output of the differential amplifier 34 is MC5. It is higher than the drain potential of 20. This output potential + V0F is fed back to the gates of the MOS transistors M18 and M20 for offset adjustment in the circuit of FIG. 3, and is output from each output current + lout and + Iofs according to the potential of the output potential + VOF. The operation is performed so that the input potential of the differential amplifier 34 becomes equal, that is, VC 5 = VC 12 by drawing the current. When the offset current + Iofs is negative, the differential operation is performed by applying a current corresponding to the output potential + V0F to each output current + Iout and + Iofs by the feed pack, conversely to the above. It operates so that the input potential of the amplifier 34 becomes equal. The same applies to the output currents -lout and -Iofs.

 Fig. 5 shows the simulation results of confirming the input voltage Vin and the output current lout when changing the gain by changing the gate voltage VGC of the voltage / current conversion circuit in Fig. 3. In Fig. 5, the solid line A shows the input / output characteristics when the gain is 72 〃S (microdimens), the broken line B shows the input / output characteristics when the gain is 59 S, and the dotted line C shows the input / output characteristics when the gain is 42 zS. Output characteristics, dashed line D is the input / output characteristics when the gain is 27.5, and dashed line E is the input / output characteristics when the gain is 7.4 zS. From the figure, it can be seen that the voltage / current conversion circuit of the embodiment can obtain good conversion characteristics (linearity) over a gain range of 0 to 45 S or more.

Note that the gain control of the voltage / current conversion circuit can be realized by changing the bias current IB2 in addition to the gate voltage VGC. In other words, in the circuit of FIG. 3, the bias currents (corresponding to the constant current IB of FIG. 2) of the signal converters 22 and 23 are given by the M0S transistors MB8, MB10, MB14 and MB16. Transistor is a Piase circuit 21 MOS transistor MB The current flowing through MB1 is the sum of the drain current of the MOS transistor MB2 connected in series with this and the bias current IB2, so that the gate voltage VGC of MB2 is By changing the bias current IB2 without changing it, the current of MB1, that is, the bias current of the signal converters 22, 23 can be changed. As a result, the gain of the voltage / current conversion circuit can be changed. Next, the filter circuit FIL constituting the read channel of FIG. 1 will be described.

 FIG. 17 shows a known complete current integration circuit introduced in the third document. This complete current integrator has two imperfect current integrators as shown in Fig. 16 and integrates them using the positive and negative symmetrical current input signals +1 in and -I in with the capacity CI of each integrator. The first mirror current outputs + If and -If are fed-packed to the opposite input nodes, respectively. As a result, the second mirror current outputs +1 out and -lout of each integration circuit are completely integrated with respect to the input current.

 That is, the sizes of the MOS transistors M1, M3, and M5, M2, M4, and M6 are made equal to each other, and the constant current bias values IB supplied through the transistors M1, M3, and M5 are made equal. When equal, the channel conductances gm of the MOS transistors M2, M4 and M6 are equal. Therefore, the current gains of the feedback current I and the output current Iout with respect to the input current Iin are equal, and

 I out / 丄 in =-g m / s C = — / s (7) Here, a = gm / C is the integration time constant, and s is the complex angular frequency represented by.

In the above equation (7), the input / output gain is inversely proportional to s, that is, inversely proportional to the signal frequency, which indicates that the circuit in FIG. 17 is a complete current integration circuit. In general, the channel conductance gm of the MOS transistor is Since it is proportional to the square root of the value of the bias current IB, the integration time constant can be varied by changing the bias current IB, and a filter circuit with a variable cut-off frequency is realized.

 The filter circuit required for hard disk drive devices needs to vary the cut-off frequency in accordance with the data read rate from the disk. It is required that the phase delay, that is, the group delay characteristic of each frequency component to be applied is flat to a frequency close to twice the cutoff frequency. As a filter circuit suitable for realizing such characteristics, generally, a transfer function of the fifth or higher order of the equi-ripple characteristic is used.

 The high-order fill circuit can be realized by connecting the secondary fill and the primary fill in multiple stages. FIG. 18 shows a block configuration of a secondary filter used to realize a high-order mouth-to-pass filter using the complete current integration circuit of FIG. Here, if each coefficient is a positive value, the transfer function is expressed as follows.

Similarly, the transfer function of the first-order filter shown in Fig. 19 is as follows.

_{H (s) =} -Α α _ (9)

 s + (Αα) The coefficients Α and Β in FIGS. 18 and 19 are determined by appropriately setting the size ratio of the MOS transistors in the incomplete current integration circuit (that is, the current mirror ratio). Thus, a desired coefficient can be realized.

As described above, the case where a higher-order filter is configured using the complete integration circuit of the related art has been described. However, the related art has the following problems. That is, a mirror current output stage for the feed pack is required in the integration circuit. Also complete Since the integrator has an infinite gain in principle when the angular frequency s is 0, that is, for a DC input, it cannot be used alone. Therefore, the figure

As shown in 19 and Eq. (9), it is necessary to construct a feed-pack loop by installing a coefficient circuit to realize the first-order filter. As a result, the circuit scale and current consumption increase. However, an increase in the circuit size causes deterioration of the operating frequency band.

 On the other hand, the input / output current gain of the integration circuit shown in FIG. 16 is expressed by the following equation (10), indicating that it is an incomplete current integration circuit.

 I out / I in =-gm / (s C + gm)

 =-/ (s + a) (10) This imperfect current integration circuit has a finite gain with respect to DC current input, like a resistor-capacitance circuit of a passive element. Can be used as The second-order filter and the first-order filter using this imperfect current integration circuit have block configurations as shown in Figs. 6 and 7, respectively, and the transfer function of the second-order filter is expressed as follows: .

H (C

 Eleven (

s ² + (A, + 2) as + (Α ′ Β, +1) α ² where h = gm / C.

 Where A, = A—2,

 B '= A-B- 1 (1 2)

 If the coefficient is used, equation (11) becomes the same as equation (8), and it can be seen that the same characteristics can be realized.

The first-order filter can be composed of an incomplete integrator alone, and no coefficient circuit is required. No return path is required. And its transfer function is as follows, as in equation (10). H (s): (1 3)

 a As explained above, using an incomplete current integration circuit that was not used in the past because it was generally difficult to design, a primary filter can be realized by the incomplete current integration circuit alone, and No feedback path is required in the circuit. Also, as is clear from the above equation (12), the second-order filter using the incomplete current integration circuit has a coefficient whose coefficient is the same as that of the complete integration circuit described above (Figs. 18 and 19). It can generally be smaller than the coefficient.

 Therefore, in the read channel LSI of the present embodiment, an incomplete current integration circuit shown in FIG. 16 is used as the filter circuit FIL. This makes it possible to greatly reduce the number of transistors and power consumption as compared with the case where a filter is formed using a complete integration circuit as in the conventional technique (FIG. 17).

 Note that the incomplete current integration circuit shown in FIG. 16 simultaneously varies the current values of the two constant current sources IB according to the information set in the register selected by the control device. It is also possible to configure so as to control the power cutoff frequency of the output current l out by changing the channel conductance of the MOS transistor M2 in the input stage. Figure 8 shows the block configuration of a 7th-order equiripple low-pass filter designed by combining the primary and secondary filters (Figures 6 and 7) using the above-mentioned CMOS imperfect current integration circuit. It is used as the fill circuit FIL of the read channel LSI shown in Fig. 1.

In Fig. 8, the one with the transfer function described in the block is the incomplete current integration circuit, and the one with "-1" in the block is the inverted current amplifier. The inverting current amplifier is similar in basic configuration to the circuit shown in Figure 16 and is obtained by simply removing the integration capacity CI. Note that in FIG. The numerical value added to each output terminal of the incomplete integrator and the inverting current amplifier indicates the mirror current gain.

 In this embodiment, the total number of bias current sources in the entire low-pass filter is 30.32 times that when the input bias of each integration circuit and the inverting current amplifier is set to the unit bias current value. When the frequency is set to 127 MHz, the unit bias current value is 0.2 mA.

 By the way, since a read channel LSI generally incorporates a high-speed digital signal processing section of not a few scales, the analog circuit section is positive-negative and symmetrical in order to avoid interference of digital noise. Is desirably provided. Therefore, in the filter circuit F IL of the present embodiment, it is preferable to provide the incomplete integration circuit shown in FIG. 16 corresponding to the positive current input and the negative current input from the voltage / current conversion circuit V GA in the preceding stage. In this case, the maximum current consumption of the entire filter circuit when the effects of semiconductor process variations and ambient temperature fluctuations are ignored is 12.1 mA for both the positive and negative sides. This is about 70% or less of the current consumption of the filter circuit designed separately using the conventional complete integration circuit in Fig. 17.

Fig. 9 shows the frequency characteristics of the group delay (phase) and current gain obtained as a result of simulation by a computer for the above-mentioned 7th-order equal ripple port one-pass fill. According to FIG. 9, the group delay ripple is 4 ± 0.1 nS up to a frequency 1.7 times or more of the cut-off frequency fc (127 MHz), and the fluctuation is suppressed to 3% or less. In other words, it can be seen that the phase hardly shifts even if the signal passes through this filter or exceeds the cutoff frequency. As a result, in the hard disk drive, the phase difference between the phase of the signal passed through this filter and the sampling clock 0 s of the subsequent A / D converter ADC is reduced, and the characteristic point of the read signal waveform is reduced. Sampling can be performed with good timing. Next, the A / D conversion circuit constituting the read channel of FIG. 1 will be described. FIG. 10 shows a 6-bit A / D conversion circuit constituting a read channel according to the present invention. Shows current track / hold circuit (sample / hold circuit).

 The reference constant current source IB and the N-MOS transistors Ml and M 2 are connected in series between the power supply potential AV DD and the ground potential AGND, and the drain of the MOS transistor M 1 serves as an input node of the input current signal I in. ing. The change in the drain potential of the MOS transistor M1 is performed via the source follower including the N-MOS transistor M5 and the constant current source Is connected between the source and the ground potential. It is configured to be transmitted to the gate electrode of the S transistor M2.

 Similarly to the reference constant current source 上 記 and the MOS transistors M1 and M2, the constant current sources IRi (i = l to 63) connected in series between the power supply potential AVDD and the ground potential AGND and the N-MO A current mirror circuit composed of S transistors M3 i and M4 i is provided. The output current Ici is taken out from the drain side of the MOS transistor M3i, and supplied to each of the 63 current comparison circuits (not shown) at the subsequent stage.

 The same gate voltage of the MOS transistor M1 is applied to the gates of the MOS transistors M301 to M363, and the gate potential of the MOS transistor M2 is N− It is configured to be transmitted to the gate electrodes of 63 N-MOS transistors M401 to M463 provided in parallel during the ON period of the CMOS transmission switch composed of the MOS transistor M6 and the P-MOS transistor M7. I have. Therefore, if the sizes of M301 to M363 and M2 and M401 to M463 provided in parallel with the above MOS transistor M1 are made equal to each other, the current flowing in M2 will be less than that of M401 to M463. It is.

On the other hand, during the off period of the CMOS transmission switches M 6 and M 7, the potential at the time of turning off the parasitic capacitance between each gate and the source electrode and between the gate and the drain electrode of each of the MOS transistors M 401 to M 463. (Gate capacitance) Cs is held, and a drain current according to the held potential flows through M401 to M463. In addition, between each drain of the MOS transistors M301 to M363 and the power supply potential. The respective current values of the connected constant current sources IR1 to IR63 are set to reference current values with respect to the amplitude of the input current signal Iin. For example, if the configuration of the A / D conversion circuit is 6 bits and −18 = 80/8, −Iin = + 32 zA to 1〃32 A, IR1 to IR63 are set as follows.

 -IR1 = 8 0-3 1.5 = 48.5 ju A,

 -IR2 = 80-30.5 = 49.5 μ, Α,

-IR32 = 80-0.5 = 79.5 A,

 -IR33 = 80 + 0.5 = 8 0.5 A,

-IR62 = 80 + 30.5 = 1 10.5 A,

 -IR63 = 80 + 31.5 = 1 11.5 A.

 When the current values of the constant current sources IR1 to IR63 are set as described above, the output currents Icl to Ic63 when the input current signal Iin changes from + 32 / A to -32 A, It changes to the value in the following range. Here, “+” represents each of the source currents to the subsequent 63 parallel current comparison circuits not shown in FIG. 10, and “one” represents the sink current from the current comparison circuits.

 -Icl =-63. ~ 10 0.5 JLA

 -I c2 =-62.5 / A to 10 1.5 uA

-Ic32 = — 32.5 A to 101.5 μ, Α

 -I c33 =-31.5 / A ~ 10 32.5 μ, Α

I c62 =-1. to 102.5 / LC A -Ic63 = —0.5 / A to 10 63.5 ^ A

 Therefore, if each of the currents Ic1 to Ic63 is compared with the reference current value “0” by the parallel 63 current comparison circuits at the subsequent stage, a digital output of the conversion result with respect to the input current value Iin is obtained. be able to.

 Although not particularly limited, when the input current from the preceding filter circuit is a positive-negative differential input current, the track-hold circuit shown in FIG. Provided for each of 1 in and the negative input current signal -I in. In that case, the output current Icl for the positive input current signal +1 in is supplied. The first current comparison circuit is supplied with the output current Ic63 for the negative input current signal -Iin, and the magnitudes thereof are compared. It is configured to Similarly, the second current comparison circuit determines the magnitude of the current corresponding to Ic2 on the positive signal input side and Ic62 on the negative signal input side, and the third current comparison circuit determines the magnitude of the current corresponding to Ic32 on the positive signal input side. It is configured to compare the magnitude of the current corresponding to Ic33 on the signal input side.

 In the above description, the difference outputs Icl to Ic63 between the input current signal Iin and the reference currents IR1 to IR63 are set so as to change to the positive and negative sides with respect to the analog ground AGND, respectively. However, according to the configuration of the current comparison circuit provided at the subsequent stage, the above reference current values may be changed so as to conform to the configuration, so that the output signal is always positive or always negative.

 Further, as specific examples of the above current comparison circuit, for example, the inventors of the present invention have proposed the following: Any known current comparison circuit, such as the circuit proposed in ISSCC 99, Digest of Technical Papers, February 1999, WA 18.5, can be used. . Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and it is needless to say that various modifications can be made without departing from the gist of the invention. Nor.

For example, in the above description, in FIGS. 2 to 4 and FIG. Although the cascode's mirror circuit is composed of N-channel MOS transistors, it can be realized by switching the conductivity type of the MOS transistor depending on the target specification. Also, in the embodiment of the fill-in screen shown in Fig. 8, the primary fill-in connection is connected after the secondary fill-in step 3, but each fill-in screen can be arranged in any order. In other words, the first fill evening may be arranged before the second fill evening or before the second fill evening.

 Further, in the above embodiment, the case where the present invention is applied to the read channel of the hard disk device has been described. However, not only such a signal processing system but also a voltage signal in which the amplitude value of the received signal changes greatly with time. A series of functions for amplifying, filtering, A / D converting, and digital signal processing the signal are used in addition to the hard disk drive, for example, transmitting and receiving information as a voltage signal via a signal transmission path. The same effect can be obtained even if the present invention is applied to an electronic device such as a communication device as shown in FIG. In FIG. 11, 100 is a voltage signal transmission source, 200 is a signal transmission path through which the voltage signal is transmitted, and V / I is a voltage / current converter that amplifies the voltage signal and converts it to a current signal. Circuit. Industrial applicability

 INDUSTRIAL APPLICABILITY The present invention can be widely used not only in a signal processing system such as a read channel of a hard disk drive but also in a signal processing system in a communication system for processing received serial data.

Claims

The scope of the claims

1. A read amplifier that reads data recorded on a magnetic disk via a read head and converts the output to an electric signal, a variable gain amplifier circuit that amplifies an output signal of the read amplifier, A filter circuit for suppressing unnecessary frequency components included, an analog / digital converter circuit for converting the amplitude of the filter output signal into a corresponding digital signal, and processing the digital signal. A hard disk drive device including a readout signal collation and a digital signal processing circuit for performing signal processing necessary for the collation; an output of the read amplifier is a voltage signal; Has voltage / current conversion means for converting the voltage signal into a current signal proportional to the voltage signal. The filter circuit receives the current signal as an input and outputs the current signal. A hard disk drive device characterized in that the analog / digital conversion circuit is provided with means for tracking and holding the current from the filter circuit at its input.

2. The filter circuit is a filter having equal-phase ripple characteristics, and the current integration circuit constituting the filter is an incomplete integration circuit whose output is limited to a constant value with respect to a DC signal input. 2. The hard disk drive device according to claim 1, wherein:

3. The hard disk drive device according to claim 1 or 2, wherein a frequency characteristic of the filter circuit is configured to be variable according to information set in a register selected by the control device. A hard disk drive device.

4. The voltage / current conversion means provided in the variable gain amplifier circuit,

A first constant current source and a first insulated gate type power supply having a fixed potential applied to the gate. A field effect transistor and a second insulated gate field effect transistor having a gate connected to the drain of the first insulated gate field effect transistor are connected in series between a power supply potential and a ground potential. And

 In parallel with this, a second constant current source, a third insulated gate field effect transistor having the same fixed potential applied to the gate as above, and a gate connected to the second insulated gate field effect transistor A fourth insulated gate field effect transistor connected to the gate, which is connected in series between the power supply potential and the ground potential;

 A fifth insulated gate field effect transistor is connected in parallel with the second insulated gate field effect transistor of the cascade mirror circuit, and the fifth insulated gate field effect transistor is connected to the fifth insulated gate field effect transistor. A voltage signal applied to the gate is input, and an output current signal corresponding to the input signal is obtained from the drain of the third insulated gate field effect transistor. A variable gain amplifier circuit, wherein the conversion gain of the input voltage and the output current is varied by being varied in accordance with information set in a selected register. The hard disk drive device according to 1, 2 or 3.

5. The filter circuit is

 A first constant current source, a first insulated gate field effect transistor having a fixed potential applied to the gate, and a first insulated gate field effect transistor having a gate connected to a drain of the first insulated gate field effect transistor. A current input stage comprising two insulated gate field effect transistors connected in series between a power supply potential and a ground potential;

In parallel with this, a second constant current source, a third insulated gate field effect transistor having the same fixed potential applied to the gate, and a gate of the second insulated gate field effect transistor A current output stage having a fourth insulated gate field effect transistor connected to the power supply potential and the ground potential connected in series with each other; A capacitive element connected between the gate of the second insulated gate field effect transistor and a ground potential;

A current signal supplied to the drain of the first insulated gate field effect transistor as an input signal; and an output current corresponding to the input current from the drain of the third insulated gate field effect transistor. A current value of the first and second constant current sources is simultaneously varied in accordance with information set in a register selected by the control device. A hard disk drive device comprising an imperfect integration circuit configured to change a channel conductance of a second insulated gate field effect transistor to control a power cutoff frequency of an output current.

6. The incomplete integration circuit includes a second current output stage having the same configuration as the current output stage in parallel with the current output stage, and the current input stage, the first current output stage, and the second current output stage. The current value of each constant current source of the current output stage 2 is simultaneously varied according to the information set in the register selected by the control device, so that the second insulated gate electric field of the input stage is The device according to claim 5, wherein the channel conductance of the effect transistor is changed so that the power cutoff frequency of the output current of the first and second current output stages is simultaneously controlled. Hard disk drive device.

7. The filter circuit having equal phase ripple characteristics according to claim 2 is

 A first, second, and third secondary filter comprising a first incomplete current integration circuit according to claim 5, an inversion current amplifier, and a second incomplete current integration circuit according to claim 6. And a primary filter comprising a first incomplete current integration circuit according to claim 5 is connected in cascade,

Of these, the first output of the second incomplete integration circuit of the first and second secondary filters is connected to the input of the second and third secondary filters at the subsequent stages, and The second output of the second incomplete integrator is the first The first output of the second incomplete integrator of the third secondary filter is connected to the input of the total integrator, and the first output of the second incomplete integrator is connected to the input of the subsequent primary filter. The second output of the circuit and the second output of the current inverting amplifier are connected to the input of the first imperfect integration circuit of the third secondary filter, and the output of the primary filter is output to the filter output. It is the 7th Phil evening

A hard disk drive device characterized by the above-mentioned.

8. The analog / digital conversion circuit

 A first constant current source connected in series between the power supply potential and the ground potential; a first N-channel insulation type having a fixed potential supplied to the gate; a gate field-effect transistor and a second N-channel insulation. The gate type field effect transistor and the gate are connected to the drain of the first N-channel insulated gate field effect transistor, and the source is connected to the gate of the second N-channel insulated gate field effect transistor. A current input section comprising a third N-channel insulated gate field effect transistor, and a second constant current source connected between the source of the transistor and a ground potential;

 A constant current source connected in series between a power supply potential and a ground potential to supply a reference current, a fourth N-channel insulated gate field effect transistor having a gate supplied with the fixed potential, A plurality of current output sections each comprising an N-channel insulated gate field-effect transistor, and a gate of the second N-channel insulated gate field-effect transistor of the current input section. The gates of each of the fifth N-channel insulated gate field effect transistors of the plurality of current output units are connected via a transmission switch,

 The reference current is set to a value corresponding to the desired conversion accuracy of the input current, and the reference current is calculated from the sum of the value of the first constant current source and the input signal from the plurality of current output units. A track-and-hold circuit configured to output a current obtained by subtracting the value of the reference current,

The output current of the above track-hold circuit is input and the voltage signal is output. A current comparison circuit;

2. The hard disk drive device according to claim 1, further comprising:

9. A voltage / current conversion circuit that receives a voltage signal and outputs a current proportional to the voltage signal, and a filter that performs a filtering process on an output current signal from the voltage / current conversion circuit and outputs a current signal And an electronic circuit including a digital signal processing circuit for receiving the current signal from the filter circuit and executing predetermined signal processing.

10. The electronic device according to claim 9, further comprising a circuit that outputs information as a voltage signal.

1 1. The circuit for outputting the voltage signal includes a read amplifier for outputting information read from a magnetic disk, and the digital signal processing circuit includes an analog / digital conversion circuit that operates according to a current signal from the filter circuit. The electronic device according to claim 10, comprising: