WO2000048390A1 - Controle de la modulation de la vitesse de balayage avec plusieurs frequences de balayage - Google Patents

Controle de la modulation de la vitesse de balayage avec plusieurs frequences de balayage Download PDF

Info

Publication number
WO2000048390A1
WO2000048390A1 PCT/US2000/002989 US0002989W WO0048390A1 WO 2000048390 A1 WO2000048390 A1 WO 2000048390A1 US 0002989 W US0002989 W US 0002989W WO 0048390 A1 WO0048390 A1 WO 0048390A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
amplitude
horizontal scanning
velocity modulation
frequency
Prior art date
Application number
PCT/US2000/002989
Other languages
English (en)
Inventor
Jeffrey Owen Allender
Gene Karl Sendelweck
Original Assignee
Thomson Licensing S.A.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson Licensing S.A. filed Critical Thomson Licensing S.A.
Priority to JP2000599203A priority Critical patent/JP2002537692A/ja
Priority to DE60001261T priority patent/DE60001261T2/de
Priority to AU34834/00A priority patent/AU3483400A/en
Priority to EP00913372A priority patent/EP1151602B1/fr
Publication of WO2000048390A1 publication Critical patent/WO2000048390A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
    • H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
    • H04N3/30—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical otherwise than with constant velocity or otherwise than in pattern formed by unidirectional, straight, substantially horizontal or vertical lines
    • H04N3/32—Velocity varied in dependence upon picture information
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
    • H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
    • H04N3/16—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by deflecting electron beam in cathode-ray tube, e.g. scanning corrections
    • H04N3/27—Circuits special to multi-standard receivers

Definitions

  • This invention relates to scanning velocity modulation (SVM)
  • This derivative signal, or scan velocity modulation l i signal can be derived from the luminance portion of the video signal and
  • This method of picture sharpness enhancement has 0 advantages over a peaking approach to picture sharpness enhancement such as 1 an avoidance of blooming of peaked high luminance (white) picture elements and 2 an avoidance of enhancement of video noise occurring within the bandwidth of
  • SVM systems are generally not well suited for use in monitors that display video
  • 29 formats can be anywhere from 2 to 2.4 times as great as an NTSC horizontal
  • multimedia monitors are becoming available that are also capable of handling computer formats. This presents significant problems as concerns use of SVM. Not only are computer monitor horizontal scan rates greater than conventional NTSC scan rates, but new high definition television scan rates defined by the Advanced Television System Committee (ATSC) standards can also be as much as 2.1 4 times greater than NTSC television scan rates. Thus, for example, if the NTSC television systems are referred to as having a scan frequency of 1 H, then VGA, HDTV and SVGA systems can be said to have scan frequencies of 2H, 2.1 4H and 2.4H, respectively.
  • ATSC Advanced Television System Committee
  • SVM SVM
  • the SVM signal generated from the derivative of a luminance component of a 2H scanning frequency signal will generally be 6 dB greater than the SVM signal which is generated for an NTSC ( 1 H) signal.
  • This amplitude range can result in an SVM signal that is less than optimal.
  • the application of scan velocity modulation to any video signal is optimized having a predetermined range of amplitudes for signal processing at the particular scan rate at which the display is to be used.
  • scanning velocity modulation signal amplitude is controlled at a plurality of horizontal scanning frequencies.
  • the method comprises the steps of, generating respective scanning velocity modulation signals from signals having a plurality of horizontal scanning frequencies and coupled for display by said apparatus, and, selectively controlling an amplitude of each respective scanning velocity modulation signal to a predetermined range of amplitudes.
  • the amount of gain applied to the scan velocity modulation signal is reduced as the frequency of the horizontal scanning frequency is increased.
  • the horizontal scanning frequency is determined by a scan frequency detector circuit.
  • the control signal is a DC voltage generated by said scan frequency detector which varies proportionally as a function of the horizontal scanning frequency. This DC voltage can then be used to directly control an amplifier gain.
  • the control signal can be a digital command signal generated by a microprocessor responsive to horizontal scan frequency selection data. In that case, the digital command signal is preferably used to selectively vary an SVM gain register for controlling the amplitude of the SVM signal.
  • the SVM amplitude control signal can be a digital command signal generated by a microprocessor responsive display source selection data.
  • the digital command signal is preferably used to selectively vary an SVM gain register for controlling the SVM signal amplitude.
  • FIGURE 1 is a graph of SVM signal amplitude versus scanning frequency.
  • FIGURE 2 is a block diagram of an inventive SVM automatic gain control system for controlling an SVM signal amplitude.
  • FIGURE 3 is a detailed circuit diagram showing an embodiment of an SVM circuit with an automatic gain control system according to FIGURE 2.
  • FIGURE 4 is a block diagram of an alternative inventive embodiment employing an SVM automatic gain control system according to FIGURE 2..
  • FIGURE 5(a) shows an SVM signal output from a differentiator for a 1 H video signal.
  • FIGURE 5(b) shows the signal of FIGURE 5(a) after amplitude control.
  • FIGURE 5(c) shows an SVM signal output from a differentiator for a 2H video signal.
  • FIGURE 5(d) shows the signal of FIGURE 5(c) after amplitude control.
  • DETAILED DESCRIPTION Figure 1 is a plot showing SVM signal amplitude versus scan frequency in a display operable at multiple scanning frequencies.
  • the y-axis represents the SVM signal amplitude, for example in decibels, when generated by a conventional SVM differentiator circuit.
  • the x-axis represents horizontal scanning frequency of an input video signal.
  • the standard NTSC horizontal frequency is denoted by 1 H, hence, 2H denotes a scanning frequency which is one octave higher, for example, as used for 640x480 video format.
  • FIGURE 1 illustrates that the SVM signal amplitude increases by about 6dB for video signals having horizontal scanning frequencies in the 2H or greater frequency band.
  • an SVM circuit designed for specific performance parameters such as peak to peak clipping and noise coring with in a predetermined range of SVM signal amplitudes with 1 H signals, can be over driven when processing SVM signals derived from video signals in the 2H frequency band.
  • Overdriving an SVM system can for example result in, SVM output drive signal clipping, the output driver amplifier operating in a power limitation condition, with in addition, continuous peak to peak clipper activation and attendant loss of image sharpness enhancement.
  • the SVM circuitry is designed for optimal performance with a range of SVM signal amplitudes derived from 2H video signals, but receives a 1 H signal, the SVM signal amplitude will be too small, possibly even failing to overcome the signal range for noise coring, and certainly resulting in insufficient picture enhancement.
  • FIGURE 2 depicts in block diagram form an SVM automatic gain control system for adjusting SVM signal amplitude to be with in a predetermined amplitude range when operating with video formats having different spatial resolution and different scanning frequencies.
  • a video signal which includes horizontal frequency information is applied to derivative circuit 1 .
  • the luminance component of the video signal is differentiated to produce an SVM signal.
  • the output of derivative circuit 1 is coupled to variable gain amplifier 2.
  • the SVM signal is amplified and is used generate a deflection current in the SVM coil for modulating the beam scanning velocity.
  • scanning frequency detector 3 makes use of a portion of the input signal containing horizontal scanning frequency information to provide an indicator of likely spatial frequency content of the input signal.
  • FIGURE 1 shows the increase in SVM signal amplitude that occurs with a doubling of input frequency.
  • an SVM amplitude control system based on horizontal sync frequency determination provides a reliable indication of the spectral content of the displayed image.
  • the horizontal scanning frequency is monitored and when it increases above 1 H, a control signal from scan frequency detector 3 causes the SVM signal from amplifier 2 to be reduced in amplitude.
  • SVM signal gain and or amplitude control can be applied generally in accordance with a complementary or inverse transfer function to that depicted in FIGURE 1 .
  • gain, or SVM amplitude is preferably halved for signals having double frequency scanning rates.
  • FIGURE 3 is a detailed circuit diagram showing an embodiment of the SVM automatic gain control system of FIGURE 2.
  • a luminance signal with negative going horizontal sync is applied to the input of the circuit. This signal can be provided by horizontal sync, luminance (Y) with sync.
  • the input video signal passes through AC coupling capacitor C1 which is coupled to the base electrode of transistor Q2, an emitter follower.
  • Resistors R1 0, R1 1 and R1 2 form a potential divider and set the base voltages of transistors Q2 and Q4.
  • the collector electrode of transistor Q2 is coupled to a source of operating potential, + VA, typically 24 volts, and its emitter is coupled through resistor R1 3 to the emitter electrode of grounded base amplifier Q4.
  • the base electrode of transistor Q4 is biased from the junction of resistors R 1 1 and R1 2 and is decoupled ground via capacitor C2.
  • the input video signal is differentiated in the collector circuit of transistor Q4 by the parallel configured network comprising capacitor C5, inductor L2 and damping resistor R1 9 thus producing an SVM signal.
  • the output of the differentiator circuit is coupled via series connected capacitor C3 and resistor R20 to the base of transistor Q6.
  • a resistor R21 is coupled to the junction of capacitor C3 and resistor R20 to bias the base of transistor Q6 to the same potential as that of transistor Q8.
  • Transistors Q6 and Q8 form a differential amplifier in which the gain is set by resistors R26 and R28,R36 and the collector current of current source transistor Q7.
  • Resistors R25, R33 and R34 form a potential divider that provides biasing voltages for transistors Q6, Q7, and Q8, where transistor Q6 is biased via resistors R20 and R21 and transistor Q8 is biased via resistor R30.
  • the junction of resistors R21 , R30, R33 and R34 is decoupled to ground by capacitor C1 4.
  • capacitor C 1 1 decouples the junction of resistors R25 and R33 to ground.
  • the collector electrode of Q6 is coupled to supply voltage + VA
  • the collector electrode of transistor Q8 is coupled to supply voltage +VA through collector load resistor R36.
  • the SVM signal output of the differential amplifier is taken from the collector electrode of transistor Q8.
  • the video signal with negative going horizontal frequency information is applied via capacitor C6 to the base electrode of PNP transistor Q3 which is biased by resistor R1 4 which is connected to ground.
  • Transistor Q3 is configured as a negative going pulse detector which outputs at its collector, a positive going horizontal rate pulse signal derived from the horizontal sync frequency of the incoming video signal.
  • the emitter of transistor Q3 is coupled to operating potential + VA.
  • Series connected resistors R1 6 and R1 7 form a collector load for transistor Q3.
  • the positive pulses from the collector are coupled via resistor R1 7, which determines a charging current for capacitor C8.
  • capacitor C8 is discharged to ground via resistor R1 6 thus forming a horizontal rate sawtooth signal.
  • the sawtooth waveform is then applied to the base electrode of transistor Q5, an emitter follower, that buffers the sawtooth signal.
  • the collector electrode of transistor Q5 is coupled to supply voltage + VA, and the emitter electrode is coupled through resistor R1 5 to ground.
  • the emitter of transistor Q5 is also coupled to resistor R1 8 and capacitor C7 which form a low pass filter that converts the sawtooth signal into a DC voltage having a value in proportion to the horizontal sync frequency of the input video signal, i.e. the higher the horizontal frequency the greater the resultant DC voltage.
  • This frequency dependent DC voltage is coupled to the base of emitter follower transistor Q1 0 which provides a current I via resistor R1 9 to the junction of resistor R27 and the emitter of the differential amplifier current source transistor Q7.
  • the collector electrode of transistor Q7 is coupled to the junction of resistors R26 and R28, and the emitter electrode is coupled to ground via resistor R27.
  • the differential amplifier comprised of the transistors Q6, Q7 and Q8 is configured as a variable gain amplifier in which the output signal amplitude is automatically reduced when horizontal scanning frequency of the display signal is increased. It may be readily appreciated that the embodiment of the invention in FIGURE 2 is not limited to the precise arrangement shown and that there are other alternatives for implementing the control system according to the present invention.
  • FIGURE 4 depicts one such alternative embodiment.
  • input stage 1 0 is shown with a plurality of user selectable video input sources including several 1 H video sources such as NTSC composite video (VID 1 , 2, 3, 4), S-video (SVID 1 , 2, 3) and component video (Y Pr Pb) .
  • input stage 10 typically has one or more input connections providing user selectable 2H and higher scanning frequency video sources including VGA 1 , VGA 2 and HDTV. It should be noted that the invention is not limited in this regard.
  • video sources may also be provided and not all of the video sources identified need be supplied.
  • the horizontal (H) sync pulses and vertical (V) sync pulses are extracted by a video processor, depicted by exemplary integrated circuit 1 1 , from the composite video or luminance signal components of the selected 1 H source.
  • Video processor 1 1 then outputs the H and V sync pulses separated from the 1 H sources to H & V selector switch 1 2 for selection and coupling to microprocessor 1 3.
  • the processing features of video processor 1 1 can be provided by an integrated circuit, for example type TA1 276N which is commercially available from Toshiba.
  • An up-converter 1 6 can be provided between input stage 1 0 and video processor 1 1 . Up-converter 1 6 is used to convert NTSC or other 1 H video signals to 2H video signals and can, for example, be implemented by line doubling. As shown in FIGURE 4, up-converter 1 6 is controlled by microprocessor 1 3 via a data bus, for example, employing an l 2 C protocol, based on a determination of the selected input horizontal frequency by microprocessor 1 3.
  • the 2H or higher input signals may provide separate horizontal and vertical sync pulses, which when selected, via the data bus, are directly coupled to H & V selector switch 1 2 and ultimately to microprocessor 1 3 for further processing.
  • video processor 1 1 will preferably receive the component video signals (R, G, B) as shown, with selection within processor 1 1 controlled by microprocessor 1 3 via the l 2 C bus.
  • microprocessor 1 3 is variously coupled to provide control via the l 2 C bus.
  • Microprocessor 1 3 can for example be an ST 9296 IC which is commercially available from ST Microelectronics.
  • microprocessor 1 3 receives selected H and V sync pulses from H & V selector switch 1 2 to determine the horizontal frequency of the video source selected for display and SVM enhancement.
  • Microprocessor 1 3 can determine the horizontal frequency of the selected display signal by a number of methods. For example, as described with reference to FIGURE 2, a frequency dependent voltage may be generated, with the resulting DC value measured by microprocessor 1 3 and compared with stored values to determine the horizontal frequency of the selected source.
  • microprocessor 1 3 can measure a duration or width of an element of the selected horizontal sync pulse to determine the horizontal scanning frequency.
  • microprocessor 1 3 since microprocessor 1 3 is responsive to user selection of display signal input, horizontal frequency indicating logic can, for example, be implemented by hard wiring or a look up table to associate the user selected input signal with a specific input signal format and scanning frequency. Furthermore, since various display signals are connected to the display device via mechanically different connectors, the horizontal frequency determination can be derived from the input socket selected . For example NTSC signals, S-video signals and SVGA signals are each input to the display via differing, non- interchangeable connectors. Thus, based on one or a combination of the various horizontal frequency determination methods, microprocessor 1 3 is preferably programmed to send a horizontal frequency specific gain or amplitude control command via the data bus to video processor 1 1 .
  • Video processor 1 1 preferably contains an SVM generator with gain or SVM output signal amplitude controlled in response to control command data received from microprocessor 1 3 via the l 2 C bus.
  • the SVM gain is controlled by a 2-bit register that can attenuate the SVM signal by OdB, -6dB, -9dB, with in addition, the capability of inhibiting the SVM signal output.
  • Microprocessor 1 3 is preferably programmed such that the SVM signal is not attenuated, ie gain is set to OdB when 1 H video sources are determined, and for 2H sources microprocessor 1 3 generates control data which provides a - 6dB reduction in of SVM signal gain.
  • Video sources with scan rates higher than 2H are preferably attenuated in accordance with the transfer function illustrated in FIGURE 1 .
  • the SVM signal is attenuated 6dB to maintain the SVM signal within a predetermined range of amplitudes.
  • the controlled amplitude SVM signal is coupled to SVM driver 1 4 and ultimately SVM coil 1 5 to produce substantially similar image enhancement, independent of the display scanning frequency.
  • NTSC or other 1 H video signals can be converted into 2H video signals by up-converter 1 6. In this way signals with inherently lower image detail, or spatial resolution, are converted and receive detectable attributes indicative of 2H video signals.
  • up converted signals may be detected as 2H video signals
  • the image detail is not comparable with that of a signal that originated as 2H signal .
  • the up conversion process cannot add image detail absent from the original 1 H image.
  • microprocessor 1 3 can determine from an exemplary look up table or the like, an amplitude control value suitable for SVM enhancement of such up-converted images.
  • an up converted image can receive an SVM amplitude value between those provided for 1 H and 2H frequency sources.
  • FIGURES 5(a), 5(b), 5(c) and 5(d) illustrate the problem identified by applicants and the advantageous amplitude control solution described herein.
  • FIGURE 5(a) shows an example of an SVM signal at an output of a differentiator or SVM signal generator. The SVM signal was formed by differentiation of a 1 H luminance signal component comprising a 1 00 IRE pulse with 60 nanosecond rise and fall times.
  • FIGURE 5(c) shows an SVM signal formed by differentiation of a 2H video signal comprising a 100 IRE pulse with 30 nanosecond rise and fall times.
  • the exemplary waveforms for FIGURES 5(a) and 5(c) are chosen to be visually equal, when displayed. Both of these signals are depicted with reference to the output of derivative circuit 1 of FIGURE 2.
  • FIGURE 5(b) illustrates the amplitude of the 1 H SVM output signal as measured from the output of variable gain amplifier 2 in FIGURE 2.
  • FIGURE 5(d) shows the amplitude of the 2H SVM output signal similarly measured at the output of variable gain amplifier 2 in FIGURE 2.
  • the amplitude of the 1 H and 2H SVM output signals are approximately the same.
  • the SVM automatic gain control system maintains an optimal amplitude range for the scanning velocity modulation signal at multiple scan frequencies.

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Details Of Television Scanning (AREA)
  • Radar Systems Or Details Thereof (AREA)

Abstract

L'invention concerne un procédé permettant de contrôler la modulation de la vitesse de balayage dans un dispositif d'affichage vidéo pouvant fonctionner à plusieurs fréquences de balayage horizontales. Ce procédé consiste à générer, à partir de signaux possédant plusieurs fréquences de balayage horizontal, différents signaux de modulation de vitesse de balayage reliés au dispositif d'affichage, et à contrôler de manière sélective l'amplitude de chaque signal de modulation de vitesse de balayage dans une plage d'amplitudes déterminée.
PCT/US2000/002989 1999-02-09 2000-02-04 Controle de la modulation de la vitesse de balayage avec plusieurs frequences de balayage WO2000048390A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2000599203A JP2002537692A (ja) 1999-02-09 2000-02-04 複数の走査周波数における走査速度変調の制御
DE60001261T DE60001261T2 (de) 1999-02-09 2000-02-04 Steuerung der abtastgeschwindigkeitsmodulation bei mehrfachen abtastfrequenzen
AU34834/00A AU3483400A (en) 1999-02-09 2000-02-04 Control of scanning velocity modulation at multiple scanning frequencies
EP00913372A EP1151602B1 (fr) 1999-02-09 2000-02-04 Controle de la modulation de la vitesse de balayage avec plusieurs frequences de balayage

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11927899P 1999-02-09 1999-02-09
US60/119,278 1999-02-09

Publications (1)

Publication Number Publication Date
WO2000048390A1 true WO2000048390A1 (fr) 2000-08-17

Family

ID=22383516

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/002989 WO2000048390A1 (fr) 1999-02-09 2000-02-04 Controle de la modulation de la vitesse de balayage avec plusieurs frequences de balayage

Country Status (9)

Country Link
EP (1) EP1151602B1 (fr)
JP (1) JP2002537692A (fr)
KR (1) KR100759294B1 (fr)
CN (1) CN1169348C (fr)
AU (1) AU3483400A (fr)
DE (1) DE60001261T2 (fr)
ES (1) ES2185577T3 (fr)
TR (1) TR200102292T2 (fr)
WO (1) WO2000048390A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101656551A (zh) * 2008-08-21 2010-02-24 爱斯泰克（上海）高频通讯技术有限公司 超宽带脉冲信号发生器集成电路

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100584981B1 (ko) * 2004-11-20 2006-05-29 삼성전기주식회사 스캐닝 미러의 회전각 조절 장치

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6199467A (ja) * 1984-10-19 1986-05-17 Sony Corp マルチ走査形テレビジヨン受像機
JPS62254576A (ja) * 1986-04-28 1987-11-06 Hitachi Ltd 画質調整回路
JPS63123275A (ja) * 1986-11-12 1988-05-27 Mitsubishi Electric Corp 映像の輪郭補正装置
EP0784402A2 (fr) * 1996-01-10 1997-07-16 Matsushita Electric Industrial Co., Ltd. Récepteur de télévision

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6199467A (ja) * 1984-10-19 1986-05-17 Sony Corp マルチ走査形テレビジヨン受像機
JPS62254576A (ja) * 1986-04-28 1987-11-06 Hitachi Ltd 画質調整回路
JPS63123275A (ja) * 1986-11-12 1988-05-27 Mitsubishi Electric Corp 映像の輪郭補正装置
EP0784402A2 (fr) * 1996-01-10 1997-07-16 Matsushita Electric Industrial Co., Ltd. Récepteur de télévision

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 010, no. 279 (E - 439) 20 September 1986 (1986-09-20) *
PATENT ABSTRACTS OF JAPAN vol. 012, no. 130 (E - 603) 21 April 1988 (1988-04-21) *
PATENT ABSTRACTS OF JAPAN vol. 012, no. 375 (E - 666) 7 October 1988 (1988-10-07) *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101656551A (zh) * 2008-08-21 2010-02-24 爱斯泰克（上海）高频通讯技术有限公司 超宽带脉冲信号发生器集成电路

Also Published As

Publication number Publication date
TR200102292T2 (tr) 2001-12-21
DE60001261D1 (de) 2003-02-27
CN1344463A (zh) 2002-04-10
DE60001261T2 (de) 2003-08-07
CN1169348C (zh) 2004-09-29
KR100759294B1 (ko) 2007-09-18
JP2002537692A (ja) 2002-11-05
EP1151602A1 (fr) 2001-11-07
EP1151602B1 (fr) 2003-01-22
KR20010094762A (ko) 2001-11-01
ES2185577T3 (es) 2003-05-01
AU3483400A (en) 2000-08-29

Similar Documents

Publication Publication Date Title
EP0469567B1 (fr) Dispositif de modulation de vitesse de balayage de rayon avec circuit de mise hors service
JPS6096081A (ja) 画像再生装置の電流変更装置
US5699127A (en) Automatic brightness limiter automatic control circuit, contrast limiter control circuit, luminance/color difference signal processor and video display apparatus
EP1151602B1 (fr) Controle de la modulation de la vitesse de balayage avec plusieurs frequences de balayage
US5920157A (en) Circuit and method for compensating for fluctuations in high voltage of fly back transformer for semiwide-screen television receiver
US6307596B1 (en) Circuit and method for indicating image adjustment pattern using OSD
JPH07118780B2 (ja) 画質補償装置
JP2929048B2 (ja) テレビジョン装置
EP1098518B1 (fr) Control de l'emission des affichages de vidéo
US6570625B1 (en) Display apparatus and display method
US6008861A (en) OSD vertical blanking signal selection circuit for display apparatus
JP3407677B2 (ja) 速度変調回路
JPS5931913B2 (ja) テレビジヨン受像機
MXPA01007885A (en) Control of scanning velocity modulation at multiple scanning frequencies
KR100518946B1 (ko) 클램프 펄스 생성 시스템 및 비디오 디스플레이
JPS62128669A (ja) 画像出力装置
JPH09247487A (ja) オートスキャン映像表示装置
JPH05115052A (ja) ピーク輝度伸長回路
JPH04241577A (ja) テレビジョン受像機
JPH05191662A (ja) 垂直偏向回路
JPH06178143A (ja) 水平ブランキング信号生成回路
JPH01158888A (ja) テレビジョン受像機
JPH05199475A (ja) ペデスタルレベル調整回路

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 00805313.8

Country of ref document: CN

AK Designated states

Kind code of ref document: A1

Designated state(s): AE AL AM AT AU AZ BA BB BG BR BY CA CH CN CR CU CZ DE DK DM EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG US UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
WWE Wipo information: entry into national phase

Ref document number: PA/a/2001/007885

Country of ref document: MX

ENP Entry into the national phase

Ref document number: 2000 599203

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 1020017010012

Country of ref document: KR

Ref document number: 2001/02292

Country of ref document: TR

WWE Wipo information: entry into national phase

Ref document number: 2000913372

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 1020017010012

Country of ref document: KR

WWP Wipo information: published in national office

Ref document number: 2000913372

Country of ref document: EP

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

WWE Wipo information: entry into national phase

Ref document number: 09913097

Country of ref document: US

WWG Wipo information: grant in national office

Ref document number: 2000913372

Country of ref document: EP