WO2000035001A1 - Verfahren zur eingehäusung elektronischer bauelemente - Google Patents
Verfahren zur eingehäusung elektronischer bauelemente Download PDFInfo
- Publication number
- WO2000035001A1 WO2000035001A1 PCT/DE1999/003469 DE9903469W WO0035001A1 WO 2000035001 A1 WO2000035001 A1 WO 2000035001A1 DE 9903469 W DE9903469 W DE 9903469W WO 0035001 A1 WO0035001 A1 WO 0035001A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- substrate
- housing
- cavities
- layer
- cover
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 69
- 239000000758 substrate Substances 0.000 claims abstract description 74
- 238000005304 joining Methods 0.000 claims abstract description 5
- 239000011521 glass Substances 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 11
- 239000012212 insulator Substances 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 238000001465 metallisation Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- 239000004922 lacquer Substances 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000007789 sealing Methods 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 235000012431 wafers Nutrition 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 9
- 239000000919 ceramic Substances 0.000 description 5
- 239000011810 insulating material Substances 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 239000006089 photosensitive glass Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 239000006090 Foturan Substances 0.000 description 1
- 244000027321 Lychnis chalcedonica Species 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000003044 adaptive effect Effects 0.000 description 1
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 1
- 230000002146 bilateral effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000006112 glass ceramic composition Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000010297 mechanical methods and process Methods 0.000 description 1
- 239000012811 non-conductive material Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000002966 varnish Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
Definitions
- the invention relates to a method for housing electronic components such as Gunn diodes.
- Gunn diodes are used to generate these radar waves. These are made of III-V semiconductor material such as GaAs or InP and generate a high-frequency electromagnetic wave when a DC voltage is applied.
- the Gunn diode element for example, has a diameter of 70 ⁇ m and a thickness of 10 ⁇ m and is contacted on its top and bottom.
- Such known Gunn diodes are usually completely enclosed and hermetically sealed by a housing consisting of a base part, a ceramic ring and a cover part.
- the ceramic ring serves on the one hand as an insulator between the two poles of the diode and on the other hand to absorb mechanical contact and installation forces in the Use case.
- a bonded gold foil (“Maltese cross") is used to make contact with the diode.
- Such a housing must be produced in sequential process steps and is therefore expensive. Due to tolerances in the production processes and components, a relatively large spread of the high-frequency properties of the housed component is also not to avoid.
- the method according to the invention for housing electronic components has the steps of forming a plurality of cavities on a housing substrate, equipping the cavities with the electronic components, sealing the cavities with a cover layer or a cover substrate and separating the components packaged in this way .
- a large number of component housings can be produced simultaneously in one method, which considerably reduces the production costs.
- the housing substrate can consist of semiconductor material, such as silicon, or of photostructurable glass. This has the advantage that the processing of silicon or photostructurable glass is technologically very well mastered and therefore very small manufacturing tolerances can be represented. This allows good reproducibility of the high-frequency properties to be achieved.
- the 'process of the invention also allows housing of very small dimensions, which have a low load by differential thermal expansion of different materials.
- Silicon, glass or glass ceramic material is also able to safely absorb the mechanical contact and installation forces that occur during use.
- the housing substrate can be provided on its side facing away from the cover substrate or the cover layer with a metal layer which serves to contact the packaged electronic component. If the housing substrate consists of semiconductor material, the side of the housing substrate facing the cover substrate or the cover layer is advantageously provided with an insulating layer for insulating the two poles of the electronic component.
- the cavities can be formed in the housing substrate as openings or only as flat cavities in the surface of the housing substrate.
- the electronic components to be packaged are arranged on a component carrier layer in a number corresponding to the number of cavities formed in the housing substrate, the assembly step being carried out the cavities with the electronic components by joining the housing substrate and the component carrier layer.
- the latter can be designed as a metal, in particular as a silver layer.
- the lid substrate can consist of semiconductor material such as silicon.
- the cover layer which can be used alternatively, can be formed from an organic dielectric into which contact holes are made. If the cover substrate consists of a conductive material, the component can advantageously be contacted by means of a microstructured contact spring which is attached to the side of the cover substrate facing the cavity. This ensures permanent and reliable contacting of the component.
- the upward-facing side of the component can advantageously be contacted by means of a metal layer which is vapor-deposited or sputtered into a contact hole in the organic dielectric.
- a photosensitive varnish is therefore particularly suitable as an organic dielectric, e.g. Polyimide or BCB (BenzoCycloButen).
- the packaged electronic components can then be separated, for example by a sawing process, and are, for example, on one Film for further processing 'available "Blue-M tape mentioned.
- insulator structures serving as side walls of the housing are exposed from the housing substrate, for example made of photosensitive glass, which correspond to the known ceramic ring.
- these insulator structures can also be produced in large numbers in parallel and therefore inexpensively, for example by selective etching of the photostructurable glass, corresponding to the number of components to be packaged.
- the cover substrate can first be joined to the housing substrate and then the component carrier layer with the components can be put on, or conversely, the component carrier layer can first be put together with the housing substrate and finally the cover substrate can be put on.
- FIG. 1 is a schematic illustration to illustrate the method according to the invention
- Figure 2 is a schematic view illustrating 'a variant of the inventive method
- FIG. 3 shows a component housing with a deep cavity and a microstructured contact spring produced by the method according to the invention
- FIG. 4 shows a component housing with the deep cavity and a cover layer formed from an organic dielectric, produced using the method according to the invention
- FIG. 5 shows a component housing produced by the method according to the invention with a flat cavity and an organic dielectric as a cover layer;
- FIG. 6 shows a component housing produced by the method according to the invention with a flat cavity and cover layer made of organic dielectric and additional back contacting
- FIG. 7 shows the essential method steps of an exemplary embodiment of the method according to the invention.
- FIG. 8 shows the essential method steps of a further exemplary embodiment of the method according to the invention.
- FIG. 1 shows the housing substrate 2, which is already provided with cavities 6 for receiving the electronic components 8, for example Gunn diodes, and a cover substrate 4 to explain the method according to the invention for housing or packaging an electronic component Si wafers are formed; however, other materials such as photostructurable glass are also possible.
- a regular two-dimensional arrangement of cavities 6 is introduced into the silicon surface by means of a photolithographic method and subsequent etching steps or micromechanical structuring methods known per se.
- the size of the cavities depends on the size of the component to be packaged or any contact springs or the like. In the example shown in FIG. 1, the depth of the cavities is approximately one third of the thickness of the housing substrate 2. However, the cavity depth can also be less.
- the housing substrate 2 For contacting a contact arranged on the underside of the component 8, which is already present in the cavity on the left, the housing substrate 2 can be provided on its underside with a conductive layer 3, the current of the conductive layer 3 flows to the underside of the electronic component 8 through the silicon package substrate.
- the cavities 6 After the cavities 6 have been prepared, they are equipped with the components 8, whereupon the housing is closed by applying the cover substrate 4, which can likewise consist of silicon.
- the cover substrate 4 For contacting a contact arranged on the upper side of the component or the diode 8, a contact spring produced by electrodeposition on the cover substrate 4 is preferably used, which is shown for example in FIG. 3 and is designated by reference number 9.
- the cover substrate 4 After the cover substrate 4 has been placed and glued to the housing substrate 2, the individual packaged diodes can be separated, for example by sawing, and are then available for further processing.
- the simultaneous production of a large number of housings results in considerable cost savings.
- the individual component Housing are manufactured with great precision, so that "there is a good reproducibility of the dimensionally dependent high-frequency properties.
- the small manufacturing tolerances also allow very small dimensions of the housing as a whole, whereby the mechanical stress due to different thermal expansion of different materials used in the housing during Operation remains low.
- the insulating layer 5 shown in FIG. 1 can be omitted if the housing substrate 2 is formed from an insulating material such as photosensitive glass. Contacting the diode by means of the substrate material is then of course not possible.
- FIG. 2 illustrates a variant of the method according to the invention for housing electronic components.
- the housing substrate 2 a Si or glass wafer, is thinned in the central area and provided with openings there. The remaining thick substrate edge stabilizes the substrate and is used for handling purposes.
- the openings 6 form the cavities for receiving the electronic components.
- Insulating material 7, for example SiN or SiO 2 is applied to the walls of the openings, as can also be seen in FIG.
- the components 8 in the method illustrated in FIG. 2 are on a component carrier layer 16, for example a GaAs Wafers arranged.
- the wafer 16 forming the component carrier layer preferably has a smaller diameter than the Si wafer 2 forming the housing substrate, so that it can be accommodated in the middle, thinly etched region of the wafer.
- the components 8 are preferably produced in a common process on the component carrier layer 16.
- the assembly process for the cavities 6 with the components 8 then takes place by joining the component carrier wafer 16 with the Sübstrat wafer 2. This assembly variant simplifies the assembly process, which enables an overall even more cost-effective manufacturing process.
- FIG. 3 shows a cross-sectional view of a first exemplary embodiment of a component housing produced using the method according to the invention.
- a cavity 6 is formed in the silicon housing substrate 2 by micromechanical etching.
- a component 8, such as a Gunn diode, is arranged in the cavity 6, the upper contact of which is contacted by means of a contact spring 9 that is micromechanically produced by galvanic metal deposition.
- the cover substrate 4 is also made of half-liter material, such as silicon, and is used to supply power to the upper diode contact.
- the lower diode contact is contacted by means of a conductive layer 3, for example made of metal, applied to the underside of the substrate by vapor deposition or sputtering.
- An insulating layer 5 is provided to isolate both poles.
- FIG. 4 shows a further exemplary embodiment of a component housing produced by means of the method according to the invention before the separation.
- a deep cavity 6 is etched out in the housing substrate 2 and is equipped with the component 8.
- the cover layer 4 is formed by an organic dielectric such as, for example, a photosensitive lacquer.
- an etching pit is formed, by means of which a contact layer 11 made of evaporated or sputtered metal makes contact with the upper side of the diode.
- FIG. 5 A further exemplary embodiment of a component housing produced by means of the method according to the invention before separation is shown in FIG. 5.
- the cavity is designed only as a flat cavity.
- the component 8 is contacted from below via the conductive substrate itself, while the electrical connection to the top of the component takes place via a contact layer 13 which, similar to the exemplary embodiment shown in FIG. 4, is formed in a recess in an organic dielectric serving as a cover layer 4 .
- the housing substrate 2 for example, made of poorly conductive or non-conductive material such as photostructurable glass, so that a contact layer 15 is necessary for contacting the downward-facing diode front. This is vapor-deposited or sputtered into the housing substrate 2 after etching a contact hole.
- FIG. 7 schematically shows the method steps of an exemplary embodiment of the method according to the invention.
- FIG. 7a shows a component 8 located on a component carrier layer 16 representative of the large number of components located on the component carrier layer 16.
- the component carrier layer 16 consists, for example, of silver.
- FIG. 7b shows the state in the manufacturing process after the housing substrate has been joined to the component carrier layer 16.
- the cover layer 4 consisting of an organic, photosensitive dielectric, for example BCB
- FIG. 7c the cover layer 4
- the component carrier layer 16 by means of an etching process or the like is removed and the remaining arrangement is cured, for example by heating (FIG. 7d).
- contact holes are formed in the organic dielectric at the position of the respective components (FIG. 7e), for example by means of a photostructuring method or by means of a laser processing method, and the dielectric between the housings is removed if necessary.
- FIG. 7f shows the state when a contact layer 11 for contacting the component 8 has been sputtered on through the contact hole.
- the individual housed components are then separated by sawing or the like (FIG. 7g).
- FIG. 8 schematically shows a further exemplary embodiment of the housing method according to the invention.
- the housing substrate 20 is designed as a carrier layer from which insulator structures 21 are formed which correspond to the ceramic rings in the prior art.
- the carrier layer 20 consists of a photo-structurable glass, which is available, for example, under the brand name Foturan ⁇ .
- this carrier layer 20 is shown in cross section on the left and the photo mask 18 is shown in a top view on the right side.
- the carrier layer 20 is first exposed and annealed by the mask 18 at the areas shown in broken lines. This defines the glass areas to be etched later.
- a component carrier layer 16 is then added with the components 8 similar to that shown in FIG. 2, so that closed cavities 6 with the component elements 8 and contact springs 9 located therein are formed.
- the sacrificial layer 4a is then etched away (FIG. 8g).
- the housing components thus formed are separated by saws, for example, and are available for further processing.
- An enlarged view of a finished, packed component is shown in FIG. 8i.
- the method according to the invention enables the simultaneous production of a large number of housings for electronic components, including Contacting with high precision and low manufacturing costs.
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Micromachines (AREA)
- Manufacture Of Switches (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP99957956A EP1147553A1 (de) | 1998-12-07 | 1999-10-30 | Verfahren zur eingehäusung elektronischer bauelemente |
JP2000587368A JP2002532876A (ja) | 1998-12-07 | 1999-10-30 | 電子的な構成素子をケーシング封入する方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19856331A DE19856331B4 (de) | 1998-12-07 | 1998-12-07 | Verfahren zur Eingehäusung elektronischer Bauelemente |
DE19856331.0 | 1998-12-07 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2000035001A1 true WO2000035001A1 (de) | 2000-06-15 |
Family
ID=7890209
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE1999/003469 WO2000035001A1 (de) | 1998-12-07 | 1999-10-30 | Verfahren zur eingehäusung elektronischer bauelemente |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP1147553A1 (de) |
JP (1) | JP2002532876A (de) |
DE (1) | DE19856331B4 (de) |
WO (1) | WO2000035001A1 (de) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10038999A1 (de) * | 2000-08-10 | 2002-03-21 | Bosch Gmbh Robert | Gehäuse für ein elektronisches Bauelement |
US9847235B2 (en) * | 2014-02-26 | 2017-12-19 | Infineon Technologies Ag | Semiconductor device with plated lead frame, and method for manufacturing thereof |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4021839A (en) * | 1975-10-16 | 1977-05-03 | Rca Corporation | Diode package |
GB2042802A (en) * | 1979-02-14 | 1980-09-24 | Ferranti Ltd | Encapsulation of semiconductor devices |
EP0085607A2 (de) * | 1982-02-02 | 1983-08-10 | Thomson-Csf | Verfahren zur gleichzeitigen Produktion von Hyperfrequenzdioden mit eingebauter Einkapselung und nach diesem Verfahren hergestellte Dioden |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5595338A (en) * | 1979-01-12 | 1980-07-19 | Nippon Telegr & Teleph Corp <Ntt> | Integrated circuit |
FR2589629B1 (fr) * | 1985-11-05 | 1987-12-18 | Radiotechnique Compelec | Composant opto-electronique pour montage en surface et son procede de fabrication |
JPH01134956A (ja) * | 1987-11-20 | 1989-05-26 | Hitachi Ltd | 半導体装置の組立方法 |
US4907065A (en) * | 1988-03-01 | 1990-03-06 | Lsi Logic Corporation | Integrated circuit chip sealing assembly |
JPH01258458A (ja) * | 1988-04-08 | 1989-10-16 | Nec Corp | ウェーハ集積型集積回路 |
JPH02303147A (ja) * | 1989-05-18 | 1990-12-17 | Hitachi Chem Co Ltd | 半導体素子搭載用配線板及びその製造法並びに該配線板を用いた半導体装置 |
US5545291A (en) * | 1993-12-17 | 1996-08-13 | The Regents Of The University Of California | Method for fabricating self-assembling microstructures |
JP3447025B2 (ja) * | 1995-07-31 | 2003-09-16 | 日本インター株式会社 | 表面実装型電子部品及びその製造方法 |
DE19620940A1 (de) * | 1995-11-17 | 1997-05-22 | Werner Prof Dr Buff | Elektronisches Bauelement und Verfahren zu seiner Herstellung |
-
1998
- 1998-12-07 DE DE19856331A patent/DE19856331B4/de not_active Expired - Fee Related
-
1999
- 1999-10-30 WO PCT/DE1999/003469 patent/WO2000035001A1/de active Application Filing
- 1999-10-30 JP JP2000587368A patent/JP2002532876A/ja active Pending
- 1999-10-30 EP EP99957956A patent/EP1147553A1/de not_active Withdrawn
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4021839A (en) * | 1975-10-16 | 1977-05-03 | Rca Corporation | Diode package |
GB2042802A (en) * | 1979-02-14 | 1980-09-24 | Ferranti Ltd | Encapsulation of semiconductor devices |
EP0085607A2 (de) * | 1982-02-02 | 1983-08-10 | Thomson-Csf | Verfahren zur gleichzeitigen Produktion von Hyperfrequenzdioden mit eingebauter Einkapselung und nach diesem Verfahren hergestellte Dioden |
Non-Patent Citations (1)
Title |
---|
E. BASSOUS: "bonding together surfaces coated with silicon dioxide", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 19, no. 7, December 1976 (1976-12-01), new york, pages 2777 - 2778, XP002131952 * |
Also Published As
Publication number | Publication date |
---|---|
DE19856331A1 (de) | 2000-06-08 |
JP2002532876A (ja) | 2002-10-02 |
DE19856331B4 (de) | 2009-01-02 |
EP1147553A1 (de) | 2001-10-24 |
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