WO2000024057A1 - Procede de fabrication d'un dispositif a semi-conducteur sur un corps de silicium, une surface de ce corps etant dotee d'une grille d'alignement et d'un motif d'oxyde partiellement en retrait - Google Patents

Procede de fabrication d'un dispositif a semi-conducteur sur un corps de silicium, une surface de ce corps etant dotee d'une grille d'alignement et d'un motif d'oxyde partiellement en retrait Download PDF

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Publication number
WO2000024057A1
WO2000024057A1 PCT/EP1999/007035 EP9907035W WO0024057A1 WO 2000024057 A1 WO2000024057 A1 WO 2000024057A1 EP 9907035 W EP9907035 W EP 9907035W WO 0024057 A1 WO0024057 A1 WO 0024057A1
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WIPO (PCT)
Prior art keywords
semiconductor device
silicon body
alignment
pattern
manufacturing
Prior art date
Application number
PCT/EP1999/007035
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English (en)
Inventor
Christiaan J. Muller
Frank A. J. M. Driessen
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Koninklijke Philips Electronics N.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics N.V. filed Critical Koninklijke Philips Electronics N.V.
Priority to JP2000577712A priority Critical patent/JP2002528895A/ja
Priority to EP99948826A priority patent/EP1046192A1/fr
Priority to KR1020007006766A priority patent/KR20010033319A/ko
Publication of WO2000024057A1 publication Critical patent/WO2000024057A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the invention relates to a method of manufacturing a semiconductor device, in particular an integrated circuit, in a silicon body which is provided at a surface with an alignment grating for aligning the silicon body relative to masks which are used in a number of successive process steps to image patterns onto the surface of the silicon body, the alignment grating being provided in the form of a strip pattern of adjacent elevations and valleys, and the surface also being provided with a mask of a material which protects the silicon body against oxidation, which mask is provided with apertures at the location of the semiconductor device, whereafter the silicon body is provided with an oxide pattern by means of oxidation, which pattern is recessed in the silicon body over at least a part of its thickness and defines active regions in the silicon body.
  • a method of the type mentioned in the opening paragraph is known from United States patent specification 5,700,732.
  • a surface of the silicon body is provided with an alignment grating in the form of a strip pattern of adjacent elevations and valleys, which correspond to a difference in height which is desirable for aligning.
  • the previously provided alignment grating is used to align the silicon body relative to masks which, during these process steps, are used to image patterns onto the surface of the silicon body.
  • a disadvantage of the known method is that, prior to the process steps, which are relevant for the manufacture of the semiconductor device, extra process steps are necessary to provide the alignment grating.
  • These extra process steps generally include a lithography step in which regions on the surface of the silicon body are defined for the valleys to be ultimately provided, followed by an etch step in which the valleys are formed by performing an etching operation on the silicon body over a specific distance corresponding to the difference in height necessary for aligning.
  • the extra lithography and etch steps contribute significantly to the overall number of necessary process steps and hence to the total process costs.
  • the inventive method mentioned in the opening paragraph is characterized in that the alignment grating and the partly recessed oxide pattern are provided simultaneously, the material which protects against oxidation being provided at the location of the alignment grating to be produced so as to comprise first wide strips, where the surface remains entirely free of recessed oxide, which alternate with second wide strips, which are each formed by a sub-pattern of relatively narrow strips of the material which protects against oxidation, which narrow strips are separated from each other by relatively narrow apertures, which are smaller than the apertures at the location of the semiconductor device, whereafter, during oxidation, each of the second wide strips is provided with a segmented, also partly recessed, oxide pattern with a profiled surface, the relatively narrow apertures having a width such that the recessed oxide pattern in the alignment grating is thinner than the simultaneously formed recessed oxide pattern in the semiconductor device.
  • this is used to create, at the location of the alignment grating, a difference in height necessary for aligning the silicon body, which difference in height is smaller than that which would be created if the oxide could also attain the full thickness at the location of the alignment grating, i.e. the thickness at the location of the semiconductor device.
  • it is possible to provide an oxide pattern which is partly recessed in the silicon body and simultaneously provide the surface of the silicon body with an alignment grating necessary for the further manufacture of the semiconductor device, without this leading to extra process steps and hence extra process costs.
  • An embodiment of the method in accordance with the invention is characterized in that the alignment grating is used, both in process steps preceding the provision of the opaque layer and in subsequent process steps, to align the silicon body relative to the masks used in the relevant process steps.
  • the alignment grating can be used for aligning purposes throughout the manufacture of the semiconductor device .
  • An embodiment of the method in accordance with the invention is characterized in that the recessed oxide pattern in the alignment grating is provided in such a manner that at the location of the alignment grating an average optical difference in height is achieved between the first and the second wide strips, which corresponds approximately to (2n+l) ⁇ 74, where n is an integer > 0 and ⁇ is the wavelength of the light used for aligning.
  • n is an integer > 0
  • ⁇ is the wavelength of the light used for aligning.
  • An embodiment of the method in accordance with the invention is characterized in that approximately ⁇ /4 is used as the average optical difference in height.
  • approximately ⁇ /4 is used as the average optical difference in height.
  • An embodiment of the method in accordance with the invention is characterized in that the recessed oxide pattern in the alignment grating is provided so as to have an average thickness in the range from approximately 0J to 0.4 ⁇ m.
  • the thickness of the recessed oxide pattern in the alignment grating lies in the range from approximately 0J to 0.4 ⁇ m, an average optical difference in height corresponding to approximately ⁇ /4 is achieved between the first and second wide strips of the alignment grating, thereby minimizing alignment errors.
  • An embodiment of the method in accordance with the invention is characterized in that the recessed oxide pattern in the semiconductor device is provided so as to have a thickness ranging from 0.5 to 1.0 ⁇ m. If the thickness of the recessed oxide pattern in the semiconductor device lies in the above-indicated range, it is possible, using the method in accordance with the invention, to create the optical difference in height, necessary for aligning, of approximately ⁇ /4 between the first and second wide strips of the alignment grating.
  • An embodiment of the method in accordance with the invention is characterized in that the alignment grating is provided with a pitch ranging from 2 to 20 ⁇ m.
  • the use of a pitch of 16.0 ⁇ m has the advantage that an alignment grating based on this pitch is compatible with conventional aligning equipment, the operation of which is still based on a pitch of 16.0 ⁇ m, possibly in combination with a pitch of 17.6 ⁇ m. Since alignment errors are proportional to the pitch of the alignment grating, the pitch of the alignment grating will be reduced in the future, in view of the manufacture of new generations of integrated circuits having smaller line widths, thus enabling a more accurate and more reliable alignment to be achieved.
  • An embodiment of the method in accordance with the invention is characterized in that the first and second wide strips are provided in an at least substantially equal width.
  • the use of first and second wide strips of equal width causes the intensities of sub-beams deflected in a first diffraction order by the alignment grating to be maximal which sub-beams are still used in conventional aligning equipment.
  • An embodiment of the method in accordance with the invention is characterized in that the alignment grating is provided on the surface of the silicon body in a local alignment marker, comprising two patterns of adjacent strips which are rotated through 90 degrees relative to each other, the pitch of the patterns being at least substantially equal.
  • a local alignment marker is important for aligning a region on the silicon body's surface bordering on the alignment marker relative to a mask pattern, commonly referred to as local aligning, in the X-direction and the Y-direction.
  • An embodiment of the method in accordance with the invention is characterized in that the alignment grating is provided on the surface of the silicon body in a global alignment marker, comprising four patterns of adjacent strips which are each rotated through 90 degrees relative to the preceding pattern of strips, which patterns can be divided into two groups of two adjoining patterns, the pitch of the groups being different.
  • a global alignment marker is important for aligning the entire silicon body relative to a mask, commonly referred to as global aligning, in the X-direction and the Y-direction. The use of a different pitch increases the capture range of the global alignment marker.
  • An embodiment of the method in accordance with the invention is characterized in that the global alignment marker is provided at least in duplicate on the surface of the silicon body, each global alignment marker taking up a position near an edge of the silicon body. In order to be able to accurately align the entire silicon body relative to a mask, the global alignment marker must be present at least in duplicate on the surface of the silicon body.
  • Figs. 1 through 5 show in diagrammatic cross-section successive stages of the manufacture of a semiconductor device with an at least partly recessed oxide pattern and the concurrent manufacture and further development of an alignment grating in a silicon body by means of the method in accordance with the invention
  • Fig. 6 is a diagrammatic plan view of a global alignment marker manufactured by means of the method in accordance with the invention.
  • Figs. 1 through 5 show, in diagrammatic cross-section, successive stages in the manufacture of a semiconductor device 5 with an at least partly recessed oxide pattern 12, and the simultaneous manufacture and further development of an alignment grating 7 by means of the method in accordance with the invention.
  • a surface 2 of a silicon body 1 of a first conductivity type in this example the p-conductivity type, is first provided with a layer 3 of a material protecting the silicon body against oxidation (Fig. 1).
  • Said layer 3 is customarily formed by an oxide layer obtained by oxidation of the silicon body 1, which oxide layer is customarily referred to as padoxide, and on which a layer of silicon nitride is deposited, but said layer 3 may alternatively be formed by a layer of oxynitride or by successive layers of these materials.
  • a mask 4 of a photoresist if necessary in combination with a bottom-antireflection layer, is provided, which mask has apertures 6 at the location of the semiconductor device 5, which apertures correspond to locations of the partly recessed oxide pattern 12 to be formed.
  • the mask 4 of photoresist has a pattern of first relatively wide strips 8, where the layer 3 of material protecting against oxidation is fully covered with photoresist, which alternate with second relatively wide strips 9, which each consist of a sub-pattern of relatively narrow strips 10 covered with photoresist, which are separated from each other by relatively narrow apertures
  • the mask 4 of photoresist is removed and apertures 6' and 11' in the layer 3 of material protecting against oxidation remain.
  • the pattern of the mask 4 of photoresist at the location of the alignment grating 7 has been transferred to the layer 3 of material protecting against oxidation.
  • the silicon body 1 is subsequently subjected to an oxidation treatment, for example a thermal oxidation, in which, at the location of the semiconductor device 5, the partly recessed oxide pattern 12 is formed which defines an active region 13 in the silicon body 1 (Fig. 3).
  • an oxidation treatment for example a thermal oxidation
  • the relatively narrow apertures 11' at the location of the second wide strips 9 of the alignment grating 7 are made so small relative to the apertures 6' at the location of the semiconductor device 5, that during the subsequent thermal oxidation oxide is formed in the relatively narrow apertures 11' in a thickness which is smaller than that of the oxide simultaneously formed in the apertures 6'.
  • This is utilized to create, at the location of the alignment grating 7, a difference in height which is necessary to align the silicon body 1, which difference in height is smaller than the difference in height that would be created if, also at the location of the alignment grating, the oxide could attain the full thickness, that is the thickness at the location of the semiconductor device 5, which in this example ranges from 0.5 to 1.0 ⁇ m.
  • the alignment grating 7 (Fig. 3) thus formed consists of first relatively wide strips 8, where the surface 2 of the silicon body 1 is free of oxide, which alternate with second relatively wide strips 9, which are each provided with the segmented, partly recessed oxide pattern 14.
  • the alignment grating 7 is used to align the silicon body 1 relative to masks (not shown), which are used in these process steps to image patterns onto the surface of the silicon body.
  • a detailed description of an aligning process and the aligning equipment used, customarily referred to as wafer stepper, is given in United States patent specification 4,251 ,160.
  • the alignment grating 7 provided in the silicon body in the manner described above is exposed by means of a laser beam or another collimated beam and imaged onto a corresponding alignment grating which is provided in the mask.
  • the exposed alignment grating 7 behaves like a phase-diffraction grating with a pitch corresponding to the regular interval between the repetitive, equal patterns which each consist of a first wide strip 8 which borders on a second wide strip 9.
  • the sub- beams deflected by the alignment grating 7 in different diffraction orders above 0 each contain an indication about the position of the alignment grating 7 relative to the corresponding alignment grating in the mask.
  • the image of the alignment grating 7 provided in the silicon body 1 is accurately matched with the corresponding alignment grating in the mask, so that the silicon body 1 is properly aligned relative to the mask.
  • the first and second wide strips 8 and 9 of the alignment grating 7 are of equal width in the range from 1 to 10 ⁇ m.
  • the use of equally wide first and second strips has the advantage that intensities of the sub-beams deflected in the first diffraction order by the alignment grating, which sub-beams are still used in conventional alignment equipment, are maximal.
  • the first and second wide strips 8 and 9 may alternatively be of different width, within the above-indicated range, which may be advantageous if sub- beams deflected in diffraction orders above 1 are used.
  • the pitch of the alignment grating 7 generally lies in the range from 2 to 20 ⁇ m.
  • the use of a pitch of 16.0 ⁇ m has the advantage that an alignment grating based on this pitch is compatible with conventional alignment equipment, the operation of which is still based on a pitch of 16.0 ⁇ m, if necessary in combination with a pitch of 17.6 ⁇ m. Since alignment errors are proportional to the pitch of the alignment grating, said pitch of the alignment grating will be reduced in the future in view of the manufacture of new generations of integrated circuits with smaller line widths, so that a more accurate and more reliable alignment can be brought about.
  • the light used for aligning generally lies in the wavelength range from 500 to 1100 nm.
  • Use can be made, for example, of a He-Ne laser having a wavelength of 633 nm, which is currently the most widely used aligning beam, but use can also be made of a Nd:YAF laser having a wavelength of 1064 nm, a Nd:YLF laser having a wavelength of 1047 nm or a ⁇ i-V or II- VI diode laser having a wavelength which is determined by the semiconductor material used, for example InGaP having a wavelength range around 500 nm or InGaAs having a wavelength range between approximately 1000 and 1500 nm.
  • InGaP having a wavelength range around 500 nm
  • InGaAs having a wavelength range between approximately 1000 and 1500 nm.
  • an average optical path length difference between the deflected beams originating from the first wide strips 8 and the second wide strips 9 is created, which corresponds approximately to (2n+l) ⁇ /2, where n is an integer equal to or greater than 0 and ⁇ is the wavelength of the light used for aligning.
  • the light is reflected, at the location of the second wide strips 9 which are each provided with the segmented, partly recessed oxide pattern 14, at the profiled interface 16 between the partly recessed oxide pattern 14 and the silicon body 1.
  • the first wide strips 8 where the surface of the silicon body is free of oxide, reflection of the light takes place at the surface 2 of the silicon body 1. It has been found that an average optical difference in height of approximately ⁇ /4 between the first and the second wide strips 8 and 9 is achieved if the thickness of the oxide in the relatively narrow apertures
  • 11 ' ranges from approximately 0.1 to 0.4 ⁇ m at the location of the alignment grating.
  • a gate oxide 17 is provided at the location of the semiconductor device 5 (Fig. 4).
  • a layer of polysilicon 18 is provided which, in this example, is the first opaque layer.
  • the layer of polysilicon 18 is provided with a pattern, if necessary after doping with, for example, phosphor, so that it can be used as a gate electrode 19.
  • source and drain-forming silicon regions 20 and 21 of a second conductivity type in this example the n-conductivity type, are formed via implantation, the partly recessed oxide pattern 12 and the gate electrode 19 jointly serving as a mask.
  • a second conductivity type in this example the n-conductivity type
  • a further dielectric layer 24, in this case of silicon oxide is formed and provided with contact holes for providing contact between the first metal layer 23 and a second metal layer 25, in this case of aluminium, which after it has been provided on the surface is patterned at the location of the semiconductor device 5.
  • the dielectric layers 22 and 24 are removed at the location of the alignment grating 7 during the formation of the above- mentioned contact holes in said layers.
  • silicon oxide other suitable electrically insulating materials, such as for example silicon nitride, may be used for the dielectric layers 22 and 24.
  • the metal layers 23 and 25 may alternatively be made of a material other than aluminium, for example tungsten or another suitable metal or combination of metals.
  • Fig. 6 shows a global alignment marker 26 on an enlarged scale, which comprises four alignment gratings 27, 28, 29 and 30 which are each rotated through 90 degrees relative to the preceding alignment grating, said alignment gratings being made by means of the method in accordance with the invention.
  • each of the alignment gratings is provided so as to correspond to a pattern formed by the alternating first relatively wide strips 8, where the surface of the silicon body is free of recessed oxide, and the second relatively wide strips 9, which are each provided with the segmented, partly recessed oxide pattern 14.
  • the global alignment marker 26 is a two-dimensional alignment marker, the alignment gratings 27 and 29 being used to align in the X-direction, and the alignment gratings 28 and 30 to align in the Y-direction.
  • the alignment gratings 27 and 28 have an equal pitch PI in the range from 2 to 20 ⁇ m, for example 16.0 ⁇ m, while the alignment gratings 29 and 30 have a different pitch P2, which also ranges from 2 to 20 ⁇ m, for example 17.6 ⁇ m.
  • the use of different pitches generally leads to an increase of the capture range of the alignment marker in the X-direction as well as in the Y-direction.
  • Each of the alignment gratings may occupy a surface area of, for example, 200 x 200 ⁇ m. Consequently, the global alignment marker 26 occupies an overall surface area of approximately 400 x 400 ⁇ m.
  • a two-dimensional alignment marker may have shapes other than the one indicated in this example.
  • the surface 2 of the silicon body is generally provided with at least two global alignment markers 26, which are individually provided at an edge of the silicon body outside regions where the mask pattern is imaged.
  • the surface 2 of the silicon body is generally provided with at least two global alignment markers 26, which are individually provided at an edge of the silicon body outside regions where the mask pattern is imaged.
  • These local alignment markers are also two-dimensional and generally consist of two alignment gratings which are rotated through 90 degrees relative to each other and which have an equal pitch in the range from 2 to 20 ⁇ m, one of the alignment gratings being used to align in the X-direction and the other to align in the Y-direction.
  • first and the second metal layer indicated herein further metal layers may be present which are electrically insulated from each other at the location of the semiconductor device by means of further dielectric layers.
  • first wide strips and the second wide strips may be interrupted instead of continuous.
  • barrier layers and anti-reflection layers for example TiN or Ti/TiN.
  • the dielectric layers may remain at the location of the alignment grating, whereafter, as a result of the transparency of these layers to light used during aligning, alignment is possible on the surface of the layer provided last, which is an opaque layer, in this case the layer of polysilicon or a metal layer.
  • the silicon body it is also possible for the silicon body to be n-conductivity type and for the source and drain-forming silicon regions to be p- conductivity type.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

Dans un procédé connu de fabrication d'un dispositif à semi-conducteur, notamment d'un circuit intégré, dans un corps de silicium, on dote une surface de ce corps d'une grille d'alignement que l'on forme selon un motif de bandes constituant des parties en relief et en creux adjacentes, et on la dote d'un motif d'oxyde partiellement en retrait, au niveau du dispositif à semi-conducteur, en déposant sur la surface du corps de silicium une couche de masquage d'un matériau antioxydant, présentant des ouvertures au niveau du dispositif à semi-conducteur, et en soumettant le corps de silicium à un traitement d'oxydation. On a considérablement simplifié ce procédé en appliquant le motif d'alignement (7) en même temps que le motif d'oxyde partiellement en retrait (12) du dispositif à semi-conducteur (5). Pour ce faire, on applique la couche de masquage du matériau antioxydant au niveau de l'emplacement du motif d'alignement, lequel se compose de premières bandes larges, totalement dépourvues d'oxyde en retrait, et de secondes bandes larges, formées chacune au moyen d'un sous-motif de bandes relativement étroites d'un matériau antioxydant alternant avec des ouvertures relativement étroites et plus petites que celles se situant au niveau du dispositif à semi-conducteur. Lors du traitement d'oxydation ultérieur, une bande sur deux des deuxièmes bandes larges est dotée d'un motif d'oxyde segmenté, partiellement en retrait (14), et présentant une surface profilée. Les ouvertures relativement étroites possèdent une largeur telle que le motif d'oxyde partiellement en retrait (14) est plus mince, au niveau du motif d'alignement (7), que le motif d'oxyde partiellement en retrait (12) formé en même temps au niveau du dispositif à semi-conducteur (5).
PCT/EP1999/007035 1998-10-20 1999-09-22 Procede de fabrication d'un dispositif a semi-conducteur sur un corps de silicium, une surface de ce corps etant dotee d'une grille d'alignement et d'un motif d'oxyde partiellement en retrait WO2000024057A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2000577712A JP2002528895A (ja) 1998-10-20 1999-09-22 表面に格子と少なくとも部分的に凹部形状のオキサイドパターンとを備えているシリコン基体に半導体装置を製造する方法
EP99948826A EP1046192A1 (fr) 1998-10-20 1999-09-22 Procede de fabrication d'un dispositif a semi-conducteur sur un corps de silicium, une surface de ce corps etant dotee d'une grille d'alignement et d'un motif d'oxyde partiellement en retrait
KR1020007006766A KR20010033319A (ko) 1998-10-20 1999-09-22 격자 및 적어도 일부분 리세스된 산화물 패턴이 제공되는표면을 가지는 실리콘 바디에서 반도체 장치를 제조하는방법

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP98203539 1998-10-20
EP98203539.6 1998-10-20

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WO2000024057A1 true WO2000024057A1 (fr) 2000-04-27

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US (1) US6255189B1 (fr)
EP (1) EP1046192A1 (fr)
JP (1) JP2002528895A (fr)
KR (1) KR20010033319A (fr)
TW (1) TW448489B (fr)
WO (1) WO2000024057A1 (fr)

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US6255189B1 (en) 2001-07-03
JP2002528895A (ja) 2002-09-03
EP1046192A1 (fr) 2000-10-25
KR20010033319A (ko) 2001-04-25
TW448489B (en) 2001-08-01

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