WO2000007371A1 - Interface pour systeme de videoconference - Google Patents

Interface pour systeme de videoconference Download PDF

Info

Publication number
WO2000007371A1
WO2000007371A1 PCT/US1999/016995 US9916995W WO0007371A1 WO 2000007371 A1 WO2000007371 A1 WO 2000007371A1 US 9916995 W US9916995 W US 9916995W WO 0007371 A1 WO0007371 A1 WO 0007371A1
Authority
WO
WIPO (PCT)
Prior art keywords
video
circuit
data
receive
input
Prior art date
Application number
PCT/US1999/016995
Other languages
English (en)
Inventor
Douglas L. Jewell
Paul D. Israelsen
David Perkes
Original Assignee
Sorenson Vision, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sorenson Vision, Inc. filed Critical Sorenson Vision, Inc.
Priority to IL14100599A priority Critical patent/IL141005A0/xx
Priority to AU52346/99A priority patent/AU752570B2/en
Priority to KR1020017001288A priority patent/KR20010072118A/ko
Priority to JP2000563070A priority patent/JP2002521979A/ja
Priority to US09/762,074 priority patent/US7075564B1/en
Priority to CA002338195A priority patent/CA2338195C/fr
Priority to EP99937533A priority patent/EP1116384A4/fr
Publication of WO2000007371A1 publication Critical patent/WO2000007371A1/fr
Priority to IL141005A priority patent/IL141005A/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/14—Systems for two-way working
    • H04N7/15—Conference systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/14—Systems for two-way working
    • H04N7/141—Systems for two-way working between two video terminals, e.g. videophone
    • H04N7/148—Interfacing a video terminal to a particular transmission medium, e.g. ISDN

Definitions

  • This invention relates to video conferencing systems and, more specifically, to a system which interfaces with one or more of a plurality of video input and one or more of a plurality of output devices.
  • Video conferencing systems are typically designed for use with one particular type of video input device, such as an NTSC camera ("NTSC” means the North American and Japanese analog video standard), a PAL camera ("PAL” means the European analog video standard), a digital camera, or a high speed serial interface camera (e.g., a Fire Wire or Universal Serial Bus (USB) camera).
  • NTSC North American and Japanese analog video standard
  • PAL PAL means the European analog video standard
  • USB Universal Serial Bus
  • Such systems are also typically designed for use with one particular output device, such as an NTSC or PAL video monitor, a television set, a Liquid Crystal Display (LCD) screen, or a computer monitor.
  • NTSC means the North American and Japanese analog video standard
  • PAL means the European analog video standard
  • USB Universal Serial Bus
  • Such systems are also typically designed for use with one particular output device, such as an NTSC or PAL video monitor, a television set, a Liquid Crystal Display (LCD) screen, or a computer monitor.
  • a video conferencing interface is part of a standards-based video conferencing system with excellent video and audio quality, high compression, and great flexibility, all at a low cost.
  • the interface includes an Application Specific Integrated Circuit (ASIC) that incorporates a unique blend of computation and data path designs implemented in hardware, as well as processing and control developed for flexibility using a standard processor.
  • ASIC Application Specific Integrated Circuit
  • the “hybrid” method of computation and control available in the disclosed system provides an advantage over "single solution” counterparts in which computation and control is implemented in dedicated hardware only.
  • the use of dedicated hardware only leads to relative inflexibility in bit rate control.
  • the “hybrid” method of computation and control in the disclosed system provides and an advantage over counterparts that use a software-programmed processor only, thereby abandoning the speed advantages of a hardware implementation.
  • the disclosed system employs hardware to implement or provide for computation and for a data path to provide for high speed data processing at a much faster rate than could be done in a processor-only environment (i.e., software).
  • a standard software based processor allows for flexibility of control so the system can be made adaptable for several different configurations. However, the result is a slower speed because of the software configuration. To attain higher speeds using hardware, a separate hardware configuration would be needed for each variation needed leading to considerable cost and complexities for implementation.
  • the bit rate at which the system interface processes images so an appropriate balance can be struck between the quality of the images processed, on the one hand, and the speed with which images are processed, on the other hand.
  • rapid motion occurs in the processed images, for example, it is typically desirable to operate at an increased bit rate so that the rapid motion is quickly processed and communicated.
  • the high speed processing negatively impacts image quality.
  • the images to be processed are relatively static from image to image (e.g., frame to frame)
  • a hardware-only implementation such flexibility would have to be hardwired at greater expense, or would simply be unavailable.
  • a software-only implementation flexibility is maintained, but at the expense of reduced processing speed.
  • the present invention employs a "hybrid" approach, heretofore unknown, to secure the benefits of a fixed hardware and a fixed software solution.
  • the ASIC is the key to implementing this hybrid approach.
  • the ASIC provides a hardwired implementation for computation and data movement while also providing the flexibility inherent in processor-based processing and control.
  • the system incorporates a memory to store the video information as it is being compressed and/or displayed.
  • the system also includes memory and Electrically Erasable Programmable Read Only Memory (EEPROM) for instructions and data storage for the processor, audio input and output, and a MOdulator/DEModulator (MODEM) for telephone/network interface.
  • EEPROM Electrically Erasable Programmable Read Only Memory
  • MODEM MOdulator/DEModulator
  • the ASIC also includes several interfaces that are flexible in their function that allow for several different system configurations with minimal modification or cost impact. These interfaces include the video input, the video output, and the high speed serial interface.
  • FIG. 1 is a block diagram depiction of a basic ASIC of the prior art suitable for use in processing video signals;
  • FIG. 2 is a block diagram of the ASIC suitable for use in one form of a video system of the present invention
  • FIG. 3 is is a block diagram of the ASIC suitable for use in another form of a video system of the present invention.
  • FIG. 4 is a block diagram of a high speed serial interface circuit for use with a video system of the present invention
  • FIG. 5. is a block diagram of a video input block of an ASIC used with a video system of the present invention:
  • FIG. 6 is a block diagram of a bus control block of an ASIC used with a video system of the present invention.
  • FIG. 7 is a block diagram of a video output block of an ASIC used with a video system of the present invention.
  • a conventional ASIC 10 may be included on a circuit board 12 .
  • the circuit board 12 includes a memory 14 connected to a Memory Control 30 forming a memory module 15 that functions to retain video signals.
  • Memory 14 may be implemented as a dynamic random access memory (DRAM), a static random access memory (SCRAM), or other suitable memory device architecture known by persons skilled in the art.
  • DRAM dynamic random access memory
  • SCRAM static random access memory
  • the circuit board 12 may also have an optional EEPROM module 16.
  • a separate processor memory module 18 e.g., SCRAM DRAM, etc.
  • an audio input/output (I/O) module 20 connected, for example, to a microphone or speaker
  • a MODEM and/or Network interface e.g. , LAN or local area network interface
  • Video-In circuitry 24 receives digital video signals 26 from a single or selected video signal source.
  • "H.263” is a video compression/decompression standard established by the International Telecommunications Union (ITU).
  • H.263 Encode circuitry 34 directs the Memory Control circuitry 30 to forward stored digital video data sent to it from the video memory module 15.
  • the Memory Control circuitry 30 sends the stored video data that it receives out onto and along the memory bus 32.
  • the H.263 Encode circuitry 34 encodes (i.e., compresses) the stored digital video data, it passes the now encoded digital video data to a MODEM or a Network module 22 for transmission to a remote station (not shown) at which location the digital video data may be decoded and subsequently displayed for viewing by a user.
  • the remote station may include the inventive video conferencing interface described herein, or it may be a conventional video conferencing system interface.
  • Encoded digital video data is transmitted by and also received from the remote station or another station through the MODEM or the Network 22.
  • the MODEM or the Network 22 transmit and receive data. If a MODEM is used, the signal is modulated and or demodulated and transmitted over an appropriate line such a telephone line or any equivalent thereof. Alternately, it may be transmitted through a network wiring arrangement which is configured to provide video signal transmission.
  • the data received from the remote location through a MODEM, a network or what ever else may be extant, is transferred through the Processor circuitry 40 to the Bus Control circuitry 36.
  • the Bus Control Circuitry 36 passes the data over the data bus 38 to H.263 Decode circuitry 42 for decoding.
  • the H.263 Decode circuitry 42 forwards the decoded digital video data to the Memory Control circuitry 30 over the memory bus 32 for storage in the DRAM 14.
  • Video Out circuitry 44 then directs the Memory Control circuitry 30 to retrieve the stored digital video data from the DRAM 14 for output by the Video Out circuitry 44 in digital form for display by a selected video display device (not shown) connected to receive the video signal from the Video Out Circuitry 44.
  • serial digital video data or serial control signals from an attached computer system, can be input or output through high speed serial interface circuitry 46, as will be described in more detail below.
  • Support circuitry 48 and performs certain "housekeeping" and control functions.
  • the Support circuitry 48 interacts with the EEPROM module 16 via a well- known I 2 C bus 50, handling interrupt signals, INT, and reset signals, RST, and programming an array of programmable I/O pins, PIO (not shown).
  • the EEPROM module 16 may be used to store machine code for the operation of the Processor circuitry 40. At start-up, the machine code can be transferred from the relatively slow EEPROM module 16 to the relatively fast processor memory device 18 for use by the Processor circuitry 40 during normal operations.
  • the system of the present invention shown in FIG. 2 incorporates a plurality of video input options supplied by video input means 11 the output of which is supplied as the input video signal 26.
  • the input means 11 is here shown to include two or more sources of video signals.
  • the sources illustrated include an Internal Digital Camera 52, an Internal NTSC or PAL video camera 56, an External NTSC or PAL video Camera 58.
  • Input may also be had from an External High Speed Serial Camera 60.
  • the High Speed Serial Camera 60 can be incorporated into the input means 11 or positioned separately to supply an input signal to the data bus 38.
  • An “internal” camera 52 is a camera in which the lens and interface control are mounted inside the system enclosure, while an “external” camera interfaces through a connector which may be the video decoder 54.
  • the digital video signals 26 can be generated by the internal digital camera 52, or by the Video Decoder module 54 converting analog NTSC or PAL signals from the internal NTSC or PAL camera 56 or the external NTSC or PAL camera 58 to the digital video signals 26.
  • a digital camera 60 having a high speed serial output such as a Fire Wire or USB port, can output serial digital video signals to the high speed serial interface 46 for further processing and transmission to the data bus 38.
  • the ASIC 10 of FIG. 2 is configured to have a memory means 15 that includes the DRAM 14 and the memory control 30.
  • Memory control circuitry 30 transfers the digital video signals 26 from a memory bus 32 to the DRAM 14 for storage and also to the H.263 encode module 34 for compression prior to processing by the video processing means 35.
  • the video processing means 35 includes the Processor 40 as well as the support circuit 48 and the bus control 36. It also includes the processor Memory 18 and the EEPROM 16 if provided.
  • the video processing means 35 and more specifically the Processor circuitry 40 directs the encoded digital video data to the remote interface circuit 19.
  • the remote interface circuit 19 is any suitable circuit to transmit and receive video conferencing signals to and from a remote source. That is, the remote interface circuit 19 is configured to receive video signals and preferably voice signals from a remote source to effect what may be referred to as video conferencing.
  • the outgoing video signals as well as audio signals are sent to a remote location which ideally is returning similar video signals and audio signals for processing by the ASIC and for presentation as a video signal on a selected video display or output device.
  • the remote interface means 19 is here illustrated to include the MODEM 22 and Audio circuit 20.
  • the ASIC 10 of FIG. 2 has all the other processing circuitry of FIG. 1 as shown in FIG. 2 while at the same time differing significantly in that a plurality of video input arrangements can be accepted from the video input means 11 using a combination of software and hardware to facilitate speed in processing and flexibility.
  • the system of the present invention in another embodiment depicted in FIG. 3 may also integrate one of several video output options, including NTSC/PAL 68, a Video Modulator 62, LCD 72, RGB 71, and a remote device connected by conductors 73 through the High Speed Serial Interface 46.
  • the digital video output of the Video Out circuitry 44 can be provided to video output means 43 which is here shown to include a Video Modulator module 62 to convert the digital video output from the video out circuitry 44 to a modulated analog signal 64.
  • the analog signal is then multiplexed by a Cable Multiplexer module 66 for output as a TV channel (e.g., channel "3") to a monitor 68.
  • the digital video output of the Video Out circuitry 44 can be converted by a Video Encoder module 70 to an NTSC or PAL analog format suitable for input to a dedicated port on the monitor 68, or can be converted into an LCD format signal for an LCD screen 72.
  • the Video Encoder module 70 can convert the digital video output from the Video Out circuitry 44 to an RGB signal 71 suitable for direct application to a computer monitor (not shown).
  • the system of the present invention can be configured or modified through the specific use of the High Speed Serial Interface 46 connected to separate video 47 not illustrated in FIG. 3.
  • the video means 47 (FIG. 4), can be used for video input, and/or video output. Additionally, it can be used to connect the system as a peripheral or remote device to another controller.
  • This controller could be, for example, a cable box, a set top box, a personal computer, or any number of general purpose or task specific controller devices. Likewise, this also allows the system to easily be integrated directly into a stand-alone teleconferencing device or video phone.
  • the depicted ASIC 10 has a High Speed Serial Interface circuit 46 (e.g., a Fire Wire or USB port) which outputs serial digital video data 71 to video means 47.
  • the video means 47 may include a controller with modem 74, which then interfaces with the telephone system 76 or a separate monitor such as monitor 68.
  • the Video-In circuitry 24 includes Input Configuration circuitry 78 that receives digital video signals 26, as well as serial digital video data from the data bus 38.
  • Control register circuitry 80 set by the Bus Control circuitry 36 causes the Input Configuration circuitry 78 to select and output either the signals 26 or the data from the data bus 38 in a 4:2:2 YUV format.
  • Pixel Decimation circuitry 82 then reduces the "color" component of the output signal, thereby reducing the data density of the signal, by outputting the signal in a 4:1:1 YUV format. Then, a First-In-First-Out (FIFO) buffer 84 holds the output signal before transferring it to the memory means 15 via memory bus 32.
  • FIFO First-In-First-Out
  • the Bus Control circuitry 36 includes Bone Interface circuitry 86 for receiving data from the data bus 38 (otherwise known as the "backbone") and Processor Interface circuitry 88 which communicates with the Processor circuitry 40 (see Figure 4).
  • Arbitration and Control circuitry 90 selects which Interface circuitry 86 and 88 will be active at any one time, and Host Interface circuitry 92 communicates data internally to and from the selected Interface circuitry 86 or 88. Data from the Host Interface circuitry 92 proceeds to Data Interface Control circuitry 94, while register information proceeds to Register Interface Control circuitry 96.
  • Both of the circuitry 94 and 96 communicate with Third Party Module circuitry 98, such as Fire Wire or USB serial -to-parallel circuitry.
  • Video Out circuitry 44 includes Memory Control/Sequencer circuitry 100 that directs the Memory Control circuitry 30 (see FIG. 7).
  • Line Store circuitry 102 then acts as a buffer for storing the video data until two video lines of data are stored.
  • Interpolator circuitry 104 then reverses the actions of the Pixel Decimation circuitry 82 (see Figure 5) by interpolating between each two lines of video data it receives to generate a 4:2:2 YUV signal.
  • a storage FIFO buffer 106 then stores the interpolated video data, and Control Registers circuitry 108 controlled by the Bus Control circuitry 36 (see Figure 1) then causes Encoder Control circuitry 110 to output the stored video data, or not, as the situation may dictate.
  • the stored video data is provided on the data bus 38 to the Bus Control circuitry 36 ( Figure 1) for use by the High Speed Serial Interface circuitry 46 (see Figure 1).
  • FIGS. 2 or 3 can be easily and inexpensively configured as several different devices including, but not limited to: a PC peripheral for camera or video conferencing; a cable box peripheral for camera or video conferencing; and a remote camera for surveillance systems.
  • the system that includes the circuit of FIGS. 2 or 3 can be integrated into or tightly coupled with other hardware to create other devices including, but not limited to, a set top box video conferencing system; a cable box video conferencing system; and a video phone.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Facsimiles In General (AREA)

Abstract

La présente invention concerne un circuit de vidéoconférence (12) configuré pour recevoir un signal (26) à partir d'un dispositif vidéo d'entrée pris parmi une pluralité de tels dispositifs. Ce signal vidéo est ensuite stocké, compressé et transmis par un interface tel qu'un modem (18). Les signaux vidéos de provenance lointaine sont reçus par un modem (18), décompressés, stockés, puis transférés pour affichage sur un dispositif vidéo de sortie pris parmi une pluralité de tels dispositifs.
PCT/US1999/016995 1998-07-30 1999-07-27 Interface pour systeme de videoconference WO2000007371A1 (fr)

Priority Applications (8)

Application Number Priority Date Filing Date Title
IL14100599A IL141005A0 (en) 1998-07-30 1999-07-27 Video conferencing interface
AU52346/99A AU752570B2 (en) 1998-07-30 1999-07-27 Video conferencing interface
KR1020017001288A KR20010072118A (ko) 1998-07-30 1999-07-27 비디오 회의 인터페이스
JP2000563070A JP2002521979A (ja) 1998-07-30 1999-07-27 テレビ会議インタフェース
US09/762,074 US7075564B1 (en) 1998-07-30 1999-07-27 Video conferencing interface
CA002338195A CA2338195C (fr) 1998-07-30 1999-07-27 Interface pour systeme de videoconference
EP99937533A EP1116384A4 (fr) 1998-07-30 1999-07-27 Interface pour systeme de videoconference
IL141005A IL141005A (en) 1998-07-30 2001-01-22 Interface for Contractual Conference

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US9464698P 1998-07-30 1998-07-30
US60/094,646 1998-07-30

Publications (1)

Publication Number Publication Date
WO2000007371A1 true WO2000007371A1 (fr) 2000-02-10

Family

ID=22246341

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1999/016995 WO2000007371A1 (fr) 1998-07-30 1999-07-27 Interface pour systeme de videoconference

Country Status (7)

Country Link
EP (1) EP1116384A4 (fr)
JP (1) JP2002521979A (fr)
KR (1) KR20010072118A (fr)
AU (1) AU752570B2 (fr)
CA (1) CA2338195C (fr)
IL (2) IL141005A0 (fr)
WO (1) WO2000007371A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2380085A (en) * 2001-08-10 2003-03-26 Daili Lu Video/audio communication system
US8208005B2 (en) 2007-07-31 2012-06-26 Hewlett-Packard Development Company, L.P. System and method of determining the identity of a caller in a videoconferencing system

Citations (5)

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Publication number Priority date Publication date Assignee Title
JPH01252087A (ja) * 1988-03-31 1989-10-06 Toshiba Corp テレビ会議システムの画面表示方式
US5539452A (en) * 1990-02-21 1996-07-23 Alkanox Corporation Video telephone system
US5825408A (en) * 1993-03-31 1998-10-20 Casio Computer Co., Ltd. Portable compact imaging and displaying apparatus
US5926208A (en) * 1992-02-19 1999-07-20 Noonen; Michael Video compression and decompression arrangement having reconfigurable camera and low-bandwidth transmission capability
US5949474A (en) * 1997-12-31 1999-09-07 At&T Corp Videophone blocker

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JPH05191802A (ja) * 1991-02-19 1993-07-30 Nippon Steel Corp 集積回路およびそれを使用した画像伝送方法
US5457780A (en) * 1991-04-17 1995-10-10 Shaw; Venson M. System for producing a video-instruction set utilizing a real-time frame differential bit map and microblock subimages
FR2687884B1 (fr) * 1992-02-24 1994-04-08 Alcatel Cit Codec videc, notamment visiophonique.
US5802281A (en) * 1994-09-07 1998-09-01 Rsi Systems, Inc. Peripheral audio/video communication system that interfaces with a host computer and determines format of coded audio/video signals
DE59601149D1 (de) * 1995-04-13 1999-02-25 Siemens Ag Verfahren und einrichtung zum speichern, suchen und abspielen von audiovisuellen informationen und datenfiles

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01252087A (ja) * 1988-03-31 1989-10-06 Toshiba Corp テレビ会議システムの画面表示方式
US5539452A (en) * 1990-02-21 1996-07-23 Alkanox Corporation Video telephone system
US5926208A (en) * 1992-02-19 1999-07-20 Noonen; Michael Video compression and decompression arrangement having reconfigurable camera and low-bandwidth transmission capability
US5825408A (en) * 1993-03-31 1998-10-20 Casio Computer Co., Ltd. Portable compact imaging and displaying apparatus
US5949474A (en) * 1997-12-31 1999-09-07 At&T Corp Videophone blocker

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1116384A4 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2380085A (en) * 2001-08-10 2003-03-26 Daili Lu Video/audio communication system
US8208005B2 (en) 2007-07-31 2012-06-26 Hewlett-Packard Development Company, L.P. System and method of determining the identity of a caller in a videoconferencing system

Also Published As

Publication number Publication date
KR20010072118A (ko) 2001-07-31
CA2338195C (fr) 2008-11-04
IL141005A0 (en) 2002-02-10
EP1116384A4 (fr) 2004-08-18
AU5234699A (en) 2000-02-21
CA2338195A1 (fr) 2000-02-10
EP1116384A1 (fr) 2001-07-18
JP2002521979A (ja) 2002-07-16
IL141005A (en) 2006-07-05
AU752570B2 (en) 2002-09-26

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