WO1999027646A1 - Dispositif a circuit amplificateur a haute frequence et systeme de transmission a haute frequence comprenant ce dispositif - Google Patents

Dispositif a circuit amplificateur a haute frequence et systeme de transmission a haute frequence comprenant ce dispositif Download PDF

Info

Publication number
WO1999027646A1
WO1999027646A1 PCT/JP1997/004248 JP9704248W WO9927646A1 WO 1999027646 A1 WO1999027646 A1 WO 1999027646A1 JP 9704248 W JP9704248 W JP 9704248W WO 9927646 A1 WO9927646 A1 WO 9927646A1
Authority
WO
WIPO (PCT)
Prior art keywords
output
input
electrode
side ground
power transistor
Prior art date
Application number
PCT/JP1997/004248
Other languages
English (en)
Japanese (ja)
Inventor
Kozo Sakamoto
Mineo Katsueda
Isao Yoshida
Masao Hotta
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP1997/004248 priority Critical patent/WO1999027646A1/fr
Publication of WO1999027646A1 publication Critical patent/WO1999027646A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/60—Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators
    • H03F3/601—Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators using FET's, e.g. GaAs FET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6611—Wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6644—Packaging aspects of high-frequency amplifiers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48101—Connecting bonding areas at the same height, e.g. horizontal bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Definitions

  • the present invention relates to a high-frequency amplifier circuit device used for a mobile wireless device such as a mobile phone, and a high-frequency transmission system configured using the same, which is suitable for increasing power and improving efficiency.
  • the gate width Wg of the power MOS FET is generally increased in order to increase the power.
  • the gate width of the power MOS FET used in the high-frequency amplifier circuit device that constitutes this high-frequency transmission system It is empirically known that the saturation output does not increase in proportion to the increase in Wg.
  • the power MOS FET transistor
  • a capacitor is added in order to reduce the increase in the area of the strip line used for matching due to this parallelism.
  • Japanese Patent Application Laid-Open No. 8-172306 discloses a high-frequency power module that is reduced in size by employing a configuration in which a strip line shorter than the wavelength is used for matching.
  • the effective transconductance gm of the transistor is gm as the original transconductance.
  • Gm gm due to the presence of the source impedance (emitter impedance in the case of a bipolar transistor) Zs. / (l + gm. 'Z s), and the source inductance (emitter inductance in the case of a bipolar transistor) L s is 2 rf ⁇ L s source impedance at operating frequency f.
  • FIG. 2 shows a high-frequency transmission system composed of a conventional high-frequency amplifier circuit device using high-frequency power MOS FET.
  • reference numeral 10 denotes a high-frequency power MOSFET
  • reference numeral 300 denotes an equivalent input signal source
  • reference numeral 210 denotes a battery
  • reference numeral 210 denotes an antenna
  • reference numeral 304 denotes a drain impedance
  • reference numeral 303 denotes a battery impedance.
  • the strip line connected to the positive terminal is designed so that the impedance when viewing the battery from node 9b is infinite.
  • Reference numeral 305 denotes an output circuit including a load-side strip line and a filter (a filter is unnecessary depending on the output circuit).
  • the negative terminal of battery 2 18 is connected to ground 4.
  • 301 is the source impedance.
  • the small-signal gate current Ig flows through the equivalent small-signal input voltage source 300, the small-signal voltage applied between the gate 8 and the source 7 of the power MOSFET 10 and the power M 0 SFET 10 A small signal drain current Id, which is determined by the product of the conductance, flows.
  • the source impedance 3 ⁇ 1 exists, the voltage applied between the gate and source of the power MOSFET 10 decreases by the voltage determined by the product of the small signal drain current Id and the source impedance 301. . For this reason, the effective transconductance g m of the power M O S F E T 10 decreases.
  • the back electrode of the semiconductor chip is not used without using a source bonding wire to reduce the source impedance.
  • the conductor in the semiconductor region from the source diffusion layer on the main surface of the semiconductor chip to the back electrode (source electrode) of the semiconductor chip and the package from the ground 2 and 4 to the package are The conductor becomes the above-mentioned source impedance 301, causing a reduction in the effective transconductance of the high-frequency amplifier circuit device, and eventually causing a saturation of the maximum output transmitted from the antenna 216 of the high-frequency transmission system.
  • the reason for increasing the power by paralleling the power MOSFETs as in the above-mentioned conventional example is that when designing a high-output high-frequency amplifier circuit with a level of 0.5 W or more, a gate of power M ⁇ SFET is required. This is because even if the width Wg is increased, there is an output saturation phenomenon in which the output does not increase in proportion to this.
  • one of the causes of this output saturation phenomenon is a quantitative study of the effect of the inductance of the connection between the ground of the power transistor (source for FET and emitter for bipolar transistor) and the ground of the matching stripline. Has never been done. Furthermore, no concrete method for fundamentally solving the above output saturation phenomenon has been proposed.
  • the transconductance gin, of the MOS FET 10 is the transconductance gm when there is no source impedance. And can be expressed by the following equation. Where Rs is the source resistance and Ls is the source inductance.
  • the transconductance gm of the high-frequency power MOS FET 10. Is 3.5 S, source impedance Z s is 50 pH, source inductance L s and 6 m If the source resistance R s is ⁇ , the source resistance R s component can be ignored when the frequency f is about 0.5 GHz or more.
  • the source impedance Z s is 314 ⁇ , and the transconductance gm! Is the transconductance gm without source impedance.
  • a first object of the present invention is to provide a high-frequency amplifier circuit device capable of solving the output saturation phenomenon of a power transistor and achieving high output and high efficiency, and a high-frequency transmission system using the same. .
  • a second object of the present invention is to provide a high-frequency amplifier circuit device that can be reduced in size and a high-frequency transmission system using the same.
  • a third object of the present invention is to optimize source (emitter) impedance.
  • An object of the present invention is to provide a high-frequency amplifier circuit device capable of further improving linear characteristics and preventing oscillation, and a high-frequency transmission system using the same.
  • a high frequency amplifier circuit device includes a power transistor, an input signal electrode and an output signal electrode of the power transistor provided on a semiconductor chip, and further includes an input side ground electrode and an output At least one of the input side ground electrode and the output side ground electrode is provided on the semiconductor chip, and the input side strip line and the output side are provided as a matching circuit of the power transistor.
  • a strip line is provided, and the input-side duland electrode is connected to the input-side ground of the input-side strip line, and the output-side ground electrode is connected to the output-side duland of the output-side strip line.
  • An input signal applied between the input signal electrode and the input side dandand causes the output signal electrode and the output side Land to generate an output signal between the one in which the voltage difference between the input-side ground and the output side ground is characterized in structure in which permissible to vary the output current of the power transistor.
  • a high-frequency amplifier circuit device provides a power transistor, an input signal electrode and an output signal electrode of the power transistor on a semiconductor chip, an input-side ground electrode and an output-side ground electrode, and At least one of the output-side ground electrode and the output-side ground electrode is provided on the semiconductor chip, the input-side ground electrode and the input-side ground are connected, and the output-side ground electrode and the output-side ground are connected to each other.
  • An output signal is generated between the output signal electrode and the output side ground by an input signal applied between the input signal electrode and the input side ground, and the input side ground and the output side
  • a current path for electrically connecting the ground is connected via a ground electrode formed on the semiconductor chip. It may be configured to allow the voltage difference between the ground and said output-side ground is changed by the output current of the power transistor.
  • the high-frequency amplifier circuit device has a power An input signal electrode and an output signal electrode of the power transistor; a back electrode on the back surface of the semiconductor chip; and an electrode pad on a main surface of the semiconductor chip. Either one is used as an input-side ground electrode, and the other is used as an output-side ground electrode.
  • An input-side strip line and an output-side strip line are provided as a matching circuit for the power transistor, and the input-side duland electrode and the input-side strip are provided. Connecting the input side ground to the input side ground, connecting the output side duland electrode to the output side duland of the output side strip line, and applying an input signal applied between the input signal electrode and the input side duland.
  • Generating an output signal between the output signal electrode and the output side ground May be the voltage difference between the de-and the output-side ground is configured to vary the output current of the power transistor.
  • the high-frequency amplifier circuit device further includes a power transistor, an input signal electrode, an output signal electrode, and a ground electrode of the power transistor provided on the semiconductor chip, wherein at least the ground electrode of the semiconductor chip is provided.
  • Two conductive layers and at least one dielectric are alternately laminated on a semiconductor package, and a conductive through hole penetrating through the dielectric for electrical connection of the conductive layers is provided. The conductive layer closer to (or farther from) the ground electrode of the semiconductor chip is connected to the input duland, and the conductive layer farther (or closer) from the duland electrode of the semiconductor chip is output.
  • the output signal electrode and the output side electrode are connected to the input signal electrode and the input side ground by an input signal applied between the input signal electrode and the input side ground.
  • An output signal may be generated between the power transistor and the land, and a voltage difference between the input-side ground and the output-side ground may be allowed to be changed by an output current of the power transistor.
  • the high-frequency amplifier circuit device includes a power transformer on a semiconductor chip. And an input signal electrode and an output signal electrode of the power transistor. Two input signals applied between the input signal electrode and the input-side ground are output from a differential output circuit based on the output durand. A signal is generated based on a signal, and the difference between the two input signals applied between the input signal electrode and the input-side duland is subjected to power amplification by the transistor, and the output signal electrode and the output are output. An output signal may be generated between the input-side ground and the output-side ground to allow a voltage difference between the input-side ground and the output-side ground to be changed by the output current of the power transistor.
  • a power transistor, an input signal electrode and an output signal electrode of the power transistor are provided on a semiconductor chip, and the power transistor is applied between the input signal electrode and an input-side ground.
  • the two input signals are subjected to power amplification by the power transistor to generate an output signal between the output signal electrode and the output side ground, and the output generated between the output signal electrode and the output side ground.
  • a signal is generated, and a difference between the output signal generated between the output signal electrode and the output side ground is converted into an output signal based on the input side ground by a differential circuit, and the second output signal is converted.
  • the power transistor may be configured to allow the voltage difference between the input-side ground and the output-side ground to be changed by the output current of the power transistor.
  • the high-frequency amplifier circuit device is provided with a power transistor, an input signal electrode and an output signal electrode of the power transistor on a semiconductor chip, and a voltage applied between the input signal electrode and an input-side ground.
  • the two input signals are input to a transformer and converted into an output signal based on the output side ground, and the difference between the two input signals applied between the input signal electrode and the input side ground is determined by the power transistor.
  • the power transistor is a power MOSFET.
  • the high-frequency transmission system according to the present invention is characterized in that an audio signal that has been power-amplified using a power amplifier that receives a two-line input signal and generates a one-line output signal is output from an antenna. is there.
  • the high-frequency transmission system may have a configuration in which an audio signal that is power-amplified using a power amplifier that receives a one-wire input signal and generates a two-wire output signal is output from an antenna.
  • FIG. 1 is a circuit diagram showing a first embodiment of a high-frequency transmission system constituted by a high-frequency amplifier circuit device according to the present invention.
  • FIG. 2 is a circuit diagram showing a high-frequency transmission system configured with a conventional high-frequency amplifier circuit device.
  • FIG. 3 shows a second embodiment of a high-frequency transmission system including the high-frequency amplifier circuit device according to the present invention.
  • FIG. 4 is a circuit diagram showing a second embodiment.
  • FIG. 4 is a plan view of the high-frequency amplifier circuit device shown in FIG.
  • FIG. 5 is a cross-sectional view of the high-frequency amplifier circuit device shown in FIG. 4 taken along the line aa ′.
  • FIG. 6 is a cross-sectional view of the high-frequency amplifier circuit device shown in FIG. 4 taken along the line bb ′.
  • FIG. 7 is a plan view of a high-frequency amplifier circuit unit showing a third embodiment of the high-frequency transmission system according to the present invention.
  • FIG. 8 is a cross-sectional view of the high frequency amplifier circuit device portion shown in FIG. 7 taken along the line aa ′.
  • FIG. 9 is a plan view of a high-frequency amplification circuit device showing a high-frequency transmission system according to a fourth embodiment of the present invention.
  • FIG. 10 is a sectional view of the high-frequency amplifier circuit device shown in FIG.
  • FIG. 11 is a circuit diagram of a high-frequency amplifier circuit device showing a fifth embodiment of the high-frequency transmission system according to the present invention.
  • FIG. 12 is a circuit diagram of a high-frequency amplifier circuit device showing a sixth embodiment of the high-frequency transmission system according to the present invention.
  • FIG. 13 is a plan view of the high-frequency amplifier circuit device shown in FIG.
  • FIG. 14 is a cross-sectional view of the high-frequency amplifier circuit device shown in FIG. 13 along the line bb ′.
  • FIG. 15 is a circuit diagram of a high-frequency amplifier circuit device showing a seventh embodiment of the high-frequency transmission system according to the present invention.
  • FIG. 16 is a circuit diagram of a high-frequency amplifier circuit device showing an eighth embodiment of the high-frequency transmission system according to the present invention.
  • FIG. 17 is a circuit diagram of a high-frequency amplifier circuit device showing a ninth embodiment of the high-frequency transmission system according to the present invention.
  • FIG. 18 is a circuit diagram showing a tenth embodiment of the high-frequency transmission system according to the present invention.
  • FIG. 1 is a circuit diagram showing a first embodiment of a high-frequency transmission system including a high-frequency amplifier circuit device according to the present invention.
  • the same components as those of the conventional example shown in FIG. 2 are denoted by the same reference numerals for the sake of description, and detailed description thereof will be omitted.
  • the difference from the conventional example shown in FIG. 2 is that the source impedance 310, which contributes to feedback from the output side to the input side, is reduced. Is divided into an input-side source impedance 303 and an output-side source impedance 302. In this embodiment, the output ground 4 of the high-frequency power MOSFET 10 is the ground of the high-frequency transmission system.
  • the first feature of the present invention is that the ground (source) of the high-frequency power MOSFET 10 is separated into an input duland (input source) 2 and an output duland (output source) 4, and the source impedance is input. It is divided into three components: a source impedance 301 that contributes to voltage feedback to the input, a source impedance 302 connected to the output durand, and a source impedance 303 connected to the input ground. That is, the input-side ground (input-side source) 2 and the output-side ground (output-side source) 4 allow the voltage to fluctuate depending on the operating state of the power MOS FET 10.
  • the configuration of the high-frequency amplification circuit device used in the high-frequency transmission system is a two-wire input, one-wire output high-frequency power amplifier circuit configuration.
  • the second feature of the present invention is that by dividing the source impedance so that the source impedance 301 component contributing to voltage feedback to the input is as small as possible, the effective transconductance of the power MOSFET 10 is improved. This is a point that prevented the decline. Therefore, there is an effect that it is possible to realize a high-frequency amplifier circuit device capable of increasing the output and increasing the efficiency in which the output saturation of the power transistor hardly occurs.
  • a third feature of the present invention is that, although the sum of the source impedances usually increases by dividing the source impedance, the source impedances connected to the output side ground 4 and the input side grounds 2 are connected.
  • Source in The point is that the impedance 303 is effectively used as a component of the input side matching circuit and the output side matching circuit, respectively.
  • the parasitic resistance component of the source impedance has the effect of being a loss component, while the inductance component has the effect of reducing the size of the matching circuit.
  • the source impedance 302 connected to the output side ground 4 is the drain side (output side) impedance 304 and the output side circuit 300 including a matching circuit strip line. Can be used as the impedance component. For this reason, it is possible to shorten the strip line of the output side circuit 305.
  • the source impedance 301 component contributing to voltage feedback to the input can be reduced, the value of the source impedance can be increased or decreased to optimize the linear characteristic of the high-frequency transmission system. And the effect of preventing oscillation.
  • FIG. 3 is a circuit diagram showing a second embodiment of the high-frequency transmission system constituted by the high-frequency amplifier circuit device according to the present invention.
  • the input / output circuit unit of the first embodiment shown in FIG. 1 is shown in more detail.
  • FIGS. 4, 5, and 6 show one embodiment of the high-frequency amplifier circuit device shown in FIG. 3, and show how the source impedance fed back to the input can be reduced by using a configuration. Is shown.
  • FIG. 3 the same components as those shown in FIG. 1 of the present invention are denoted by the same reference numerals, and detailed description thereof will be omitted.
  • a strip line 61 and capacitors 52 and 53 are provided as input matching circuits for the input of a high-frequency power MOSFET 10 formed on a semiconductor chip in the high-frequency amplification circuit portion.
  • a strip line 62 and capacitors 54, 55 are provided as matching circuits.
  • the input-side strip line 61 uses the input-side ground 2 as the ground
  • the output-side strip line 62 uses the output-side ground 4 as the ground.
  • the length of the strip line portion branched from the output side strip line 62 and the branch line portion branched to the power supply terminal 6 is adjusted so that it is ideally open for AC.
  • the branched stripline portion extending in the direction of node 5 of the output-side stripline 62 serves as a load of the power MOSFET 10.
  • Capacitors 51 and 56 are coupling capacitors and are provided for transmitting only high-frequency signals.
  • reference numerals 7, 8, and 9 indicate the source, gate, and drain of the power MOSFET 10, respectively, and II, 12, 13, and 15a indicate conductive wiring on the semiconductor chip.
  • 21 a, 22 a, 23 a, and 24 a are electrodes formed on the semiconductor chip.
  • 21 a, 22 a, and 24 a are bonding pads
  • 23 a is a semiconductor chip.
  • the back electrode 14a is a conductor (conductive wire) in the semiconductor chip from the branch point of the conductive wires 13 and 15a to the back electrode 23a, 31a, 32a, 34a Denotes a bonding wire, and 33a denotes a conductive wiring of a package (or module).
  • Fig. 3 and Fig. 1 The correspondence between Fig. 3 and Fig. 1 is as follows. That is, reference numeral 122 in FIG. 3 denotes an input side circuit, and a signal corresponding to the equivalent small signal voltage source 300 in FIG. 1 is applied between the gate node 8 and the input duland 2.
  • the conductive wiring 13 corresponds to the source impedance 301 returned to the input. Also, conductive wires 15a and 3a are connected to input source impedance 303, conductive wires 14a and 33a are connected to output source impedance 302, conductive wires 11 and 31a are connected to output impedance 304, and stripped.
  • FIG. 4 is a plan view of the high-frequency amplifier circuit device according to the present invention.
  • a cross-sectional view taken along line aa ′ and a cross-sectional view taken along line bb ′ are respectively shown. These are shown in FIGS. 5 and 6.
  • a power transistor that is, in the case of the present embodiment, a first MOS FET 10 is formed.
  • input signals gate signals
  • electrode layers 42, bonding wires 32, and gate wires 12 are provided.
  • output signals drain signals
  • electrode layers 41, bonding wires 31, and drain wires 11 are provided. It is provided. Further, as shown in FIG.
  • the semiconductor chip 1 has conductive layers 44, 71b, 72d, 73b, 74d, 75a and the like and dielectrics 81, 82, 83, 84, 8 5 is arranged in a groove formed in a part of a multi-layer package (or multi-layer module) which is laminated alternately.
  • the conductive layers 73c and 74b The connection is made using a second conductor (conductive wiring 33a in FIG. 3) composed of through holes 94b, 95b and the like.
  • the input-side signal line electrode layer 72h is combined with the input-side ground electrode layers 71e and 73b formed between the dielectrics 82 and 83. This forms the input-side strip line.
  • the output-side signal line electrode layer 41 forms an output-side strip line in combination with the output-side ground electrode layer 71a formed with the dielectric 81 interposed therebetween. I have.
  • reference numerals 72c, 72f, 74c and 74f denote output-side signal conductive layers
  • 74d denotes an input-side signal conductive layer.
  • the high-frequency amplifier circuit device of the present embodiment configured as described above includes a back electrode 1 16 of the semiconductor chip 1, that is, a power MOS FET.
  • the input side ground (source) electrode pad 24, ground (source) wiring 14, and bonding wire 34 are newly provided.
  • Through hole 9 lb, 92b, 93b and the conductive layer 44, 72b, the first conductor 34a (Fig. 3) is newly provided, so that the input-side strip line darland (Fig. ) Are connected to the conductive layers 71b and 73b.
  • the source impedance component fed back to the input side is the sum of the conductive layers 13, 14 a and 33 a.
  • the force adding the source impedances 15a and 34a and the source impedance component fed back to the input side can be drastically reduced to only the impedance 13.
  • the impedance 13 is mainly the impedance of the source diffusion layer of the power MOS FET 10 and is very small. Therefore, a decrease in the effective transconductance of the power MOS FET 10 can be prevented. .
  • the output saturation of the power transistor hardly occurs, and a high-frequency transmission system including a high-frequency amplifier circuit device capable of increasing the output and increasing the efficiency can be realized. This has the effect.
  • Conductive wires 12, 32, 15a, and 34a are used as part of the input matching circuit, and conductive wires 11, 31, 31a, 1a, and 33a are used as output matching circuits. Since it can be used effectively as a part, it has the effect of reducing the size of the matching circuit.
  • the source impedance 13 contributing to the voltage feedback to the input can be reduced. Therefore, by optimizing the source impedance by increasing or decreasing the value, the high-frequency transmission with the high-frequency amplifier circuit device can be realized. This has the effect of improving the linear characteristics of the system and preventing oscillation.
  • the back electrode 1 16 of the semiconductor chip 1 is used as the input ground electrode terminal 23 of the power MOS FET 10. 16 may be used as the input duland electrode 24a, and the pad (electrode) 24 formed on the main surface of the semiconductor chip 1 may be used as the output ground electrode 23a. In this case as well, it is possible to increase the output, increase the efficiency, and reduce the size of the high-frequency amplifier circuit device that constitutes the high-frequency transmission system, and it is also possible to improve the linear characteristics and prevent oscillation. Some things remain the same.
  • FIG. 7 is a plan view of a high-frequency amplifier circuit device showing a third embodiment of the high-frequency transmission system according to the present invention.
  • FIG. 8 is a cross-sectional view of a portion taken along line aa ′ shown in FIG. Note that the cross-sectional view of the portion taken along the line bb 'shown in FIG. 7 is omitted because it is the same as that in FIG.
  • This embodiment is an example in which an input ground electrode and an output ground electrode are provided on a semiconductor main surface, and has the same circuit configuration as that shown in FIG. That is, the difference from the first embodiment is that the output side ground electrode 23 a is not the back surface 116 of the semiconductor chip but the bonding pad 23 on the semiconductor main surface, and the electrode layers 71 a and Bonding wire 33 and electrode layers 43, 72a, 74a, etc. and through holes 91a, 92a, 93a, 94a, 95
  • a second conductor made of a or the like (the conductor 33a of the package in FIG. 3) is used.
  • FIGS. 7 and 8 the same components as those shown in FIGS. 4 and 5 of the second embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.
  • a gallium arsenide MES FET or a bipolar transistor that cannot use the main surface of the semiconductor as a source.
  • a power MOS FET 10 whose source is a semiconductor substrate may be used as a power transistor, and an input-side ground electrode 24 and an output-side ground electrode 23 may be provided on a semiconductor main surface.
  • the back electrode 1 16 is used as the second input-side ground electrode or the second output-side ground electrode, and is connected in parallel with the input-side duland electrode 24 or the output-side ground electrode 23.
  • the source impedance can be reduced.
  • the high-frequency transmission system using the high-frequency amplifier circuit device described in the first and second embodiments is used.
  • the stem has the effect of increasing the output, increasing the efficiency and reducing the size, and has the effect of improving the linear characteristics and preventing oscillation.
  • FIG. 9 is a plan view of a high-frequency amplification circuit device showing a high-frequency transmission system according to a fourth embodiment of the present invention.
  • the ground electrodes 23 and 24 are formed on the active region of the power transistor (on the gate in the case of the FET, and on the emitter in the case of the bipolar transistor), whereby the wiring shown in FIG.
  • This is an embodiment in which the source impedance (emitter impedance in the case of a bipolar transistor) component indicated by 13 is reduced.
  • the same components as those shown in FIGS. 4 and 7 are denoted by the same reference numerals, and detailed description thereof will be omitted.
  • FIG. 10 is a cross-sectional view of the active region of the power transistor in the case of the present embodiment.
  • reference numeral 101 denotes a p-type semiconductor substrate
  • 102 denotes a high-concentration p-type buried layer
  • 103 denotes a p-type epitaxial layer having a thickness of about 2 ⁇
  • 104 denotes a p-type epitaxial layer.
  • High-concentration ⁇ -type diffusion layer 105 is a ⁇ -type well, 106 and 111 are insulating layers, 107 is a gate oxide film, 108 is a gate electrode layer using polycrystalline silicon, etc., 1 Reference numeral 09 denotes a low-concentration ⁇ -type diffusion layer for increasing the breakdown voltage, 110 a denotes an ⁇ -type diffusion layer for a source, and 110 b denotes an n-type diffusion layer for a drain.
  • 1 1 2a is the aluminum electrode for the source
  • 1 1 2b is the aluminum electrode for the drain
  • 1 1 3 is the insulating film
  • 1 1 4 is the aluminum electrode for the source
  • 1 1 5 is the protective insulating film
  • 1 1 7 is the The source bonding wire, 116, is a back surface electrode and can be used as an input duland electrode or an output duland electrode.
  • the bonding wires 1 17 (bonding wires 33 and 34 in FIG. 9) of the ground electrode (source electrode) are wired on the active region where the gate electrode and the like of the power MOSFET are arranged. . Therefore, aluminum electrode for source
  • the feature is that the source wiring such as 114, 112a is shortened, and the impedance of wiring 13 in Fig. 3 can be reduced.
  • the reason why the source pad can be formed on the active region as in the present embodiment is that the thickness of the second-layer source aluminum electrode 114 is increased to about 1.5 m or more, and the bonding wire is formed on the active region. This is because the shock when wiring 1 1 7 is reduced.
  • the bonding pad 1 18 on the active area is used as the input-side ground electrode 34a and the output-side ground electrode 33a for connection by the bonding wires and the like shown in FIG.
  • Both the ground side (source) and the output side ground (source) bonding pads 24 and 23 are shown as being formed on the active area of the power transistor 10. However, only one of them is active. Simply forming the other electrode terminal in the region and arranging the other electrode terminal on the semiconductor main surface which is not the active region, or simply using the back electrode of the semiconductor chip 1 has the effect of reducing the impedance of the wiring 13.
  • this embodiment also has the effect of increasing the output, increasing the efficiency, and reducing the size, as well as improving the linear characteristics and oscillating for the same reason as the high-frequency amplifier circuit device constituting the high-frequency transmission system described in the first embodiment. There is an effect that prevention can be achieved.
  • FIG. 11 is a circuit diagram of a high-frequency amplifier circuit device showing a fifth embodiment of the high-frequency transmission system according to the present invention.
  • the output circuit 217 and the antenna 216 shown in FIG. 3 are not shown.
  • the same parts as those shown in FIGS. 1 and 3 are denoted by the same reference numerals. The detailed description is omitted.
  • a three-stage configuration using power MOS FETs 10, 10 a, and 10 b as power transistors increases the number of transistors compared to the circuit configuration shown in Figure 3.
  • wiring 13a, 13b, 12a, 12b, 11a, lib, 17a, 17b, bonding wire 31b, 31c, bonding pad 2 1b, 21c, capacitors 57a, 57b, and striplines 62a, 62b increase.
  • the input side ground 2 and the output side ground 4 are separated so that the source impedance 13 of the power MOSFET 10 is reduced to reduce the mutual conductance.
  • This embodiment is characterized in that wiring 15 a from the source of each of the three power MOS FETs 10, 10 a, and 10 b to the input durand electrode terminal 24 a and the output durand electrode terminal 23 a are provided. This is to prevent the mutual conductance from dropping by separating the wiring 13b, 13a, and 13 to the wiring.
  • the effects of increasing the output, increasing the efficiency, and reducing the size are achieved for the same reason as the high-frequency amplifier circuit device that configures the high-frequency transmission system described in the first embodiment.
  • FIG. 12 is a circuit diagram of a high-frequency amplifier circuit device showing a sixth embodiment of the high-frequency transmission system according to the present invention.
  • FIGS. 13 and 14 show an example of a mounting method for realizing the high-frequency amplifier circuit device shown in FIG. That is, FIG. 13 is a plan view of the high-frequency amplifier circuit device part shown in FIG. 12, and FIG. 14 is a cross-sectional view of the part along the line bb ′ shown in FIG. Also, for convenience of explanation, in FIGS. 12, 13, and 14, the same components as those shown in FIGS. 1, 3, 4, and 6 are denoted by the same reference numerals, and detailed description thereof is given. Detailed description is omitted.
  • the input-side ground electrode and the output-side ground electrode are separated on the chip.
  • the common ground electrode 23a backside electrode 1 16
  • the source impedance is set to the conductive line 13 composed of the source diffusion layer and the source wiring and the semiconductor chip 1 4
  • the ground is divided into two parts to reduce the force that becomes the sum of 4a (only the conductive line 13 when the back electrode 116 is not used) and the impedance due to the package.
  • the first conductor 35 and the second conductor 36 were separated.
  • a semiconductor package or module configured by alternately laminating two or more conductive layers and one or more dielectric layers using the back electrode 1 16 of the power MOSFET 10 as the ground electrode 23 a Located above.
  • a semiconductor through hole 94 b, 95 b or the like penetrating through the dielectric is used.
  • the conductive layer 73 c closer to the ground electrode 1 16 (backside electrode) of the chip 1 is connected to the conductive layer 73 b used as the input side ground 2 in FIG.
  • the characteristic feature is that the conductive layer 75a farther away from the force is connected to the output side ground 4 in FIG.
  • the conductive layer 73 d functions as the first conductor 35 shown in FIG.
  • the conductive layers 73c, 73d, and 73b are distinguished for the sake of explanation, but are not actually cut.
  • the through hole 94b, the conductive layer 74b, and the through hole 95b are used as the second conductor 36 shown in FIG.
  • the source impedance that causes the reduction of the transconductance gm is only the impedance of the source wiring 13 and the substrate 14 a of the semiconductor chip 1.
  • the source impedance that causes the reduction of the transconductance gm is only the impedance of the source wiring 13 and the substrate 14 a of the semiconductor chip 1.
  • the conductive layer 75b which is a part of the input duland, is connected to the output duland 75a, so that the impedance of the through holes 94b, 95b of the package is fed back to the input. It became one dance component (the component of source impedance 301 in Fig. 2), and the source current flowed, causing the transconductance gm to decrease.
  • FIG. 15 is a circuit diagram of a high-frequency amplifier circuit device showing a seventh embodiment of the high-frequency transmission system according to the present invention.
  • the high-frequency amplifier circuit device of the present embodiment is an example in which a signal (two-wire signal) based on the input ground 2 different from the output Darund 4 of the power M ⁇ SFET 10 is used.
  • a specific connection example for generating a signal based on the reference is shown.
  • the output circuit 217 and the antenna 216 shown in FIG. 3 are not shown.
  • the same components as those shown in FIGS. 1 and 3 are denoted by the same reference numerals, and detailed description thereof will be omitted.
  • the output signal of the input circuit 124 is converted into a two-wire input signal of the power mosfet 10 by using the transformer 2 12.
  • the two-line input signal is configured to be power-amplified by the power MISFET 10 and converted to a one-line output signal, and output from the antenna as in the embodiments shown in FIGS. 1 and 3.
  • the high-frequency amplifier circuit device constituting the high-frequency transmission system can have not only a large output, a high efficiency, and a small size but also a special frequency characteristic, This achieves the effect of being able to freely realize the optimal design of the linear characteristics and the desired high-frequency amplifier circuit that does not easily oscillate.
  • the object of the present embodiment can be achieved if the above-described transposition is inserted somewhere in the input circuit of the power transistor. It is also possible to arrange between the input side matching circuit composed of the lip line 61 and the capacitors 52 and 53 and the power M0SFET10. With such a configuration, this embodiment also has the effect of increasing the output, increasing the efficiency, and reducing the size for the same reason as the high-frequency amplifier circuit device described in the first and second embodiments. This has the effect of improving the linear characteristics and preventing oscillation.
  • FIG. 16 is a circuit diagram of a high-frequency amplifier circuit device showing an eighth embodiment of the high-frequency transmission system according to the present invention.
  • the power MOS FET amplifies a two-wire input signal to produce a one-wire output signal.
  • the present embodiment is an example in which a one-line input signal is amplified by a power MOSFET, converted to a two-line output signal, and then converted to a one-line signal before reaching the antenna. is there.
  • a transformer 212 is used as this signal conversion means.
  • the output circuit 2 17 and the antenna 2 16 shown in FIG. 3 are not shown. Also, for convenience of description, in FIG. 16, the same parts as those shown in FIG. 15 are denoted by the same reference numerals, and detailed description thereof will be omitted.
  • the source impedance component that contributes to the feedback from the output side to the input side is only the impedance indicated by the wiring 13, so that the high-frequency transmission system described in the first embodiment and the second embodiment is configured.
  • the high-frequency amplifier circuit device it has the effect of increasing the output, increasing the efficiency, and reducing the size, and has the effect of improving the linear characteristics and preventing oscillation.
  • the purpose of the present embodiment can be achieved if the position of the transformer 2 12 is inserted somewhere in the output circuit of the power MOSFET 10.
  • the strip line 6 2 It can also be placed between the output matching circuit composed of the capacitors 54 and 55 and the power MOSFET 10.
  • the output ground 4 of the power MOS FET 10 is the system duland, so the antenna 2 16 uses the output duland 4 as the duland.
  • the input ground 2 of the power MOSFET 10 is used as the ground of the system, so the antenna 2 16 uses the input ground 2 as the ground.
  • the transformer 2 12 is not necessary, and the two-wire signal may be connected to both ends of the antenna as it is through an output circuit including a filter or the like.
  • FIG. 17 is a circuit diagram of a high-frequency amplifier circuit device showing a ninth embodiment of the high-frequency transmission system according to the present invention.
  • the high-frequency amplifier circuit device according to the present embodiment generates a signal (two-wire signal) based on the input durand 2 different from the output durand 4 of the power MOSFET 10 by a configuration different from that in FIG. It is an example for. That is, in the present embodiment, the output signal of the input circuit 124 is converted to the input signal level of the power MOS FET 10 by using the differential circuit 126.
  • the differential circuit 126 is composed of, for example, resistors 13 1 and 13 2, MOS FETs 10 x and 10 y, a constant current source 220, and a reference voltage 219.
  • the output circuit 217 and the antenna 216 shown in FIG. 3 are not shown.
  • the same components as those shown in FIG. 15 of the seventh embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.
  • this embodiment also has the effect of increasing the output, increasing the efficiency, and reducing the size for the same reason as the high-frequency amplifier circuit device described in the first and second embodiments. Has the effect that the linear characteristics can be improved and oscillation can be prevented.
  • FIG. 18 is a circuit diagram showing a tenth embodiment of the high-frequency transmission system according to the present invention. is there.
  • a description will be given of a wireless device of a digital cellular system called GSM (Global System for Mobile Communications) in the 800/90 OMHz band.
  • GSM Global System for Mobile Communications
  • reference numerals 201 are RF (Redio Frequency) filters, 202 is LNA (Low Noise Amplifier), 203 is RF (Redio Frequency) band S AW (Surface Acoustic Wave) filter, and 204 is high frequency signal Processing device, 205 is a baseband block, 207 is TCXC (Temperature Compensated Cristal Osci 1 lator), 208 is PLL, 206, 209, 210 is VC ⁇ (Voltage Controlled Oscillator), 2 1 1 is buffer, 2 12 is a transformer, 2 13 is a high-frequency power amplifier circuit, 2 14 is a low-pass filter, 2 15 is a switch circuit, 2 16 is an antenna, and 4 is the ground of this wireless device (in this case, the battery Durand is connected).
  • TCXC Tempoture Compensated Cristal Osci 1 lator
  • 208 is PLL
  • 210 Voltage Controlled Oscillator
  • FIG. 15 of the seventh embodiment the ground of the wireless device is used as the high-frequency power amplifier circuit 21 (the ground on the output side of the high-frequency power amplifier circuit 21).
  • Transformers 2 and 12 shown in Fig. 15 are used to receive input signals based on input side ground 2 different from 4.
  • this wireless device By adopting such a configuration, in the case of the present embodiment, as described in the seventh embodiment, there is an effect of increasing the output, increasing the efficiency, and reducing the size of the high-frequency amplifier circuit device constituting the wireless device. In addition, there is an effect that the linear characteristic can be improved and oscillation can be prevented. Therefore, this wireless device also has the effect of increasing the output, increasing the efficiency, and reducing the size, and further has the effect of improving the linear characteristics and preventing oscillation.
  • the present invention has been described above.
  • the present invention is not limited to the above-described embodiment.
  • the silicon transistor but also gallium arsenide can be used as the power transistor.
  • ME SF ET and bipolar transients The same effect can be obtained even with a high-frequency power transistor such as a stereo JFET.
  • the power transistor and the matching circuit have been described as having a cross-sectional structure that can be incorporated in the same package (module). However, only the power transistor is assembled in a package, and a drain (a collector for a bipolar transistor) is provided from the package.
  • a circuit configuration for connecting the input stripline and the output stripline may be used.
  • the high-frequency amplifier circuit device described in the embodiment When the high-frequency amplifier circuit device described in the embodiment is used in a power amplifier circuit of a mobile wireless device such as a mobile phone used in a frequency band of about 0.9 GHz to about 2 GHz, particularly, about 1 W is used. Even with the above high-output circuit, high efficiency can be achieved, and the power amplifier module in which the power transistor and its matching circuit are formed can be miniaturized. Therefore, the performance, size, and cost of mobile radio equipment can be reduced. Has the effect of improving the linear characteristics and preventing oscillation.
  • the present invention is particularly effective in a high frequency field having a frequency of 10 GHz to 0.5 GHz.
  • the strip line length is several mm or more, so that it is necessary to form the matching strip line in a module outside the semiconductor chip on which the power transistor is formed.
  • a high-frequency amplifier circuit device of the present invention that does not reduce the mutual conductance of the power transistor is required.
  • the width of the strip line must be increased to reduce the parasitic resistance,
  • a strip line that cannot be formed on such a power transistor is used, a strip line cannot be formed on a semiconductor chip. That is, when a strip line is formed in a module outside a semiconductor chip, the high-frequency amplifier circuit device of the present invention is effective.
  • the module area can be reduced by increasing the output and reducing the area of the matching circuit. This makes it possible to realize a high-frequency power amplifier circuit device and an high-frequency transmission system using the same, which enable optimal design of linear characteristics and oscillation prevention.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Amplifiers (AREA)
  • Microwave Amplifiers (AREA)

Abstract

Cette invention se rapporte aux dispositifs à circuit amplificateur de puissance à haute fréquence dans lesquels la fréquence de la bande opérationnelle varie de 500 MHz à environ 10 GHz et le niveau de puissance est au moins égal à 0,5 W. Le problème de ces dispositifs est que l'on ne peut accroître le niveau de puissance en proportion de l'accroissement de la largeur de grille d'un transistor de puissance. Outre le fait qu'elle apporte une solution au problème susmentionné, cette invention concerne un dispositif à circuit amplificateur de puissance à haute fréquence ainsi qu'un système de transmission à haute fréquence comprenant ce dispositif. Ce dispositif et ce système sont conçus de manière à réduire l'espace dans le circuit de mise en correspondance, à améliorer la linéarité et à prévenir les oscillations dans un transistor de puissance (10) ainsi que dans un circuit de mise en correspondance entrée/sortie. Les mises à la terre (2) et (4) d'une ligne de type bande côté entrée (61) et d'une ligne de type bande côté sortie (62) sont ainsi séparées l'une de l'autre. Ces mises à la terre (2) et (4) sont connectées respectivement à une électrode de mise à la terre côté entrée (24a) et à une électrode de mise à la terre côté sortie (23a) qui sont disposées sur une puce à semi-conducteur supportant le transistor de puissance (10). Il est ainsi possible de réduire la composante d'impédance de source efficace qui est à l'origine de la détérioration du circuit amplificateur de puissance à haute fréquence en conductivité réciproque.
PCT/JP1997/004248 1997-11-21 1997-11-21 Dispositif a circuit amplificateur a haute frequence et systeme de transmission a haute frequence comprenant ce dispositif WO1999027646A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP1997/004248 WO1999027646A1 (fr) 1997-11-21 1997-11-21 Dispositif a circuit amplificateur a haute frequence et systeme de transmission a haute frequence comprenant ce dispositif

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP1997/004248 WO1999027646A1 (fr) 1997-11-21 1997-11-21 Dispositif a circuit amplificateur a haute frequence et systeme de transmission a haute frequence comprenant ce dispositif

Publications (1)

Publication Number Publication Date
WO1999027646A1 true WO1999027646A1 (fr) 1999-06-03

Family

ID=14181509

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP1997/004248 WO1999027646A1 (fr) 1997-11-21 1997-11-21 Dispositif a circuit amplificateur a haute frequence et systeme de transmission a haute frequence comprenant ce dispositif

Country Status (1)

Country Link
WO (1) WO1999027646A1 (fr)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001050531A1 (fr) * 1999-12-31 2001-07-12 Hei, Inc. Dispositif et procede d'interconnexion
EP1187208A2 (fr) * 2000-08-30 2002-03-13 Hitachi, Ltd. Dispositif semi-conducteur
WO2008114610A1 (fr) * 2007-03-19 2008-09-25 Murata Manufacturing Co., Ltd. Dispositif de circuit haute fréquence, dispositif de circuit actif et dispositif de transmission/réception
US8472278B2 (en) 2010-04-09 2013-06-25 Qualcomm Incorporated Circuits, systems and methods for adjusting clock signals based on measured performance characteristics
JP2016046539A (ja) * 2014-08-19 2016-04-04 富士通株式会社 増幅器
JP2016518783A (ja) * 2013-04-15 2016-06-23 アジャンス スパシャル ユーロペエンヌ 広帯域の包絡線追跡高周波パワー増幅器

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63219210A (ja) * 1987-03-06 1988-09-12 Mitsubishi Electric Corp Ｆｅｔ増幅器
JPH08204472A (ja) * 1995-01-24 1996-08-09 Nec Eng Ltd 高周波増幅回路

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63219210A (ja) * 1987-03-06 1988-09-12 Mitsubishi Electric Corp Ｆｅｔ増幅器
JPH08204472A (ja) * 1995-01-24 1996-08-09 Nec Eng Ltd 高周波増幅回路

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001050531A1 (fr) * 1999-12-31 2001-07-12 Hei, Inc. Dispositif et procede d'interconnexion
US6294966B1 (en) 1999-12-31 2001-09-25 Hei, Inc. Interconnection device
US6838953B2 (en) 1999-12-31 2005-01-04 Hei, Inc. High-frequency interconnection for circuits
EP1187208A2 (fr) * 2000-08-30 2002-03-13 Hitachi, Ltd. Dispositif semi-conducteur
EP1187208A3 (fr) * 2000-08-30 2011-09-07 Hitachi, Ltd. Dispositif semi-conducteur
WO2008114610A1 (fr) * 2007-03-19 2008-09-25 Murata Manufacturing Co., Ltd. Dispositif de circuit haute fréquence, dispositif de circuit actif et dispositif de transmission/réception
US8472278B2 (en) 2010-04-09 2013-06-25 Qualcomm Incorporated Circuits, systems and methods for adjusting clock signals based on measured performance characteristics
JP2016518783A (ja) * 2013-04-15 2016-06-23 アジャンス スパシャル ユーロペエンヌ 広帯域の包絡線追跡高周波パワー増幅器
JP2016046539A (ja) * 2014-08-19 2016-04-04 富士通株式会社 増幅器

Similar Documents

Publication Publication Date Title
CN109818582B (zh) 具有谐波陷波器的宽带功率放大器
US8339204B2 (en) Semiconductor device
US7437129B2 (en) Electric component for communication device and semiconductor device for switching transmission and reception
JP2020027975A (ja) 高周波モジュールおよび通信装置
JP2020027974A (ja) 高周波モジュールおよび通信装置
US9503030B2 (en) Radio frequency power amplifier
EP3694102B1 (fr) Amplificateurs et modules d'amplificateurs comportant des circuits d'embase
KR102584792B1 (ko) 고주파 모듈 및 통신 장치
TWI485837B (zh) 具有多晶片模組結構的高頻電路
KR102543348B1 (ko) 고주파 모듈 및 통신 장치
US20220021404A1 (en) Radio-frequency module and communication device
US20210409062A1 (en) Radio-frequency module and communication device
US20220360230A1 (en) Output-integrated transistor amplifier device packages incorporating internal connections
JP2018085613A (ja) 半導体装置
JP2003115732A (ja) 半導体装置
WO1999027646A1 (fr) Dispositif a circuit amplificateur a haute frequence et systeme de transmission a haute frequence comprenant ce dispositif
US11483023B2 (en) Radio-frequency module and communication device
US11411585B2 (en) Radio-frequency module and communication device
JP3744828B2 (ja) 半導体装置
JP2755250B2 (ja) 半導体集積回路
US6448616B1 (en) Adaptive biasing of RF power transistors
JP2008236354A (ja) 増幅器
US11979117B2 (en) High frequency semiconductor amplifier
US20240162862A1 (en) Amplifier device with low frequency resonance decoupling circuitry
US20220407467A1 (en) Doherty amplifier

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): CN JP KR SG US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
NENP Non-entry into the national phase

Ref country code: KR

122 Ep: pct application non-entry in european phase