WO1999027582A3 - Optimierter randabschluss von halbleiter-bauelementen - Google Patents

Optimierter randabschluss von halbleiter-bauelementen Download PDF

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Publication number
WO1999027582A3
WO1999027582A3 PCT/DE1998/003453 DE9803453W WO9927582A3 WO 1999027582 A3 WO1999027582 A3 WO 1999027582A3 DE 9803453 W DE9803453 W DE 9803453W WO 9927582 A3 WO9927582 A3 WO 9927582A3
Authority
WO
WIPO (PCT)
Prior art keywords
area
met1
metallic
metallic coating
coating
Prior art date
Application number
PCT/DE1998/003453
Other languages
English (en)
French (fr)
Other versions
WO1999027582A2 (de
Inventor
Roland Sittig
Detlef Nagel
Ralf-Ulrich Dudde
Bernd Wagner
Klaus Reimer
Original Assignee
Fraunhofer Ges Forschung
Roland Sittig
Detlef Nagel
Dudde Ralf Ulrich
Bernd Wagner
Klaus Reimer
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fraunhofer Ges Forschung, Roland Sittig, Detlef Nagel, Dudde Ralf Ulrich, Bernd Wagner, Klaus Reimer filed Critical Fraunhofer Ges Forschung
Priority to EP98963372A priority Critical patent/EP1036418A2/de
Priority to DE19881806A priority patent/DE19881806B4/de
Priority to US09/555,040 priority patent/US6426540B1/en
Priority to JP2000522625A priority patent/JP2001524756A/ja
Priority to DE19881806D priority patent/DE19881806D2/de
Publication of WO1999027582A2 publication Critical patent/WO1999027582A2/de
Publication of WO1999027582A3 publication Critical patent/WO1999027582A3/de
Priority to US10/669,024 priority patent/US6956249B2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thyristors (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

Das technische Gebiet der Erfindung ist ein sperrfähiges Halbleiterbauelement, wie IGBT, Thyristor, GTO oder Diode, insbes. Schottkydiode. Im Randbereich einer Anoden-Metallisierung (1, 31) ist ein (im Randbereich direkt) auf dem Substrat (9) des Bauelements fest angeordnetes Isolatorprofil (10a, 10b, 10c, 10d, 11) mit Krümmungsbereich (KB) und Sockelbereich (SB) vorgesehen, welches Isolatorprofil im Krümmungsbereich (KB) eine Oberfläche (OF) aufweist, die flach beginnend stetig stärker gekrümmt nach außen und aufwärts verläuft. Auf der Oberfläche (OF) ist eine der Oberflächenkrümmung direkt folgende, die innere Anoden-Metallisierung seitlich verlängernde Metallisierung (MET1; 30a, 30b, 30c, 30d, 31b) aufgebracht. Das obere ende der gekrümmten Metallisierung (MET1; 30a, 30b...) ist durch den umlaufenden Sockelbereich (SB) des Isolatorprofils (10a,..., 11) von einer diesen umgebenden äußeren Metallisierung (MET2, 3) isolierend so beabstandet, daß ein weitgehend stetiger, Extremwerte vermeidender Feldlinienverlauf zwischen den beiden Metallisierungen (1, 31, MET1; 3, MET2) - bei Anlegen von Sperrspannung oder Blockierspannung zwischen den beabstandeten Metallisierungen - entsteht.
PCT/DE1998/003453 1997-11-24 1998-11-23 Optimierter randabschluss von halbleiter-bauelementen WO1999027582A2 (de)

Priority Applications (6)

Application Number Priority Date Filing Date Title
EP98963372A EP1036418A2 (de) 1997-11-24 1998-11-23 Optimierter randabschluss von halbleiter-bauelementen
DE19881806A DE19881806B4 (de) 1997-11-24 1998-11-23 Optimierter Randabschluss von Halbleiter-Bauelementen
US09/555,040 US6426540B1 (en) 1997-11-24 1998-11-23 Optimized border of semiconductor components
JP2000522625A JP2001524756A (ja) 1997-11-24 1998-11-23 半導体素子の最適化されたエッジ終端部
DE19881806D DE19881806D2 (de) 1997-11-24 1998-11-23 Optimierter Randabschluss von Halbleiter-Bauelementen
US10/669,024 US6956249B2 (en) 1997-11-24 2003-09-23 Termination of semiconductor components

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19752020.0 1997-11-24
DE19752020 1997-11-24

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US09555040 A-371-Of-International 1998-11-23
US10/127,636 Continuation US20020140046A1 (en) 1997-11-24 2002-04-22 Optimized junction termination of semiconductor components

Publications (2)

Publication Number Publication Date
WO1999027582A2 WO1999027582A2 (de) 1999-06-03
WO1999027582A3 true WO1999027582A3 (de) 1999-07-15

Family

ID=7849660

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1998/003453 WO1999027582A2 (de) 1997-11-24 1998-11-23 Optimierter randabschluss von halbleiter-bauelementen

Country Status (5)

Country Link
US (3) US6426540B1 (de)
EP (1) EP1036418A2 (de)
JP (1) JP2001524756A (de)
DE (1) DE19881806D2 (de)
WO (1) WO1999027582A2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001524756A (ja) * 1997-11-24 2001-12-04 フラウンホーファー−ゲゼルシャフト ツル フェルデング デル アンゲヴァンテン フォルシュング エー．ファー． 半導体素子の最適化されたエッジ終端部
US6301051B1 (en) * 2000-04-05 2001-10-09 Rockwell Technologies, Llc High fill-factor microlens array and fabrication method
US7362697B2 (en) 2003-01-09 2008-04-22 International Business Machines Corporation Self-healing chip-to-chip interface
US20060006394A1 (en) * 2004-05-28 2006-01-12 Caracal, Inc. Silicon carbide Schottky diodes and fabrication method
JP5625336B2 (ja) * 2009-11-30 2014-11-19 サンケン電気株式会社 半導体装置
CN102184947A (zh) * 2011-03-15 2011-09-14 上海集成电路研发中心有限公司 一种高压半导体结构及其制备方法
US9196560B2 (en) 2013-10-31 2015-11-24 Infineon Technologies Austria Ag Semiconductor device having a locally reinforced metallization structure and method for manufacturing thereof
CN112701165A (zh) * 2019-10-22 2021-04-23 珠海格力电器股份有限公司 碳化硅二极管及其制备方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0095755A2 (de) * 1982-05-28 1983-12-07 Siemens Aktiengesellschaft Halbleiterbauelement mit Planarstruktur
EP0237844A1 (de) * 1986-03-18 1987-09-23 BBC Brown Boveri AG Verfahren zur Herstellung einer Abdeckschicht für die Halbleitertechnik sowie Verwendung der Abdeckschicht
JPS6338259A (ja) * 1986-08-01 1988-02-18 Fujitsu Ltd 半導体装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3706128A (en) * 1970-06-30 1972-12-19 Varian Associates Surface barrier diode having a hypersensitive n region forming a hypersensitive voltage variable capacitor
DE3219606A1 (de) * 1982-05-25 1983-12-01 Siemens AG, 1000 Berlin und 8000 München Schottky-leistungsdiode
JPS61181414A (ja) 1985-02-07 1986-08-14 松下電器産業株式会社 電動調理器
KR0154702B1 (ko) * 1995-06-09 1998-10-15 김광호 항복전압을 향상시킨 다이오드 제조 방법
DE19535322A1 (de) 1995-09-22 1997-03-27 Siemens Ag Anordnung mit einem pn-Übergang und einer Maßnahme zur Herabsetzung der Gefahr eines Durchbruchs des pn-Übergangs
SE9700156D0 (sv) * 1997-01-21 1997-01-21 Abb Research Ltd Junction termination for Si C Schottky diode
JP2001524756A (ja) * 1997-11-24 2001-12-04 フラウンホーファー−ゲゼルシャフト ツル フェルデング デル アンゲヴァンテン フォルシュング エー．ファー． 半導体素子の最適化されたエッジ終端部

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0095755A2 (de) * 1982-05-28 1983-12-07 Siemens Aktiengesellschaft Halbleiterbauelement mit Planarstruktur
EP0237844A1 (de) * 1986-03-18 1987-09-23 BBC Brown Boveri AG Verfahren zur Herstellung einer Abdeckschicht für die Halbleitertechnik sowie Verwendung der Abdeckschicht
JPS6338259A (ja) * 1986-08-01 1988-02-18 Fujitsu Ltd 半導体装置

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
BRIEGER K -P ET AL: "The contour of an optimal field plate-an analytical approach", IEEE TRANSACTIONS ON ELECTRON DEVICES, MAY 1988, USA, vol. 35, no. 5, ISSN 0018-9383, pages 684 - 688, XP002102106 *
PATENT ABSTRACTS OF JAPAN vol. 012, no. 250 (E - 633) 14 July 1988 (1988-07-14) *
YEARN-IK CHOI ET AL: "Tapered sidewall Schottky diodes with very low taper angles", PROCEEDINGS OF THE 14TH CONFERENCE (1982 INTERNATIONAL) ON SOLID STATE DEVICES, TOKYO, JAPAN, 24-26 AUG. 1982, ISSN 0021-4922, Japanese Journal of Applied Physics, Supplement, 1982, Japan, pages 137 - 140, XP002102107 *

Also Published As

Publication number Publication date
WO1999027582A2 (de) 1999-06-03
US6426540B1 (en) 2002-07-30
JP2001524756A (ja) 2001-12-04
EP1036418A2 (de) 2000-09-20
US20040129993A1 (en) 2004-07-08
US20020140046A1 (en) 2002-10-03
DE19881806D2 (de) 2000-08-24
US6956249B2 (en) 2005-10-18

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