WO1999022319A1 - Procede de calcul du temps de retard de propagation d'un circuit logique - Google Patents

Procede de calcul du temps de retard de propagation d'un circuit logique Download PDF

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Publication number
WO1999022319A1
WO1999022319A1 PCT/JP1997/003927 JP9703927W WO9922319A1 WO 1999022319 A1 WO1999022319 A1 WO 1999022319A1 JP 9703927 W JP9703927 W JP 9703927W WO 9922319 A1 WO9922319 A1 WO 9922319A1
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WO
WIPO (PCT)
Prior art keywords
cell
input terminal
delay time
capacitance
logic circuit
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PCT/JP1997/003927
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English (en)
Japanese (ja)
Inventor
Yohei Akita
Kazuo Yano
Yasuhiko Sasaki
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Hitachi, Ltd.
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Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP1997/003927 priority Critical patent/WO1999022319A1/fr
Publication of WO1999022319A1 publication Critical patent/WO1999022319A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Definitions

  • the present invention relates to a method for calculating a propagation delay time of a logic circuit, a recording medium recording a propagation delay time calculation program, a propagation delay time calculation system, and a method for synthesizing a logic circuit.
  • the “propagation delay time calculation method” described in Japanese Patent Application Laid-Open No. 1-2271869 is based on the method of calculating the rise Z fall time of the signal applied to the input terminal of the cell and the size of the capacitance added to the output terminal of the cell. This method determines the cell propagation delay time.
  • the capacitance applied to the output terminal is the input capacitance and wiring capacitance of the next-stage cell, but the input capacitance is fixed.
  • the "delay simulator” described in Japanese Patent Application Laid-Open No. 2-249070 prepares in advance information about the waveform rounding of the signal output to the output terminal of the cell, and then forms the waveform rounding of the delay time of the next cell. It discloses the method used to assess dependencies.
  • the delay time of a logic circuit is represented by the sum of the delays of the cells that make up the circuit, and the delay of each cell is its own delay (1), load delay (2),
  • the calculation method (11) is used, which is represented by the sum of delay (3) and wiring delay (24).
  • the self-delay (1) is the inherent delay time of the cell
  • the load delay (2) is the cell delay time caused by the load capacitance (4) added to the output end of the cell
  • the slope delay (3) Is the cell delay time caused by the rounding of the signal at the input terminal of the cell, that is, the slope (5).
  • the self-delay is a constant
  • the load delay is a function of the load capacitance added to the output terminal
  • the srobe delay is the waveform distortion of the input terminal (5).
  • a value that is prepared in advance in the delay library (8) for each cell is used [11].
  • the load capacitance of the cell output terminal (4) which determines the magnitude of the load delay, is determined by the capacitance (7) of the input terminal of the cell connected to the next stage. For each type and for each input terminal, a parameter with a fixed value prepared in the capacitance library (9) is used (12).
  • the wiring delay (24) is determined by the wiring length and the wiring shape of the wiring connected to the output terminal of the cell. When only the wiring capacitance component is considered, the wiring capacitance (23) of the wiring is loaded. Calculate the delay time with the same parameters as the capacity.
  • the basic principle is to understand the delay time of the logic circuit.Based on the calculation result of the delay time, the circuit configuration that minimizes the delay time or the delay is kept constant. The process of selecting a circuit configuration that minimizes the area from among multiple candidates is performed.
  • the above-mentioned logic circuit delay time calculation method mainly targets CMOS technology, which is currently the mainstream of synthesis of logic circuits, so this method is accurate when using circuit technologies other than CMOS.
  • the delay time cannot be calculated in some cases.
  • lotus transistor circuits that can reduce the area, power consumption, and delay time compared to CMOS circuits have been receiving attention.
  • Japanese Patent Application Laid-Open No. Hei 7-168874 describes a method for configuring a high-speed, low-power-consumption, small-area circuit using bus transistors.
  • the present inventors calculated the delay time of a logic circuit including a pass transistor circuit by a method based on the above-described conventional model, but found that sufficient accuracy could not be obtained by prior studies by the present inventors. .
  • the capacitance of the input terminal of the cell which is considered to be a constant in the conventional delay time calculation method in the conventional model, is not actually a constant in a cell that includes a pass transistor inside, but rather due to the slope of the input terminal signal. It is due to the change.
  • Figure 11 shows a conceptual diagram of the cross-sectional structure of the M0S transistor and the capacitance between the terminals.
  • the input terminal of the cell is connected only to the gate terminal of the M0S transistor, and only the gate terminal capacitance affects the delay.
  • the gate terminal capacity is defined as a gate terminal and a source terminal, a gate terminal and a drain terminal, a gate terminal and a substrate, and the like. It shows the sum of the capacitance generated between the terminal and all other terminals. This gate terminal capacitance could be regarded as an almost constant value in the delay time calculation.
  • the input terminal capacitance greatly changes depending on the on / off state of the M0S transistor. Because, when the input terminal is connected to the source terminal of M0S, the input terminal capacitance is equal to the source capacitance when M0S is off, but the input terminal capacitance is equal to the source capacitance when M0S is on. This is because the capacitance that affects the delay changes depending on the ON / OFF state of the M0S transistor so that the sum of the drain capacitance and the capacitance of the circuit connected to the drain path is obtained.
  • FIG. 7 shows a pass transistor cell as an example in which the above phenomenon occurs.
  • the CMOS cell (14) shown in Fig. 7 (a) has almost always a constant capacitance because its input terminal (16) is connected only to the gate terminal of the M0S transistor constituting the inside.
  • a highly accurate delay time could be calculated using the conventional propagation delay calculation method.
  • the pass transistor cell (15) shown in Fig. 7 (b) not only the one connected to the gate terminal of the M0S transistor like the input terminal a (17) but also the internal There are also input terminals b (18) and input terminals c (19) of cells connected to the drain terminal of the M0S transistor.
  • the capacitance of the input terminal connected to the drain terminal of such an M0S transistor differs greatly depending on whether the transistor is in a conducting state or a blocking state.
  • the input terminal (18X19) connected to the drain terminal of the bus transistor is switched from low to high or from high to low, the conduction state of the M0S transistor changes at an intermediate stage. Depending on whether the low or low-to-high transition completes instantaneously or changes over time, The capacity looks different.
  • the electric signal to the input terminal has a rounded waveform, that is, a slope (Fig. 17).
  • the slope is an index indicating the magnitude of the rounding of the signal to be propagated, and can be represented by the time at which the signal rises (falls).
  • the magnitude of the slope changes depending on the magnitude of the load to be driven. Therefore, the input terminal of the cell connected to the drain input terminal of the pass transistor as shown in (18) and (19) in Fig. 7 becomes conductive depending on the magnitude of the slope of the waveform input to that input terminal.
  • the capacitance value appears to change because the proportion of time in state Z shutoff changes.
  • Fig. 8 shows how the capacitance of the input terminal b (18) in Fig. 7 (b) changes with the slope.
  • the extent to which the capacitance changes depending on the slope depends on the technology, etc., but the capacitance may fluctuate up to about 10 times depending on the slope.
  • the input capacitance of the input terminal of the cell which was treated as a fixed value in the CMOS circuit that was the mainstream in the past, is changed to the direct input terminal by the source and drain paths of the MOS transistor such as a pass transistor circuit.
  • the input terminal capacitance of the cells changes due to the slope, so it is clear that sufficient accuracy cannot be obtained by delay time calculation using the conventional model. .
  • the present invention is capable of accurately calculating a delay time even in a circuit including a cell such as a bus transistor cell in which an input terminal capacitance changes due to a slope of an applied input signal.
  • the purpose of the present invention is to provide a delay time calculation method in consideration of the above.
  • the delay time from the input terminal to the output terminal of the cell reflects the dependence of the signal applied to the input terminal on the thrower using the mouth-to-mouth delay.
  • the general method used at this time is to consider the magnitude of the load delay of the cell preceding the cell for which the delay time is calculated as an index indicating the magnitude of the input signal's thrower. In the configuration shown in Fig.
  • the load delay of cell 1 becomes the slope of the signal applied to input terminal 2 of cell 2.
  • this method is applied directly to the slope dependence of the input terminal capacitance, inconvenience will occur.
  • the load delay of the preceding cell is determined by the capacitance of the input terminal that is the load.
  • the capacitance of the input terminal is determined by the slope of the applied signal. That is, it is determined by the load delay of the preceding cell.
  • the load delay of the preceding cell is also determined by the capacitance added to the output terminal, that is, the capacitance of the input terminal of the next cell. In other words, the load delay of the preceding cell and the input terminal capacitance cannot be determined unless the other is determined, and circulation occurs.
  • a second object of the present invention is to provide a method for calculating a lobe when considering the lobe dependence of a signal applied to an input terminal.
  • a third object of the present invention is to provide a method for synthesizing a logic circuit including pass transistors by using the delay time calculating method provided by the present invention. Disclosure of the invention In order to achieve the above object, the present invention provides a delay time calculation method that takes into account the dependence of the capacitance of an input terminal on the rounding of an input signal by the following method.
  • the implementation means of the present invention comprises a cell 1 (32), a cell 2 (35) having an input terminal and an output terminal and having a predetermined logic function between the input terminal and the output terminal as shown in FIG. And a logic circuit in which output terminal 1 (31) of cell 1 (32) is connected to input terminal 2 (33) of cell 2 (35) via node 1 (37).
  • the capacity of the input terminal 2 (33) is stored in the storage area 1 (40), and the cell 1 (3
  • Step 2 reads the capacitance of input terminal 2 (33) from storage area 1 (40), and output terminal 1 (32) of cell 1 (32) based on the capacitance of input terminal 2 (33) determined in step 2.
  • Step 4 (46) that reads the delay time from input terminal 1 (30) to output terminal 1 (31) of cell 1 (32) from cell 41 (32) propagates from the input terminal to the output terminal of the cell.
  • step 1 the capacitance of the input terminal 2 (33) is changed to the input terminal 2 (3
  • the index of the transition time of the signal applied to 3) (hereinafter referred to as waveform rounding) is stored in storage area 1 (40) as a function of (5) (42),
  • step 2 by reading the capacitance of the input terminal 2 (33) from the storage area 1 (40) based on the waveform transition (5) of the signal applied to the input terminal 2 (33), 44),
  • the reference capacitance (27) of the input terminal 2 (33) is stored in the storage area 3 (42) of FIG. 9 (60),
  • a step (2-1) (61) of reading out the reference capacity (27) of the input terminal 2 (33) of the cell 2 (35) from the storage area 3 (42); ) Is replaced by the output terminal 1 (31) of the cell 1 (32) when the input terminal of the cell 1 (32) is replaced with a capacitive element having a capacitance equivalent to the reference capacitance (27) read out by the above-mentioned stesa (2-1).
  • Step (2-4) read from storage area 2 (41),
  • the cell read in the step (2-4) from the delay time from the input terminal 1 (30) to the output terminal 1 (31) of the cell 1 (32) read in the step (2-3) Subtract the self-delay from input terminal 1 (30) to output terminal 1 (31) of 1 (32), and add the load capacitance calculated in step (2-2) to output terminal 1 (31). It has a step (2-5) (63) of calculating a delay time (hereinafter called load delay),
  • the load delay of the cell 1 (32) calculated in the step (2-5) is defined as the waveform rounding (5) of the signal applied to the input terminal 2 (33) of the cell 2 (35).
  • This is a propagation delay time calculation method characterized by the following.
  • Fig. 1 shows a delay time calculation method considering the input terminal capacitance that changes due to the rounding of the input signal waveform.
  • Fig. 2 shows the propagation delay time calculation method of the conventional model.
  • Fig. 3 shows the propagation delay time in the embodiment.
  • FIG. 4 shows an example of input and output of a propagation delay time calculation system, and a configuration of a propagation delay time calculation system using a logic circuit propagation delay time calculation method provided by the present invention.
  • Fig. 5 is a library configuration diagram considering the dependence of input terminal capacitance on waveform rounding (the configuration diagram of the library required for the delay time calculation by the logic circuit propagation delay time calculation method provided by the present invention).
  • FIG. 6 is a flow chart of the propagation delay time calculation method considering the dependence of the input terminal capacitance on the waveform
  • Fig. 7 shows that the conventional delay time calculation method enables highly accurate delay time calculation CMOS cells
  • Figure 8 is an example of a pass transistor cell where sufficient accuracy cannot be obtained by the method.
  • Figure 8 shows how the capacitance at input terminal b in Figure 7 (b) changes due to the slope of the signal applied to input terminal b.
  • FIG. 9 is a diagram showing a delay time calculation method for calculating the input terminal capacitance that changes due to the rounding of the input signal using the reference input terminal capacitance
  • FIG. 10 shows the delay of the logic circuit.
  • Figure 11 is a block diagram of the time calculation system. Fig.
  • FIG. 12 is a diagram for explaining the capacity of a transistor
  • Fig. 12 is a diagram for explaining a method of calculating a cell's self-delay
  • Fig. 13 is a diagram for explaining a method of calculating a cell's load delay.
  • FIG. 14 is a diagram for explaining a method of calculating a slope delay of a cell
  • FIG. 15 is a diagram for explaining a method of calculating a reference input terminal capacitance of a cell.
  • FIG. 16 is a diagram for explaining a method of calculating a capacitance slope coefficient of a cell
  • FIG. 17 is a diagram for explaining a slope
  • FIG. 18 is a diagram of an interactive logic circuit propagation delay time meter.
  • Fig. 12 is a diagram for explaining the capacity of a transistor
  • Fig. 12 is a diagram for explaining a method of calculating a cell's self-delay
  • Fig. 13 is a diagram for explaining a method of calculating a cell's
  • Fig. 19 is a diagram showing the flow of delay time calculation using the interactive logic circuit propagation delay time calculation system
  • Fig. 20 is a diagram showing the logic circuit by the logic circuit synthesis system. It is a figure which shows a synthesis
  • This embodiment describes a logic circuit delay time calculation system based on the above-described conventional model and incorporating the input signal dependency of the input terminal capacitance provided by the present invention into the model.
  • the second system is based on hardware with at least a keyboard (70), CPU (71), CRT (72), and magnetic disk unit (73). It is operated by.
  • FIG. 3 shows the calculation method described in the present embodiment, corresponding to FIG. 2 showing the calculation method of the conventional model.
  • the delay time calculation system described in this embodiment includes connection information (21) of cells constituting a logical circuit, a delay library (8) including delay information of each cell, Input the capacitance library (9) containing the capacitance information of the input terminals of the input terminals, calculate their delay times, and output the result.
  • Cell connection information (21), delay library (8), capacity library (1) (9) and the method of calculating the delay time based on them are as follows.
  • connection information is an element that determines the path for performing the delay calculation.
  • connection information information on the length of the wiring connecting the terminals is also included in the connection information, and together with the wiring capacitance and wiring resistance per unit length determined by the manufacturing process, is used as an element in calculating the wiring delay.
  • Figure 5 shows the configuration of the library used for delay time calculation used in this system.
  • the library consists of a delay library (8) with information on delay and a capacitance library (9) with information on capacitance, both of which relate to all cells used in the logic circuit that calculates the delay time. It has the information of.
  • the delay library (8) has the following harameters.
  • the delay library 1 includes the contents of the storage area 2 (41) in FIG.
  • the cell capacity varies with the size of the load capacitance added to the output end of the cell.
  • Load delay is stored as a table of parameters for load capacity.
  • the capacity library (9) has the following parameters.
  • the capacity library 1 includes the contents of the storage area 1 (40) of FIG. 1 and the storage area 3 (42) of FIG.
  • the delay library and the capacity library are created by calculating a target harameter by performing circuit simulation for each cell under specific conditions and combining them. The method is described below. (3 1) Self delay (1)
  • Figure 14 shows the configuration of the circuit that determines the slope delay coefficient.
  • an ideal pulse (applied pulse 1) is applied to the input terminal 1 of cell 1
  • a constant waveform rounding (S 1) occurs.
  • the delay time until a signal is propagated to the output terminal when applying / losing (applied pulse 2) is calculated by circuit simulation. Assuming that the delay time when applying an ideal pulse without waveform distortion is T 1 and the delay time when applying a pulse with waveform distortion S 1 is T 2, the slope delay coefficient s becomes
  • Figure 15 shows the configuration of the circuit for determining the reference input terminal capacitance.
  • a reference cell for calculating the input terminal capacity is determined, and the self-delay and load delay tables of the reference cell are obtained in advance by the method described in (3-1) (3-2).
  • the reference cell is selected from cells that appear frequently in logic circuits that calculate the propagation delay time, such as inverters and NAND cells.
  • Figure 16 shows the configuration of the circuit that determines the capacitance slope coefficient (28).
  • a reference cell for calculating the capacitance slope coefficient (28) is determined, and the reference cell is calculated in advance using the method described in (3-1) and (3-2). Find the delay and load delay tables.
  • N input terminals 1 (2 ⁇ N ⁇ M: M is the maximum number of fanouts determined by the design rules) are connected to the output terminal 0 of the reference cell and the input terminal 1 of the cell 1 for calculating the capacitance slope coefficient (28).
  • the ideal Hals is applied to the input terminal 0 of the reference cell, and the delay time T 1 until the signal propagates to the output terminal 1 of the reference cell is obtained by circuit simulation.
  • the output terminal 0 of the reference cell is calculated by calculating the delay time of the reference cell when the load capacitance of the reference cell is added to T1. Calculate the effective input capacitance C eff per input terminal 1 by finding the load capacitance C added to, and dividing it by N.
  • the self-delay is subtracted from the delay time T1 of the reference cell, and the load delay ⁇ 2 corresponding to the signal slope of the input waveform is calculated. Divide the obtained effective input capacitance C e f f by the reference input terminal capacitance,
  • FIG. 6 shows a flowchart of a system for calculating the delay time of the logic circuit using the parameters shown in FIG.
  • the slope delay is obtained by multiplying the load delay of the (n-1) th cell by the slope delay coefficient of the nth cell. Use the thrower delay coefficient registered in the delay library (8). (50)
  • the self-delay (1) of the n-th cell is obtained from the delay library (8).
  • (51) (4-3) Calculate the waveform rounding (5) at the input terminal of the (nU) th cell.
  • the calculation method using the conventional model for the actual circuit including the bus transistor provided an accuracy of only about 30% error soil for the simulation at the transistor level, but the waveform rounding at the input terminal proposed in the present invention
  • an accuracy of about 5% error soil can be obtained.
  • the delay time calculation of the logic circuit described in the first embodiment is performed.
  • This paper describes an interactive logic circuit propagation delay time calculation system constructed by adding a man-machine interface.
  • This logic circuit propagation delay time calculation system includes, in addition to the logic circuit delay time calculation system described in the first embodiment, an input device for a user to input data necessary for delay time calculation, and a delay time calculation result. And an output device for outputting the same.
  • the configuration of the interactive logic circuit propagation delay time calculation system is shown below. (Fig. 18)
  • the input device consists of input devices such as a keyboard and a mouse, and inputs data necessary for delay time calculation through these devices.
  • the data required for the interval calculation are the connection information of the logic circuit for which the delay time is to be calculated, and the delay library and the capacity library that contain information on the cells used in the logic circuit.
  • the input device is used to notify its location to the interactive logic circuit propagation delay time calculation system, and the existing data is used. Instruct to use.
  • the output device consists of a data output device such as a CRT, printer, plotter, etc., and a data storage device such as a magnetic disk.
  • the interactive delay time calculation system outputs the delay time calculation result to one of these devices at the instruction of the user.
  • the magnetic disk is selected as the output destination of the calculation result, the calculation result is not output in a state that can be directly viewed, and the calculation result is referred to from the magnetic disk using another system. .
  • the interactive logic circuit propagation delay time calculation system includes the logic circuit propagation delay time calculation system described in the first embodiment as a subsystem.
  • the propagation delay time calculation system calculates the propagation delay time of the logic circuit based on the data specified by the input device, and outputs the calculation to the output device according to a user's instruction.
  • the input device inputs data required for delay time calculation.
  • the input data is logic circuit connection information, delay library, and capacity library.
  • the input device indicates to which output device the result of the delay time calculation is to be output.
  • Candidate output devices include CRTs, printers, blotters, and magnetic disks.
  • the spoken logic circuit delay time calculation system activates the logic circuit delay time calculation system, which is a subsystem, and actually calculates the delay time. After that, the calculation result is output to the output device specified by the user.
  • calculation result output by the interactive logic circuit delay time calculation system is read from the output device specified in advance to obtain the delay time calculation result.
  • a logic circuit synthesis system having, as a subsystem, the logic circuit delay time calculation system described in the first embodiment will be described.
  • Main subject A physical circuit synthesis system is a system that generates an optimal circuit based on a specific evaluation criterion from the logic functions to be configured and the cell group that constitutes the components.
  • This logic circuit synthesis system is, in addition to the logic circuit delay time calculation system described in the first embodiment, a logic function input device for defining the logic circuit function, and a logic circuit candidate for realizing the defined logic function. It consists of a logic circuit generation device that generates groups, a cost calculation device that calculates the cost of the circuit based on the delay time calculation results of the logic circuit, and a logic circuit selection device.
  • This device inputs the logical function of the logical circuit to be configured by the logical circuit synthesis system.
  • the logical function is input in the form of a Boolean function or BDD (Binary-Decision-Diagram).
  • the cost is calculated using a function such as (1-4) logic circuit selection device
  • the logic circuit selection device uses a cost calculation device to select an optimal circuit from a given group of circuits. Calculate the cost of the circuits that make up the circuit group, compare their magnitudes, and search for the circuit with the lowest cost to select the optimal circuit.
  • circuits are synthesized according to the following operation flow. (Fig. 20)
  • the logic circuit is determined by calculating the cost of the generated circuit and searching for the one with the smallest cost.
  • an input signal to an input terminal having an input terminal connected to the source / drain path of the M0S transistor is obtained. It is possible to calculate with high accuracy the delay time of a logic circuit including a cell whose input terminal capacitance changes due to the rounding of the waveform, and to make a more accurate determination of the circuit selection in the synthesis of those circuits. Can be.
  • the waveform distortion of the input signal to the input terminal such as having the input terminal connected to the source / drain path of the M0S transistor
  • the delay time of a logic circuit including a cell whose input terminal capacitance changes can be calculated with high accuracy.
  • an input terminal having an input terminal connected to the source / drain path of the M0S transistor can be connected. It is possible to calculate a logic circuit including cells whose input terminal capacitance changes due to the rounding of the input signal waveform based on accurate delay time calculation.

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Abstract

L'invention porte sur un procédé de calcul du temps de retard de propagation d'un circuit logique, ce temps de retard pouvant être calculé avec précision même si la capacité du terminal d'entrée de la cellule du circuit logique varie en fonction du bord arrondi de l'onde forme d'un signal appliqué. Alors que, dans le procédé de calcul traditionnel, on calcule le temps de retard en considérant que la capacité du terminal d'entrée est fixe, selon le procédé de l'invention, on calcule le temps de retard en prenant en compte la variation de capacité du terminal d'entrée dans une banque de retard en fonction du bord arrondi de la forme d'onde. De plus, et selon ce procédé, le temps de retard de chaque solution candidate du circuit logique est utilisé pour un objet comparatif, en tant que base de sélection de la solution optimum à partir d'une pluralité de solutions candidates du circuit logique de façon à obtenir une fonction logique désirée.
PCT/JP1997/003927 1997-10-29 1997-10-29 Procede de calcul du temps de retard de propagation d'un circuit logique WO1999022319A1 (fr)

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PCT/JP1997/003927 WO1999022319A1 (fr) 1997-10-29 1997-10-29 Procede de calcul du temps de retard de propagation d'un circuit logique

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PCT/JP1997/003927 WO1999022319A1 (fr) 1997-10-29 1997-10-29 Procede de calcul du temps de retard de propagation d'un circuit logique

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102306222A (zh) * 2011-08-31 2012-01-04 南通泰慕士服装有限公司 一种浆料用量的计算方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0540801A (ja) * 1991-08-06 1993-02-19 Mitsubishi Electric Corp タイミングシミユレーシヨンシステム

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0540801A (ja) * 1991-08-06 1993-02-19 Mitsubishi Electric Corp タイミングシミユレーシヨンシステム

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
LALGUDI N. KANNAN, "A Methodology and Algorithms for Post-Placement Delay Optimization", 31ST IEEE DESIGN AUTOMATION CONFERENCE, (1994), pages 327-332. *
ROGER S. SHUM, "An Empirical Timing Characterization Method and its Application to CMOS Logic Circuits", MICROELECTRONICS JOURNAL, (1993), pages 477-484. *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102306222A (zh) * 2011-08-31 2012-01-04 南通泰慕士服装有限公司 一种浆料用量的计算方法

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