WO1998057529A1 - Dispositif microfabrique a rapport dimensionnel eleve avec isolation et interconnexions electriques - Google Patents
Dispositif microfabrique a rapport dimensionnel eleve avec isolation et interconnexions electriques Download PDFInfo
- Publication number
- WO1998057529A1 WO1998057529A1 PCT/US1998/012247 US9812247W WO9857529A1 WO 1998057529 A1 WO1998057529 A1 WO 1998057529A1 US 9812247 W US9812247 W US 9812247W WO 9857529 A1 WO9857529 A1 WO 9857529A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- trench
- isolation
- region
- substrate
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
- G01P15/00—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration
- G01P15/02—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses
- G01P15/08—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values
- G01P15/097—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values by vibratory elements
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
- B81C1/00246—Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01C—MEASURING DISTANCES, LEVELS OR BEARINGS; SURVEYING; NAVIGATION; GYROSCOPIC INSTRUMENTS; PHOTOGRAMMETRY OR VIDEOGRAMMETRY
- G01C19/00—Gyroscopes; Turn-sensitive devices using vibrating masses; Turn-sensitive devices without moving masses; Measuring angular rate using gyroscopic effects
- G01C19/56—Turn-sensitive devices using vibrating masses, e.g. vibratory angular rate sensors based on Coriolis forces
- G01C19/5719—Turn-sensitive devices using vibrating masses, e.g. vibratory angular rate sensors based on Coriolis forces using planar vibrating masses driven in a translation vibration along an axis
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
- G01P15/00—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration
- G01P15/02—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses
- G01P15/08—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values
- G01P15/0802—Details
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
- G01P15/00—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration
- G01P15/02—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses
- G01P15/08—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values
- G01P15/0888—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values for indicating angular acceleration
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
- G01P15/00—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration
- G01P15/02—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses
- G01P15/08—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values
- G01P15/125—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values by capacitive pick-up
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2203/00—Basic microelectromechanical structures
- B81B2203/03—Static structures
- B81B2203/0323—Grooves
- B81B2203/033—Trenches
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/07—Integrating an electronic processing unit with a micromechanical structure
- B81C2203/0707—Monolithic integration, i.e. the electronic processing unit is formed on or in the same substrate as the micromechanical structure
- B81C2203/0757—Topology for facilitating the monolithic integration
- B81C2203/0778—Topology for facilitating the monolithic integration not provided for in B81C2203/0764 - B81C2203/0771
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
- G01P15/00—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration
- G01P15/02—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses
- G01P15/08—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values
- G01P2015/0805—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values being provided with a particular type of spring-mass-system for defining the displacement of a seismic mass due to an external acceleration
- G01P2015/0808—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values being provided with a particular type of spring-mass-system for defining the displacement of a seismic mass due to an external acceleration for defining in-plane movement of the mass, i.e. movement of the mass in the plane of the substrate
- G01P2015/0811—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values being provided with a particular type of spring-mass-system for defining the displacement of a seismic mass due to an external acceleration for defining in-plane movement of the mass, i.e. movement of the mass in the plane of the substrate for one single degree of freedom of movement of the mass
- G01P2015/0814—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values being provided with a particular type of spring-mass-system for defining the displacement of a seismic mass due to an external acceleration for defining in-plane movement of the mass, i.e. movement of the mass in the plane of the substrate for one single degree of freedom of movement of the mass for translational movement of the mass, e.g. shuttle type
Definitions
- the present invention relates generally to microfabricated devices, and more particularly to three dimensional microfabricated devices having a high vertical aspect ratio.
- Microelectromechanical systems integrate micromechanical structures and microelectronic circuits on the same silicon chip to create an integrated device.
- MEMS have many useful applications such as microsensors and microactuators .
- An example of a microsensor is a gyroscope used in a missile guidance system.
- An example of a microactuator is a micropositioner used to move a read/write head in a disk drive.
- the device is fabricated by depositing a thin film on a surface.
- the thin film is typically deposited by chemical vapor deposition (CVD) and etched to yield a desired shape.
- a layer of sacrificial material underlying the thin film may be etched to open up passageways or clearances between moving parts of the microstructure.
- the height of the microstructure is limited to the thickness of the deposited thin film. Since the thin film structure has microscopic thickness, on the order of one micron, it tends to be flexible out of the plane of fabrication. In view of the foregoing, there is a need for a way to make taller microstructures (on the order of 10 to 250 microns) .
- the microstructures should have a high vertical aspect ratio; that is, such microstructures should have a height significantly larger than their lateral width.
- the channel between the interdigited electrodes should also have a high vertical aspect ratio.
- the invention is directed to a method of fabricating a microelectromechanical system.
- the method includes providing a substrate having a device layer, etching a first trench in the device layer, depositing a dielectric isolation layer in the first trench, and etching a second trench in the device layer.
- the first trench surrounds a first region of the substrate, and the second trench is located in the first region and defines a microstructure.
- Circuitry may be formed in a second region of the substrate outside the first region, and an electrical connection may be formed over the first trench to connect the microstructure to the circuitry.
- the isolation layer may fill the first trench, or a filler material may be deposited over the isolation layer in the first trench.
- the substrate may include a handle layer, a sacrificial layer and the device layer. A portion of the sacrificial layer may be removed to release the microstructure.
- the sacrificial layer may include silicon dioxide, the device layer may includes epitaxial silicon, and the isolation layer may include silicon nitride.
- the invention is directed to a microfabricated device.
- the device includes a substrate having a device layer and an isolation trench extending through the device layer and surrounding a first region of the substrate.
- the isolation trench includes a lining of a dielectric insulative material.
- a plurality of microstructure elements formed from the device layer are located in the first region and are laterally anchored to the isolation trench.
- Implementations of the invention include the following.
- the lining may fill the isolation trench, or a filler material may be deposited on the lining and fill the trench.
- Circuitry may be formed in a second region of the substrate outside the first region, and an electrical connection may be disposed over the isolation trench to connect at least one of the microstructure elements to the circuitry.
- the substrate may include a handle layer, a sacrificial layer and the device layer. A portion of the sacrificial layer may be removed from the first region to form a gap between the microstructure elements and the handle layer.
- the sacrificial layer may include silicon dioxide, the device layer may include epitaxial silicon, and the lining may include silicon nitride .
- the microstructures are electrically isolated from the microelectronic circuits, but can be electrically connected to the microelectronic circuits by interconnect layers.
- the device may be fabricated utilizing standard microfabrication techniques.
- the invention is compatible with existing very large scale integrated (VLSI) circuit fabrication processes so that microelectronic circuits may be fabricated on the surface of the device.
- the microstructures have a high vertical aspect ratio (on the order of 10:1 to 25:1 or even higher) .
- Microsensors fabricated according the invention have a larger sense capacitance, and thus an increased signal-to-noise ratio, due to the increased surface area between the electrode fingers.
- the microstructures also have a larger mass and a larger moment of inertia, and consequently thermal noise is reduced.
- the high vertical aspect ratio microstructures have a large separation of vibrational modes.
- Figure 1 is a schematic top plan view of a microf bricated device in accordance to the present invention.
- Figure 2 is a cross-sectional view of the device of Figure 1 along lines 2-2.
- Figure 3 is an enlarged and perspective view of the microfabricated device of Figure 1.
- Figures 4, 6-11, 13 and 15 are schematic cross- sectional views.
- Figures 5, 12 and 14 are schematic plan views illustrating steps in the fabrication of the microfabricated device of Figure 1.
- Figures 6, 13 and 15 are cross-sectional views of Figures 5, 12 and 14, respectively, along lines 6-6, 13-13 and 15-15, respectively.
- the scale in the plan views is not the same as the scale in the cross-sectional views.
- Figure 16A is a schematic cross-sectional view illustrating a dry release step for the fabrication process of the present invention.
- Figure 16B is a schematic cross-sectional view illustrating an isolation trench which is entirely filled by the isolation layer.
- Figure 17 is a scanning electron microscope photograph of a microfabricated device fabricated in accordance with the present invention.
- Figure 18 is a scanning electron microscope photograph of a cross-section of an isolation trench.
- Figure 19-25 are scanning electron microscope photographs of devices fabricated in accordance with the present invention.
- microfabricated device 10 in accordance with the present invention.
- the illustrated microfabricated device is a linear accelerometer.
- the principles of the invention are applicable to many other devices, such as vibromotors, angular accelerometers, gyroscopes, resonators, microactuators, icrovalves, filters, and chemical detectors.
- Device 10 includes a circuit region 12 and a structure region 14 formed in a substrate 16. As will be described in more detail below, microstructure elements in structure region 14 are electrically isolated from each other and from circuit region 12 by a filled isolation trench region 18.
- a recess 20 is etched into an upper surface of substrate 16 in structure region.
- Recess 20 contains the various microstructure elements, such as electrodes fingers and plates, flexures, and proof mass beams or bodies, required by device 10.
- the microstructure elements in recess 20 are defined and separated by a channel 28. At least some of the microstructure elements are separated from a handle layer 44 and can move. In addition, because all of the microstructure elements are fabricated from a single device layer 48, the elements are coplanar.
- Device 10 includes a proof mass 24 which is laterally anchored to sidewalls 22 of recess 20 by flexures 26. Flexures 26 are designed to suspend proof mass 24 in recess 20 and to permit proof mass 24 to vibrate along the X-axis parallel to the surface of substrate 16.
- a plurality of stationary electrode fingers 30a and 30b are anchored to and project inwardly along the Y-axis from sidewalls 23 of recess 20.
- a plurality of movable electrode fingers 32 project from proof mass 24 along the Y-axis and are interdigitated with stationary electrode fingers 30a and 30b. Each movable electrode finger 32 is adjacent to one stationary electrode finger 30a and one stationary electrode finger 30b.
- the movable microstructure elements in structure region 14, including proof mass 24, electrode fingers 32 and flexures 26, are separated from the bottom of recess 20 by an air gap 34.
- the air gap 34 may have a width D which is defined by the thickness of a sacrificial layer 46 between device layer 48 and handle layer 44.
- Flexures 26 may have a width W F of about two to six microns. Electrode fingers 30a, 30b and 32 may have a length L of about ten to five-hundred microns and a width W E of about two to six microns. Stationary electrode fingers 30a and 30b may be separated from movable electrode fingers 32 by a gap having a width W g of about one to three microns .
- the microstructure elements in structure region 14 have a thickness T (see Figure 2) .
- the thickness T may be about ten microns to one-hundred microns, with the preferred thickness being determined by the application and desired sensitivity. Even thicker microstructures may be possible as anisotropic etching technology improves.
- the thickness T is much larger than the width W F of flexures 26, the width W p of electrode fingers 30a, 30b and 32, or the width W g of the gap between the stationary and moveable electrode fingers.
- Flexures 26 may have a vertical aspect ratio (a ratio of T to W F ) of at least about 10:1.
- electrode fingers 30a, 30b and 32 may have a vertical aspect ratio (the ratio of T to W E ) of at least 5:1.
- the gap between stationary electrode fingers 30a and 30b and movable electrode fingers 32 may have a vertical aspect ratio (the ratio of T to W G ) of at least 10:1. Vertical aspect ratios of 25:1 may be achieved utilizing current etching techniques.
- the high vertical aspect ratio provides an increased surface area between the electrode fingers, and thus a larger sense capacitance.
- the increased sense capacitance provides an increased signal-to-noise ratio.
- the microstructures also have a larger mass and a larger moment of inertia, and consequently reduced thermal noise.
- the thicker structures are more rigid in the vertical direction and thus less likely to move out of the plane of fabrication.
- the high vertical aspect ratio microstructures have a large separation of vibrational modes due to the significant difference in rigidity of the microstructures in different directions.
- Circuit region 12 contains the necessary integrated circuitry to drive and/or sense the position of proof mass 24. Circuit region 12 is not shown in detail because its circuitry will depend upon the purpose of the device; that is, the circuitry will depend upon whether the device is an angular accelerometer, gyroscope, linear accelerometer, microactuator, etc.
- the microelectronic circuitry may be constructed according to known circuit designs, and thus the content of circuit region 12 is not crucial to the invention.
- circuit region 12 may be fabricated utilizing traditional VLSI processes, such as complementary metal oxide semiconductor (CMOS) processes. As shown in Figure 2, if circuit region 12 is fabricated using CMOS processes, it may include both n-channel transistors 80 and p-channel transistors 82 (not shown in Figure 1 for the reasons discussed above) .
- CMOS complementary metal oxide semiconductor
- the microstructure elements in structure region 14 may be electrically connected to circuit region 12 by conductive electrical interconnections 36 which extend over isolation trench 18.
- the electrical interconnections 36 may be formed of polysilicon or a metal such as aluminum, copper or tungsten.
- the isolation trench 18 separates circuit region 12 from structure region 14. Isolation trench 18 preforms three primary functions. First, isolation trench 18 electrically isolates structure region 14 from circuit region 12. In addition, isolation trench 18 electrically isolates the microstructure elements in structure region 14 from each other. For example, because they project from different portions of the isolation trench, stationary electrodes 30a are electrically isolated from stationary electrodes 30b and from proof mass 24. Second, isolation trench 18 provides a lateral anchoring point for mechanically anchoring the microstructure elements in structure region 14 to substrate 16. Third, isolation trench 18 provides a bridge to support electrical interconnections 36 between the microstructure elements and the circuit region.
- Isolation trench 18 extends entirely through the thickness of device layer 48. Isolation trench 18 may have a width W ⁇ of about two to seven microns. Isolation trench 18 is lined with an isolation layer 64.
- the isolation layer is an insulating dielectric, such as 0.5 microns of silicon nitride. Isolation trench 18 may be back-filled with a filler material such as undoped polysilicon. Alternately, isolation trench 18 may be entirely filled by isolation layer 64, without use of a filler material. Isolation layer 64 may provide the sidewalls 22 of recess 20.
- Fabrication of device 10 comprises three basic steps: formation of isolation trench 18, formation of circuit region 12 and electrical interconnections 36 by VLSI processing, and formation of structure region 14.
- the fabrication process begins with the formation of isolation trench 18 in substrate 16.
- Substrate 16 includes a handle layer 44, a sacrificial layer 46, and a device layer 48.
- the handle layer 44 may comprise a material which bonds to sacrificial layer 46.
- Handle layer 44 may be silicon or another high-temperature substrate, such as quartz.
- Sacrificial layer 46 may be a layer of silicon oxide. Sacrificial layer 46 may have a thickness of between about 0.5 and 2.0 microns, such as 1.0 microns.
- Device layer 48 may include a surface sublayer 50 and an underlying sublayer 52.
- Surface sublayer 50 is a layer of a semiconductor material suitable for VLSI processing.
- Surface sublayer 50 may be formed of epitaxial silicon.
- surface sublayer 50 may be composed of another semiconductor material such as gallium arsenide.
- Surface sublayer 50 may be about five microns thick.
- the dopant levels in surface sublayer 50 may be selected to match a standard VLSI process.
- surface sublayer 50 may be lightly doped with an n-type dopant for compatibility with a CMOS fabrication process .
- Underlying sublayer 52 may be a semiconductor or other material onto which surface sublayer 50 may be grown by an epitaxial process.
- underlying sublayer 52 may be a single-crystal silicon ⁇ 100>- substrate .
- Underlying sublayer 52 may be doped to independently control the electrical properties of the device, such as the resistivity of the microstructure elements in structure region 14. It is advantageous to use antimony as a dopant in underlying sublayer 52 because it minimizes diffusion of the dopant into surface sublayer 50.
- Underlying sublayer 52 may be about forty- five micron thick.
- the thickness of device layer 48 will determine the total thickness T of the microstructure elements in structure region 14.
- the thickness of sacrificial layer 46 will determine the distance D between the microstructure elements and handle layer 44.
- an etch stop or pad oxide layer 54 is next deposited on an upper surface of surface sublayer 50.
- Etch stop layer 54 may be composed of an oxide, such as silicon dioxide, and may be deposited by thermal oxidation.
- Etch stop layer 54 may have a thickness of about 0.18 microns and may be formed on surface sublayer 50 using a wet thermal oxidation step at about 900°C for about fifty minutes.
- etch stop layer 54 is photolithographically defined, and both etch stop layer 54 and device layer 48 are etched to form a trench 60.
- the trench may have a width W ⁇ of about two to seven microns, and a depth equal to the total thickness of device layer 48 and etch stop layer 54, i.e., about forty-five microns.
- the etch of etch stop layer 54 may be performed using a deep anisotropic plasma etch.
- the etch of the etch stop layer may be performed using reactive ion etching (RIE) by flowing the gasses carbon tetraflouride (CF 4 ) , trifluromethane (CHF 3 ) and helium (He) at 90 seem, 30 seem and 120 seem, respectively.
- RIE reactive ion etching
- This etch may be performed at a power of 850 watts and a pressure of 2.8 Torr.
- the device layer 48 may be patterned etched. This etch may be performed using an inductively coupled plasma (ICP) etch.
- ICP inductively coupled plasma
- the so-called "Bosch” process may be used, as this process currently provides state-of-the-art anisotropic silicon etching.
- ICP etching services may be obtained from the Microelectronics Center of North Carolina (MCNC) in Research Triangle Park, North Carolina, or from the Center for Integrated Systems of Stanford University in Palo Alto, California.
- trench 60 surrounds the portion of device layer 48 which will become structure region 14. Although shown as a simple rectangle, trench 60 may have a more complicated shape, and multiple trenches may be formed in the substrate.
- isolation layer 64 is deposited onto substrate 16. Isolation layer 64 covers etch stop layer 54 and lines sidewalls 62 and floor 63 of trench 60 (see Figure 5) .
- the isolation layer 64 is a conformal insulative dielectric, such as silicon nitride. Alternately, isolation layer 64 may be a thermal oxide. Isolation layer 64 may be about 0.26 microns thick.
- a silicon nitride layer may be deposited using low-pressure chemical vapor deposition (LPCVD) with the deposition gasses dichlorosilane (SiH 2 Cl 2 ) and ammonia (NH 3 ) at flow rates of 100 seem and 25 seem, respectively. The deposition may be performed at a pressure of 140 mTorr and a temperature of 835°C.
- a filler material 66 may be deposited to backfill trench 60.
- Filler material 66 is also deposited on isolation layer 64.
- Filler material 66 may be an insulator, semiconductor or conductor.
- the filler material 66 may be undoped polysilicon and may be deposited by CVD using silane (SiH 4 ) at a pressure of 375 mTorr at a temperature of 610°C for about ten hours.
- the thickness of filler material 66 is a function of the width of trench 60. For example, for an LPCVD process, the thickness of the layer of filler material is at least one-half the width of the trench.
- CMP chemical mechanical polishing
- a self-aligned nitride etch is performed next.
- a capping layer 68 is grown on filler material 66.
- Capping layer 68 may be a thermal oxide which grows on the polysilicon of filler material 66 but not on the nitride of isolation layer 64.
- Capping layer 68 may be 0.24 microns thick and may be grown by a wet oxidation process at 900°C for about two hours .
- isolation layer 64 is silicon nitride
- a blanket plasma nitrite etch is used to remove isolation layer 64.
- the blanket plasma nitride etch may be performed with sulfur hexaflouride (SF 6 ) and helium (He) at flow rates of 175 seem and 50 seem, respectively.
- the etch may be performed at a pressure of 375 mTorr and a power of 250 watts .
- isolation trench 18 The dielectric material of isolation layer 64 lining the walls of trench 18 electrically isolates structure region 14 from circuit region 12.
- Substrate 16 may now be subjected to standard VLSI processes to form circuit region 12.
- capping layer 68 and etch stop layer 54 are removed to expose the epitaxial silicon of surface sublayer 50.
- the etch may be performed using a plasma etch with the etching gasses CF 4 , CHF 3 and He at flow rates of 30 seem, 35 seem and 100 seem, respectively.
- the etch may be performed at a power of 700 watts and a pressure of 3.0 Torr.
- circuit region 12 is to be formed on an epitaxial layer using a CMOS process
- surface sublayer 50 is doped in circuit region 12 to form an n-well 40 and a p-well 42.
- n-well 40 the portion of surface sublayer 50 in structure region 14 is also subjected to the same n-type doping steps used in the circuit fabrication. This causes surface sublayer 50 in structure region 14 to become more conductive. This ensures that the entire thickness of device layer 48 in structure region 14 is a composed of a conductive material .
- transistors 80 and 82 are formed on substrate 16 using standard VLSI techniques to deposit gate structure 86.
- electrical interconnections 36 are formed between the microstructure elements in structure region 14 and circuit region 12. Electrical interconnections 84 are also formed between transistors 80 and 82 in circuit region 12. Electrical interconnections 36 may be formed as part of the same standard VLSI process that deposits electrical interconnections 84.
- Each electrical interconnection 36 includes a conductive layer 74 and an insulative layer 70 to isolate device layer 48 from conductive layer 74. Insulative layer 70 may be formed of silicon nitride. Such a layer may be 0.3 microns thick and may be deposited by LPCVD with the deposition gasses SiH 2 Cl 2 and NH 3 , at flow rates of 100 seem and 25 seem, respectively.
- the deposition may be performed at a pressure of 140 mTorr and a temperature of 835°C.
- Insulative layer 70 may be patterned to form through-holes 72 where electrical contact between device layer 48 and conductive layer 74 is desired.
- conductive layer 74 is deposited and patterned to form the electrical interconnections between structure region 14 and circuit region 12.
- the conductive layer 74 extends over isolation trench 18 so that electrical interconnections 36 provide the only connections between structure region 14 and circuit region 12.
- Conductive layer 74 may be a 0.54 micron thick layer of doped polysilicon deposited by LPCVD using the deposition gasses SiH 4 and phosphene (PH 3 ) at flow rates of 100 seem and 1 seem, respectively. The deposition may be performed at a temperature of 375 mTorr and a temperature of 610 °C for about five hours. Alternately, conductive layer 74 may be composed of a metal such as aluminum, copper or tungsten.
- device 10 may be completed by forming the microstructure elements in structure region 14.
- a second etching step is used to etch trenches or channels 28 in structure region 14 of device layer 48.
- Figure 15 shows the pattern that will be etched into device layer 48 to form channels 28 in phantom.
- Channels 28 may be etched using an ICP etch similar to the etching step used to form trench 60. The etch stops at the buried sacrificial layer 46.
- sacrificial layer 46 is etched to form air gap 34 and release proof mass 24 and flexures 26 from underlying handle layer 44.
- the release etch step may remove the sacrificial layer from beneath stationary electrode fingers 30a and 30b and may partially undercut isolation trench 18.
- the release etch may be performed using a timed hydrofluoric acid (HF) etch. This wet etch may be performed using about 49% concentration HF for about one minute. The wet etch may be followed by critical point carbon dioxide drying.
- HF hydrofluoric acid
- channels 28 may overlap isolation trench 18. This guarantees that all MEMS structures are electrically isolated from one another even in the event of mask misalignment by insuring the removal of all conductive material of device layer 48 from the trench side walls. This may cause the etch of channels 28 to also etch a portion of filler material 66 in isolation trench 18. As shown in Figure 17, if filler material 66 is etched, this process will create silicon nitride walls which bridge the gaps between the adjacent electrode fingers.
- a dry release process may be used to remove the portion of sacrificial layer 46 beneath structure region 14.
- the portion of handle layer 44 beneath structure region 14 may be etched to form a cavity 90 and expose sacrificial layer 46.
- the etching of handle layer 44 may be performed using an anisotropic wet etch with potassium hydroxide (KOH) or EDP .
- KOH potassium hydroxide
- handle layer 44 could be isotropically etched.
- sacrificial layer 46 may be removed using a dry oxide etch through the cavity.
- the microstructure elements in structure region 14 are suspended in an open space rather than forming an air gap with handle layer 44.
- the dry release step permits the isolation layer 64 to be a thermal oxide layer rather than a nitride layer.
- trench 60 is entirely filled by isolation layer 64.
- This embodiment does not use a filler material 66. Instead, isolation layer 64 grows on the sidewalls of the trench to fill the trench.
- trench 60 has a width W ⁇ of only about one to two microns . No CMP step and no capping layer are needed in this embodiment because the isolation layer covers the entire surface of sublayer 50.
- trench 60 could be etched through sacrificial layer 46 to expose handling layer 44. Then isolation layer 64 could be deposited onto sidewalls 62 and handle layer 44 at the bottom of trench 60. This would prevent the wet etch of the release step from undercutting isolation trench 18 because the isolation trench would extend entirely to the bottom surface of handle layer 44.
- a device having an isolation trench was fabricated.
- the trench electrically isolates adjacent stationary electrodes from each other and from the circuit region.
- a silicon nitride isolation layer lines the edges of the isolation trench, and it is filled with an undoped polysilicon filler material.
- a portion of the filler material in the isolation trench was also etched, leaving silicon nitride walls bridging the gaps between the adjacent electrode fingers.
- the dark region at the bottom of the image is the silicon oxide sacrificial layer and the grey region above it is the silicon device layer.
- the two vertical stripes are the silicon nitride isolation material, and the rough region between the vertical stripes is the polysilicon filler material.
- the region where the vertical stripes of the isolation layer curve and become horizontal show that the bottom of the isolation trench included a "footing effect" . That is, the bottom of the trench, and the isolation layer deposited therein, extends horizontally into the device layer. It is believed that this footing effect is caused by lateral etching when the trench etch front encounters the oxide of the sacrificial layer. The footing provides additional mechanical strength to the anchors.
- a "keyhole" is present where the polysilicon backfill did not completely close off the bottom of the trench.
- Figures 19-25 show a variety of test structures that were fabricated to evaluate the present invention. These test structures included isolation trenches and interconnect layers to demonstrate process functionality. They did not include microelectronic circuits.
- the devices are a Z-axis gyroscope (Figure 19) , an angular accelerometer (Figure 20) , a linear accelerometer ( Figure 21), a resonant accelerometer (Figure 22), a resonator ( Figure 23), a vibro-motor ( Figure 24), and a stain- failure test device (Figure 25) .
- a microfabrication process has been described for forming a device having a high vertical aspect ratio and electrical isolation between a structure region and a circuit region.
- the device may be fabricated on a single substrate and may include electrical interconnections between the structure region and the circuit region.
Abstract
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP98930171A EP1010361A4 (fr) | 1997-06-13 | 1998-06-12 | Dispositif microfabrique a rapport dimensionnel eleve avec isolation et interconnexions electriques |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/874,568 | 1997-06-13 | ||
US08/874,568 US6121552A (en) | 1997-06-13 | 1997-06-13 | Microfabricated high aspect ratio device with an electrical isolation trench |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1998057529A1 true WO1998057529A1 (fr) | 1998-12-17 |
Family
ID=25364092
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1998/012247 WO1998057529A1 (fr) | 1997-06-13 | 1998-06-12 | Dispositif microfabrique a rapport dimensionnel eleve avec isolation et interconnexions electriques |
Country Status (3)
Country | Link |
---|---|
US (2) | US6121552A (fr) |
EP (1) | EP1010361A4 (fr) |
WO (1) | WO1998057529A1 (fr) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2003037782A2 (fr) * | 2001-10-20 | 2003-05-08 | Robert Bosch Gmbh | Composant micromecanique et son procede de production |
EP1339101A2 (fr) * | 2002-02-22 | 2003-08-27 | Xerox Corporation | Systèmes et procédés pour l'intégration de dispositifs circuits hétérogènes |
EP1617178A1 (fr) * | 2004-07-12 | 2006-01-18 | STMicroelectronics S.r.l. | Structure micro-électro-mécanique avec des régions électriquement isolées et son procédé de fabrication |
EP1677073A1 (fr) * | 2004-12-29 | 2006-07-05 | STMicroelectronics S.r.l. | Gyroscope mems ayant des zones électriquement isolées |
WO2008052762A2 (fr) * | 2006-11-01 | 2008-05-08 | Atmel Germany Gmbh | Dispositif semi-conducteur et procédé de fabrication d'un dispositif semi-conducteur |
WO2008067294A2 (fr) * | 2006-11-27 | 2008-06-05 | University Of Florida Research Foundation, Inc. | Méthodes de formation d'isolations et d'encapsulage par microfabrication |
DE10003066B4 (de) * | 1999-01-25 | 2010-12-30 | DENSO CORPORATION, Kariya-shi | Halbleitersensor für eine physikalische Größe und Verfahren zum Herstellen desselben |
EP2082989A3 (fr) * | 2008-01-24 | 2013-10-09 | Delphi Technologies, Inc. | Procédé de fabrication d'un capteur |
Families Citing this family (89)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69942486D1 (de) * | 1998-01-15 | 2010-07-22 | Cornell Res Foundation Inc | Grabenisolation für mikromechanische bauelemente |
US6238580B1 (en) * | 1998-02-20 | 2001-05-29 | The Aerospace Corporation | Method of HF vapor release of microstructures |
US6600252B2 (en) * | 1999-01-14 | 2003-07-29 | The Regents Of The University Of Michigan | Method and subsystem for processing signals utilizing a plurality of vibrating micromechanical devices |
US6713938B2 (en) * | 1999-01-14 | 2004-03-30 | The Regents Of The University Of Michigan | Method and apparatus for filtering signals utilizing a vibrating micromechanical resonator |
US6433401B1 (en) * | 1999-04-06 | 2002-08-13 | Analog Devices Imi, Inc. | Microfabricated structures with trench-isolation using bonded-substrates and cavities |
US6798609B1 (en) * | 1999-07-28 | 2004-09-28 | Seagate Technology, Inc. | Magnetic microactuator with capacitive position sensor |
US8389370B2 (en) * | 1999-08-02 | 2013-03-05 | Schilmass Co. L.L.C. | Radiation-tolerant integrated circuit device and method for fabricating |
US6703679B1 (en) * | 1999-08-31 | 2004-03-09 | Analog Devices, Imi, Inc. | Low-resistivity microelectromechanical structures with co-fabricated integrated circuit |
JP4161493B2 (ja) * | 1999-12-10 | 2008-10-08 | ソニー株式会社 | エッチング方法およびマイクロミラーの製造方法 |
US20020071169A1 (en) | 2000-02-01 | 2002-06-13 | Bowers John Edward | Micro-electro-mechanical-system (MEMS) mirror device |
US6753638B2 (en) | 2000-02-03 | 2004-06-22 | Calient Networks, Inc. | Electrostatic actuator for micromechanical systems |
US6440766B1 (en) * | 2000-02-16 | 2002-08-27 | Analog Devices Imi, Inc. | Microfabrication using germanium-based release masks |
US6887391B1 (en) * | 2000-03-24 | 2005-05-03 | Analog Devices, Inc. | Fabrication and controlled release of structures using etch-stop trenches |
US6628041B2 (en) | 2000-05-16 | 2003-09-30 | Calient Networks, Inc. | Micro-electro-mechanical-system (MEMS) mirror device having large angle out of plane motion using shaped combed finger actuators and method for fabricating the same |
US6585383B2 (en) | 2000-05-18 | 2003-07-01 | Calient Networks, Inc. | Micromachined apparatus for improved reflection of light |
US6560384B1 (en) | 2000-06-01 | 2003-05-06 | Calient Networks, Inc. | Optical switch having mirrors arranged to accommodate freedom of movement |
US6262464B1 (en) | 2000-06-19 | 2001-07-17 | International Business Machines Corporation | Encapsulated MEMS brand-pass filter for integrated circuits |
WO2002012116A2 (fr) * | 2000-08-03 | 2002-02-14 | Analog Devices, Inc. | Procede de fabrication de systemes microelectromecaniques optiques a plaquette liee |
US6825967B1 (en) | 2000-09-29 | 2004-11-30 | Calient Networks, Inc. | Shaped electrodes for micro-electro-mechanical-system (MEMS) devices to improve actuator performance and methods for fabricating the same |
US6888979B2 (en) | 2000-11-29 | 2005-05-03 | Analog Devices, Inc. | MEMS mirrors with precision clamping mechanism |
US20020167072A1 (en) * | 2001-03-16 | 2002-11-14 | Andosca Robert George | Electrostatically actuated micro-electro-mechanical devices and method of manufacture |
KR100405176B1 (ko) * | 2001-04-12 | 2003-11-12 | 조동일 | 선택적 에스오아이 구조를 이용한 단결정 실리콘마이크로일렉트로미케니컬 시스템을 위한 절연 방법 |
US6813412B2 (en) * | 2001-07-24 | 2004-11-02 | Michael J. Daneman | Mems element having perpendicular portion formed from substrate |
US6583031B2 (en) | 2001-07-25 | 2003-06-24 | Onix Microsystems, Inc. | Method of making a MEMS element having perpendicular portion formed from substrate |
US6544863B1 (en) | 2001-08-21 | 2003-04-08 | Calient Networks, Inc. | Method of fabricating semiconductor wafers having multiple height subsurface layers |
US6624726B2 (en) * | 2001-08-31 | 2003-09-23 | Motorola, Inc. | High Q factor MEMS resonators |
US6611168B1 (en) | 2001-12-19 | 2003-08-26 | Analog Devices, Inc. | Differential parametric amplifier with physically-coupled electrically-isolated micromachined structures |
US6828171B2 (en) * | 2002-01-16 | 2004-12-07 | Xerox Corporation | Systems and methods for thermal isolation of a silicon structure |
US6627529B2 (en) * | 2002-02-07 | 2003-09-30 | Micron Technology, Inc. | Capacitance reduction by tunnel formation for use with semiconductor device |
US20030161949A1 (en) * | 2002-02-28 | 2003-08-28 | The Regents Of The University Of California | Vapor deposition of dihalodialklysilanes |
US8294172B2 (en) | 2002-04-09 | 2012-10-23 | Lg Electronics Inc. | Method of fabricating vertical devices using a metal support film |
US20030189215A1 (en) * | 2002-04-09 | 2003-10-09 | Jong-Lam Lee | Method of fabricating vertical structure leds |
US7728339B1 (en) | 2002-05-03 | 2010-06-01 | Calient Networks, Inc. | Boundary isolation for microelectromechanical devices |
EP1375416B1 (fr) * | 2002-06-20 | 2007-10-24 | STMicroelectronics S.r.l. | Dispositif microélectromécanique, particulièrement microactionneur pour unité de disque dur, et sa méthode de fabrication |
US6841802B2 (en) | 2002-06-26 | 2005-01-11 | Oriol, Inc. | Thin film light emitting diode |
WO2004013893A2 (fr) * | 2002-08-01 | 2004-02-12 | Georgia Tech Research Corporation | Resonateurs microelectromecaniques isolant a materiau piezo-electrique sur semi-conducteur et procede de fabrication |
AU2003290513A1 (en) * | 2002-08-07 | 2004-04-08 | Georgia Tech Research Corporation | Capacitive resonators and methods of fabrication |
US7224035B1 (en) | 2002-10-07 | 2007-05-29 | Zyvex Corporation | Apparatus and fabrication methods for incorporating sub-millimeter, high-resistivity mechanical components with low-resistivity conductors while maintaining electrical isolation therebetween |
US6879016B1 (en) | 2002-10-07 | 2005-04-12 | Zyvex Corporation | Microcomponent having intra-layer electrical isolation with mechanical robustness |
US6961299B2 (en) * | 2002-12-05 | 2005-11-01 | Hewlett-Packard Development Company, L.P. | Storage device |
US6713829B1 (en) | 2003-03-12 | 2004-03-30 | Analog Devices, Inc. | Single unit position sensor |
US8519503B2 (en) | 2006-06-05 | 2013-08-27 | Osi Optoelectronics, Inc. | High speed backside illuminated, front side contact photodiode array |
US8686529B2 (en) | 2010-01-19 | 2014-04-01 | Osi Optoelectronics, Inc. | Wavelength sensitive sensor photodiodes |
US7709921B2 (en) | 2008-08-27 | 2010-05-04 | Udt Sensors, Inc. | Photodiode and photodiode array with improved performance characteristics |
US7057254B2 (en) * | 2003-05-05 | 2006-06-06 | Udt Sensors, Inc. | Front illuminated back side contact thin wafer detectors |
US6917459B2 (en) * | 2003-06-03 | 2005-07-12 | Hewlett-Packard Development Company, L.P. | MEMS device and method of forming MEMS device |
US6952041B2 (en) * | 2003-07-25 | 2005-10-04 | Robert Bosch Gmbh | Anchors for microelectromechanical systems having an SOI substrate, and method of fabricating same |
JP2005098740A (ja) * | 2003-09-22 | 2005-04-14 | Denso Corp | 容量式半導体力学量センサ |
US6914709B2 (en) * | 2003-10-02 | 2005-07-05 | Hewlett-Packard Development Company, L.P. | MEMS device and method of forming MEMS device |
US6861277B1 (en) | 2003-10-02 | 2005-03-01 | Hewlett-Packard Development Company, L.P. | Method of forming MEMS device |
ATE364929T1 (de) * | 2003-11-14 | 2007-07-15 | Koninkl Philips Electronics Nv | Halbleiterbauelement mit enem resonator |
US7146080B2 (en) | 2004-03-11 | 2006-12-05 | Lambda Crossing, Ltd. | Method of connecting an optical element to a PLC |
US20050201668A1 (en) * | 2004-03-11 | 2005-09-15 | Avi Neta | Method of connecting an optical element at a slope |
US7224870B2 (en) * | 2004-03-11 | 2007-05-29 | Lambda Crossing | Method of coupling fiber to waveguide |
US7037745B2 (en) * | 2004-05-06 | 2006-05-02 | Dalsa Semiconductor Inc. | Method of making electrical connections to hermetically sealed MEMS devices |
DE102004022781A1 (de) * | 2004-05-08 | 2005-12-01 | X-Fab Semiconductor Foundries Ag | SOI-Scheiben mit MEMS-Strukturen und verfüllten Isolationsgräben definierten Querschnitts |
US7618837B2 (en) * | 2004-06-29 | 2009-11-17 | Peking University | Method for fabricating high aspect ratio MEMS device with integrated circuit on the same substrate using post-CMOS process |
US7235493B2 (en) * | 2004-10-18 | 2007-06-26 | Micron Technology, Inc. | Low-k dielectric process for multilevel interconnection using mircocavity engineering during electric circuit manufacture |
US7795695B2 (en) | 2005-01-27 | 2010-09-14 | Analog Devices, Inc. | Integrated microphone |
US7531424B1 (en) * | 2005-05-03 | 2009-05-12 | Discera, Inc. | Vacuum wafer-level packaging for SOI-MEMS devices |
US7337671B2 (en) | 2005-06-03 | 2008-03-04 | Georgia Tech Research Corp. | Capacitive microaccelerometers and fabrication methods |
US7939355B2 (en) * | 2005-10-13 | 2011-05-10 | The Regents Of The University Of California | Single-mask fabrication process for linear and angular piezoresistive accelerometers |
US8034719B1 (en) | 2005-12-08 | 2011-10-11 | The United States Of America As Represented By The Secretary Of The Navy | Method of fabricating high aspect ratio metal structures |
US7578189B1 (en) | 2006-05-10 | 2009-08-25 | Qualtre, Inc. | Three-axis accelerometers |
CN101479185B (zh) * | 2006-06-29 | 2012-03-28 | Nxp股份有限公司 | Mems器件及制造方法 |
US7868403B1 (en) * | 2007-03-01 | 2011-01-11 | Rf Micro Devices, Inc. | Integrated MEMS resonator device |
US7639104B1 (en) * | 2007-03-09 | 2009-12-29 | Silicon Clocks, Inc. | Method for temperature compensation in MEMS resonators with isolated regions of distinct material |
CN101826535A (zh) * | 2007-09-13 | 2010-09-08 | 李刚 | 一种微机电器件与集成电路器件单片集成芯片 |
EP2060871A3 (fr) * | 2007-11-19 | 2012-12-26 | Hitachi Ltd. | Capteur d'inertie |
US7851875B2 (en) | 2008-01-11 | 2010-12-14 | Infineon Technologies Ag | MEMS devices and methods of manufacture thereof |
US8125046B2 (en) * | 2008-06-04 | 2012-02-28 | Infineon Technologies Ag | Micro-electromechanical system devices |
MX2011002852A (es) | 2008-09-15 | 2011-08-17 | Udt Sensors Inc | Fotodiodo de espina de capa activa delgada con una capa n+ superficial y metodo para fabricacion del mismo. |
US8499629B2 (en) * | 2008-10-10 | 2013-08-06 | Honeywell International Inc. | Mounting system for torsional suspension of a MEMS device |
US7943525B2 (en) * | 2008-12-19 | 2011-05-17 | Freescale Semiconductor, Inc. | Method of producing microelectromechanical device with isolated microstructures |
WO2010111601A2 (fr) * | 2009-03-26 | 2010-09-30 | Semprius, Inc. | Procédés de formation de dispositifs à circuits imprimés imprimables et dispositifs formés de la sorte |
US8399909B2 (en) | 2009-05-12 | 2013-03-19 | Osi Optoelectronics, Inc. | Tetra-lateral position sensing detector |
US20100289065A1 (en) * | 2009-05-12 | 2010-11-18 | Pixart Imaging Incorporation | Mems integrated chip with cross-area interconnection |
WO2011026100A1 (fr) | 2009-08-31 | 2011-03-03 | Georgia Tech Research Corporation | Gyroscope à onde acoustique de volume et à structure à rayons |
TW201109267A (en) * | 2009-09-08 | 2011-03-16 | Jung-Tang Huang | A general strength and sensitivity enhancement method for micromachined devices |
CN102050418B (zh) * | 2010-09-30 | 2013-01-09 | 北京大学 | 一种三维集成结构及其生产方法 |
TWI426572B (zh) | 2011-10-20 | 2014-02-11 | Ind Tech Res Inst | 微機電感測裝置及其製造方法 |
JP6020793B2 (ja) * | 2012-04-02 | 2016-11-02 | セイコーエプソン株式会社 | 物理量センサーおよび電子機器 |
JP2014021037A (ja) * | 2012-07-23 | 2014-02-03 | Seiko Epson Corp | Memsデバイス、電子モジュール、電子機器、及び移動体 |
US8912615B2 (en) | 2013-01-24 | 2014-12-16 | Osi Optoelectronics, Inc. | Shallow junction photodiode for detecting short wavelength light |
US9218065B2 (en) * | 2013-03-11 | 2015-12-22 | Intel Corporation | Stress tolerant MEMS accelerometer |
US9079763B2 (en) | 2013-04-22 | 2015-07-14 | Freescale Semiconductor, Inc. | MEMS device with stress isolation and method of fabrication |
JP6206651B2 (ja) | 2013-07-17 | 2017-10-04 | セイコーエプソン株式会社 | 機能素子、電子機器、および移動体 |
JP2016042074A (ja) | 2014-08-13 | 2016-03-31 | セイコーエプソン株式会社 | 物理量センサー、電子機器および移動体 |
JP2019120559A (ja) * | 2017-12-28 | 2019-07-22 | セイコーエプソン株式会社 | 物理量センサー、物理量センサーの製造方法、物理量センサーデバイス、電子機器および移動体 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3725671A (en) * | 1970-11-02 | 1973-04-03 | Us Navy | Pyrotechnic eradication of microcircuits |
US4049903A (en) * | 1974-10-23 | 1977-09-20 | Amp Incorporated | Circuit film strip and manufacturing method |
US4764644A (en) * | 1985-09-30 | 1988-08-16 | Microelectronics Center Of North Carolina | Microelectronics apparatus |
Family Cites Families (38)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4063271A (en) * | 1972-07-26 | 1977-12-13 | Texas Instruments Incorporated | FET and bipolar device and circuit process with maximum junction control |
US3936329A (en) * | 1975-02-03 | 1976-02-03 | Texas Instruments Incorporated | Integral honeycomb-like support of very thin single crystal slices |
US3962052A (en) * | 1975-04-14 | 1976-06-08 | International Business Machines Corporation | Process for forming apertures in silicon bodies |
JPS5636143A (en) * | 1979-08-31 | 1981-04-09 | Hitachi Ltd | Manufacture of semiconductor device |
US4307507A (en) * | 1980-09-10 | 1981-12-29 | The United States Of America As Represented By The Secretary Of The Navy | Method of manufacturing a field-emission cathode structure |
US4631803A (en) * | 1985-02-14 | 1986-12-30 | Texas Instruments Incorporated | Method of fabricating defect free trench isolation devices |
US4698900A (en) * | 1986-03-27 | 1987-10-13 | Texas Instruments Incorporated | Method of making a non-volatile memory having dielectric filled trenches |
EP0296348B1 (fr) * | 1987-05-27 | 1993-03-31 | Siemens Aktiengesellschaft | Procédé d'attaque pour creuser des trous ou des sillons dans du silicium de type n |
JPH01138110A (ja) * | 1987-11-25 | 1989-05-31 | Showa Denko Kk | ダイヤモンド製パイプおよびその製造法 |
US5343064A (en) * | 1988-03-18 | 1994-08-30 | Spangler Leland J | Fully integrated single-crystal silicon-on-insulator process, sensors and circuits |
JPH0338061A (ja) * | 1989-07-05 | 1991-02-19 | Fujitsu Ltd | 半導体記憶装置 |
JPH03129854A (ja) * | 1989-10-16 | 1991-06-03 | Toshiba Corp | 半導体装置の製造方法 |
US5131978A (en) * | 1990-06-07 | 1992-07-21 | Xerox Corporation | Low temperature, single side, multiple step etching process for fabrication of small and large structures |
US5271801A (en) * | 1990-07-09 | 1993-12-21 | Commissariat A L'energie Atomique | Process of production of integrated optical components |
US5417111A (en) * | 1990-08-17 | 1995-05-23 | Analog Devices, Inc. | Monolithic chip containing integrated circuitry and suspended microstructure |
US5326726A (en) * | 1990-08-17 | 1994-07-05 | Analog Devices, Inc. | Method for fabricating monolithic chip containing integrated circuitry and suspended microstructure |
US5198390A (en) * | 1992-01-16 | 1993-03-30 | Cornell Research Foundation, Inc. | RIE process for fabricating submicron, silicon electromechanical structures |
DE4202454C1 (fr) * | 1992-01-29 | 1993-07-29 | Siemens Ag, 8000 Muenchen, De | |
FR2700065B1 (fr) * | 1992-12-28 | 1995-02-10 | Commissariat Energie Atomique | Procédé de fabrication d'accéléromètres utilisant la technologie silicium sur isolant. |
CA2154357C (fr) * | 1993-02-04 | 2004-03-02 | Kevin A. Shaw | Microstructures et methode a un seul masque et a cristal unique pour leur obtention |
JP3818673B2 (ja) * | 1993-03-10 | 2006-09-06 | 株式会社デンソー | 半導体装置 |
EP0618450A1 (fr) * | 1993-03-30 | 1994-10-05 | Siemens Aktiengesellschaft | Capteur d'accélération |
US5536988A (en) * | 1993-06-01 | 1996-07-16 | Cornell Research Foundation, Inc. | Compound stage MEM actuator suspended for multidimensional motion |
EP0635884A1 (fr) * | 1993-07-13 | 1995-01-25 | Siemens Aktiengesellschaft | Procédé pour la fabrication d'une rainure dans un substrat et application à la technologie de puissance vive |
DE4332057A1 (de) * | 1993-09-21 | 1995-03-30 | Siemens Ag | Integrierte mikromechanische Sensorvorrichtung und Verfahren zu deren Herstellung |
DE4332843C2 (de) * | 1993-09-27 | 1997-04-24 | Siemens Ag | Verfahren zur Herstellung einer mikromechanischen Vorrichtung und mikromechanische Vorrichtung |
DE4400127C2 (de) * | 1994-01-05 | 2003-08-14 | Bosch Gmbh Robert | Kapazitiver Beschleunigungssensor und Verfahren zu seiner Herstellung |
DE4419844B4 (de) * | 1994-06-07 | 2009-11-19 | Robert Bosch Gmbh | Beschleunigungssensor |
US5447884A (en) * | 1994-06-29 | 1995-09-05 | International Business Machines Corporation | Shallow trench isolation with thin nitride liner |
US5565625A (en) * | 1994-12-01 | 1996-10-15 | Analog Devices, Inc. | Sensor with separate actuator and sense fingers |
DE19500392A1 (de) * | 1995-01-09 | 1996-07-18 | Siemens Ag | Integrierte Schaltungsstruktur und Verfahren zu deren Herstellung |
US5504026A (en) * | 1995-04-14 | 1996-04-02 | Analog Devices, Inc. | Methods for planarization and encapsulation of micromechanical devices in semiconductor processes |
US5798283A (en) * | 1995-09-06 | 1998-08-25 | Sandia Corporation | Method for integrating microelectromechanical devices with electronic circuitry |
US5747353A (en) * | 1996-04-16 | 1998-05-05 | National Semiconductor Corporation | Method of making surface micro-machined accelerometer using silicon-on-insulator technology |
US5882532A (en) * | 1996-05-31 | 1999-03-16 | Hewlett-Packard Company | Fabrication of single-crystal silicon structures using sacrificial-layer wafer bonding |
US5637189A (en) * | 1996-06-25 | 1997-06-10 | Xerox Corporation | Dry etch process control using electrically biased stop junctions |
EP0822578B1 (fr) * | 1996-07-31 | 2003-10-08 | STMicroelectronics S.r.l. | Procédé de fabrication des dispositifs semi-conducteurs intégrés comprenant un microcapteur chemoresistifs de gaz |
US5807783A (en) * | 1996-10-07 | 1998-09-15 | Harris Corporation | Surface mount die by handle replacement |
-
1997
- 1997-06-13 US US08/874,568 patent/US6121552A/en not_active Expired - Lifetime
-
1998
- 1998-06-12 WO PCT/US1998/012247 patent/WO1998057529A1/fr not_active Application Discontinuation
- 1998-06-12 EP EP98930171A patent/EP1010361A4/fr not_active Withdrawn
-
1999
- 1999-06-29 US US09/342,348 patent/US6960488B2/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3725671A (en) * | 1970-11-02 | 1973-04-03 | Us Navy | Pyrotechnic eradication of microcircuits |
US4049903A (en) * | 1974-10-23 | 1977-09-20 | Amp Incorporated | Circuit film strip and manufacturing method |
US4764644A (en) * | 1985-09-30 | 1988-08-16 | Microelectronics Center Of North Carolina | Microelectronics apparatus |
Non-Patent Citations (1)
Title |
---|
See also references of EP1010361A4 * |
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10003066B4 (de) * | 1999-01-25 | 2010-12-30 | DENSO CORPORATION, Kariya-shi | Halbleitersensor für eine physikalische Größe und Verfahren zum Herstellen desselben |
US7312553B2 (en) | 2001-10-20 | 2007-12-25 | Robert Bosch Gmbh | Micromechanical component and method for producing same |
WO2003037782A3 (fr) * | 2001-10-20 | 2004-01-29 | Bosch Gmbh Robert | Composant micromecanique et son procede de production |
WO2003037782A2 (fr) * | 2001-10-20 | 2003-05-08 | Robert Bosch Gmbh | Composant micromecanique et son procede de production |
EP1339101A2 (fr) * | 2002-02-22 | 2003-08-27 | Xerox Corporation | Systèmes et procédés pour l'intégration de dispositifs circuits hétérogènes |
EP1617178A1 (fr) * | 2004-07-12 | 2006-01-18 | STMicroelectronics S.r.l. | Structure micro-électro-mécanique avec des régions électriquement isolées et son procédé de fabrication |
US7437933B2 (en) | 2004-07-12 | 2008-10-21 | Stmicroelectronics S.R.L. | Micro-electro-mechanical structure having electrically insulated regions and manufacturing process thereof |
US7258008B2 (en) | 2004-12-29 | 2007-08-21 | Stmicroelectronics S.R.L. | Micro-electro-mechanical gyroscope having electrically insulated regions |
EP1677073A1 (fr) * | 2004-12-29 | 2006-07-05 | STMicroelectronics S.r.l. | Gyroscope mems ayant des zones électriquement isolées |
WO2008052762A2 (fr) * | 2006-11-01 | 2008-05-08 | Atmel Germany Gmbh | Dispositif semi-conducteur et procédé de fabrication d'un dispositif semi-conducteur |
WO2008052762A3 (fr) * | 2006-11-01 | 2008-07-17 | Atmel Germany Gmbh | Dispositif semi-conducteur et procédé de fabrication d'un dispositif semi-conducteur |
WO2008067294A2 (fr) * | 2006-11-27 | 2008-06-05 | University Of Florida Research Foundation, Inc. | Méthodes de formation d'isolations et d'encapsulage par microfabrication |
WO2008067294A3 (fr) * | 2006-11-27 | 2008-11-27 | Univ Florida | Méthodes de formation d'isolations et d'encapsulage par microfabrication |
EP2082989A3 (fr) * | 2008-01-24 | 2013-10-09 | Delphi Technologies, Inc. | Procédé de fabrication d'un capteur |
Also Published As
Publication number | Publication date |
---|---|
US6121552A (en) | 2000-09-19 |
US20040147055A1 (en) | 2004-07-29 |
US6960488B2 (en) | 2005-11-01 |
EP1010361A4 (fr) | 2001-05-30 |
EP1010361A1 (fr) | 2000-06-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6121552A (en) | Microfabricated high aspect ratio device with an electrical isolation trench | |
US6291875B1 (en) | Microfabricated structures with electrical isolation and interconnections | |
US6433401B1 (en) | Microfabricated structures with trench-isolation using bonded-substrates and cavities | |
US7618837B2 (en) | Method for fabricating high aspect ratio MEMS device with integrated circuit on the same substrate using post-CMOS process | |
US6951824B2 (en) | Method for manufacturing a micromechanical component and a component that is manufactured in accordance with the method | |
US6686638B2 (en) | Micromechanical component including function components suspended movably above a substrate | |
US6739189B2 (en) | Micro structure for vertical displacement detection and fabricating method thereof | |
US7943525B2 (en) | Method of producing microelectromechanical device with isolated microstructures | |
US7437933B2 (en) | Micro-electro-mechanical structure having electrically insulated regions and manufacturing process thereof | |
TWI395257B (zh) | 在高深寬比微機電系統中寬溝槽及窄溝槽之形成 | |
WO2005092782A1 (fr) | Detecteur au silicium monocristallin a couche additionnelle et procede de production correspondant | |
WO1993022690A1 (fr) | Capteur d'acceleration et son procede de fabrication | |
US6569702B2 (en) | Triple layer isolation for silicon microstructure and structures formed using the same | |
US9194882B2 (en) | Inertial and pressure sensors on single chip | |
US6472290B2 (en) | Isolation in micromachined single crystal silicon using deep trench insulation | |
EP0895090B1 (fr) | Procédé de fabrication d'accéléromètre et capteur gyroscopique intégré à haute sensibilité et capteurs fabriqués par ce procédé | |
US7550358B2 (en) | MEMS device including a laterally movable portion with piezo-resistive sensing elements and electrostatic actuating elements on trench side walls, and methods for producing the same | |
KR100817813B1 (ko) | 실리콘 기판 상에 상이한 수직 단차를 갖는 미세구조물의제조 방법 | |
WO2003065052A2 (fr) | Procede relatif a la fabrication d'un accelerometre | |
US7063796B2 (en) | Micromechanical component and method for producing the same | |
JP4122572B2 (ja) | 半導体力学量センサの製造方法 | |
Johnstone et al. | Micromachining Technologies | |
CN117342516A (zh) | 一种mems垂直电极结构的制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): JP KR |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE |
|
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
Ref document number: 1998930171 Country of ref document: EP |
|
NENP | Non-entry into the national phase |
Ref country code: JP Ref document number: 1999503250 Format of ref document f/p: F |
|
WWP | Wipo information: published in national office |
Ref document number: 1998930171 Country of ref document: EP |
|
WWW | Wipo information: withdrawn in national office |
Ref document number: 1998930171 Country of ref document: EP |