Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/38—Information transfer, e.g. on bus
  • G06F13/40—Bus structure
  • G06F13/4004—Coupling between buses
  • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
  • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
  • G09G5/363—Graphics controllers
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2300/00—Aspects of the constitution of display devices
  • G09G2300/04—Structural and physical details of display devices
  • G09G2300/0404—Matrix technologies
  • G09G2300/0408—Integration of the drivers onto the display substrate
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2360/00—Aspects of the architecture of display systems
  • G09G2360/12—Frame memory handling
  • G09G2360/121—Frame memory handling using a cache memory
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2360/00—Aspects of the architecture of display systems
  • G09G2360/12—Frame memory handling
  • G09G2360/125—Frame memory handling using unified memory architecture [UMA]
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2360/00—Aspects of the architecture of display systems
  • G09G2360/12—Frame memory handling
  • G09G2360/128—Frame memory using a Synchronous Dynamic RAM [SDRAM]
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
  • G09G5/001—Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
  • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
  • G09G5/39—Control of the bit-mapped memory
  • G09G5/393—Arrangements for updating the contents of the bit-mapped memory

Definitions

• TITLE COMPUTER SYSTEM WITH UNIFIED SYSTEM MEMORY AND IMPROVED BUS CONCURRENCY
• This invention relates to computer systems, and more particularly, to an integrated computer system having a unified system memory and improved bus concurrency.
• Typical computer systems include a central processing unit (“CPU”) and system memory coupled to a high-speed system bus.
• a bus bridge device is employed to bridge the high-speed system bus to a lower- speed peripheral bus.
• slower-speed devices such as modems, drive controllers, and network interlaces, are located on the low-speed bus.
• a graphics controller is located on the high-speed bus.
• the graphics controller typically includes its own memory separate from the main system memory. This separate graphics memory is used to store screen image data for display on a monitor.
• DMA controller typically included in modern computer systems. The DMA controller allows for the direct transfer of data between system memory on the high-speed bus and peripheral bus devices on the low-speed bus.
• Computer system 100 includes system memory 112 and CPU 114. both coupled to the high-speed system bus 110.
• a graphics controller 132 is also coupled to the high-speed system bus 1 10.
• Bus bridge 120 couples the high- speed system bus 110 to a low-speed peripheral bus 130.
• One or more bus devices, such as bus device 134. may be coupled to the low-speed peripheral bus 130.
• Bus device 134 may be any type of bus device commonly found in computer systems, such as a modem device.
• Graphics controller 132 is connected to graphics memory 133.
• DMA controller 122 which facilitates data transfers between bus device 134 and system memory 112.
• System memory 112 typically comprises DRAM memory operating in fast page mode or extended data out (EDO) mode.
• System memory 112 stores data operated on by CPU 114.
• CPU 114 transfers data to and from system memory 112 over high-speed system bus 110.
• CPU 114 may also transfer data to and from bus device 134 through bus bridge 120.
• DMA controller 122 allows data to be transferred directly between bus device 134 and system memory 112.
• Graphics controller 132 operates on data contained in graphics memory 133, which is memory separate from system memory 112.
• Graphics memory 133 is typically high-speed DRAM or VRAM memory.
• Graphics memory 1 3 contains data corresponding to the screen image displayed upon an external monitor.
• CPU 114 may also access graphics memory 133.
• graphics controller 132 only accesses graphics memory 133 and does not access system memory 112.
• Graphics controller 132 displays screen images by reading the screen image data stored in graphics memory 133 and converting the screen image data mto analog monitor signals which create the screen unage display on an external monitor
• An increasingly popular application ot computer systems is in small hand-held low-power and low-cost computer de ⁇ ices I hus, it is desirable to have a low-cost lo -power computer svstem that can be implemented in a small amount ot space
• One method ot obtammg low cost low power small sized computer systems is to integrate as mans ot the computer svstem functions onto a single mtegrated circuit device as possible
• Technolo ical improvements in the feature size ot mtegrated circuits in recent vears have allowed man ⁇ ot the functions shown in computer svstem 100 to be integrated onto a single monolithic substrate
• DMA controller 122 and graphics controller 132 may all be integrated mto a sincle dev ice as shown b ⁇ the dotted-hne enclosure 140 in Fig 1A
• Computer svstem 150 includes CPU 1 14 and umficd memon 1 16 both coupled to Inch-speed svstem bus 1 10
• Bus b ⁇ dge 120 couples high-speed svstem bus 110 to low-speed peripheral bus 130
• a bus device 134 is coupled to the low-speed pe ⁇ pheral bus 130 111 contrast to computer s stem 100 of Tig 1A graphics controller 118 ot computer sv stem 150 in T ig IB is coupled to the high-speed sv stem bus 110
• the CPU 1 14 and graphics controller 1 18 both access data m the unified memon 1 16 In other words both CPU data and screen image data arc stored in the unified memory 1 16
• the architecture ot computer svstem 150 allows mtegration ot many ot the computer svstem components into a single mtegrated device wlule requiring fewer external interlaces than the mtegrated device represented bv dotted-lme 140 in Fig 1A
• the CPU 1 14 graphics controller 1 18 bus b ⁇ dge 120 and DMA controller 122 mav all be mtegrated mto a single device requiring external data interlaces onlv to low -speed bus 130 and to high-speed svstem bus 1 10 (svstem memory 1 16)
• Bv utilizing a unified memon architecture the separate external interlace to graphics memory 133 has been elunmated thus savmg numerous pms on the integrated circuit package urthermore onlv a single memory controller is needed to interlace to the unified system memory 1 16 as opposed to two memory controllers that would be needed
• CPU 114, graphics controller 118. and DMA controller 1 12 must all share the high-speed system bus 1 10 in order to access the unified memory 1 16. Therefore, only one of these devices may access the unified memory 1 16 at a time. For example, if the CPU is currently performing a burst read operation from the unified memory 116. the graphics controller 118 must wait until the CPU access is completed before the graphics controller 1 18 may access the unified memory 1 16. This architecture can lead to serious performance bottlenecks. For example, when graphics controller 1 18 is performing a screen refresh operation, it must have continuous access to the unified memory 1 16 during the refresh operation. Otherwise, visible glitches would appear to the user on the external monitor.
• the CPU and DMA controller are completely denied access to the unified memory 1 16. thereby severely impairing overall system performance.
• the DMA controller is performing a long DMA block transfer over the high-speed system bus 110 to the unified memory 1 16.
• the graphics controller 1 18 may have to wait an extended period of time before being able to perform a new screen refresh operation. If this period of time is too long, noticeable glitches will appear on the monitor to the user.
• a computer system in accordance with the present invention, includes a central processing unit (CPU), a graphics controller, system memory, data steering logic, and memory arbitration logic.
• the graphics controller and system memory are both coupled to a high-speed data bus. Data accessed by the CPU and data accessed by the graphics controller are both stored in the system memory.
• the data steering logic is coupled to the high-speed data bus. coupled to a low-speed data bus, and coupled to the CPU.
• the data steering logic is configured to selectively couple the CPU to either the high-speed data bus. or to the low-speed data bus.
• the data steering logic is able to accommodate data transfers between the CPU and a device connected to the second data bus concurrently with data transfers between the graphics controller and the system memory.
• the memory arbitration logic is coupled to the graphics controller and to the CPU. This arbitration logic is configured to arbitrate for access to the system memory, thereby preventing bus contention on the high-speed data bus.
• a direct memory access (DMA) controller is included in the computer system as described above. This DMA controller is coupled to the memory arbitration logic.
• the memory arbitration logic and data steering logic are configured to accommodate the DMA controller accessing devices on the low-speed data bus concurrently with the graphics controller accessing the system memory.
• This embodiment may also include system arbitration logic coupled to the CPU and DMA controller I he svstem arbitration logic arbitrates between the CPU and the DMA controller tor access to the system memon I he winner ot tins arbitration is indicated to the memory arbitration logic which then arbitrates between the winner and the graphics controller lor ultimate access to the svstem memory
• the svstem arbitration logic mav be configured so that the CPU is the default arbitration winner Tims, the svstem arbitration logic alwavs indicates the CPU as the arbitration winner, unless the DMA controller asserts a bus request indication prompting svstem arbitration
• the memon arbitration logic mav be configured so that the graphics controller has arbitration priority over the winner ot the svstem arbitration This priority scheme is desirable to ensure that the graphics controller mav regularly access svstem memon m order to maintain a glitch tree screen displav
• the CPU mav comprise a cache memon
• the cache memon is a small, high-speed memon located between the CPU and
• a single mtegrated circuit device comp ⁇ smg a CPU a graplucs controller, data steering logic, and memon arbitration logic
• the graphics controller is coupled to a high-speed data bus Oiis high-speed data bus also connects to svstem memory that is external from the integrated circuit device Data accessed bv the CPU and data accessed bv the graphics controller are both stored in this external svstem memon'
• the data steering logic is coupled to the high-speed data bus to an external lovv- speed data bus and to the CPU
• the data steermg logic is configured to selectivelv couple the CPU to either the high-speed data bus or the external low -speed data bus
• the data steermg logic accommodates data tiansleis between the CPU and an external bus device coupled to the external low-speed data bus concurrent with data transters between the graplucs controller and the external sv
• the present mvention achieves a computer svstem with improved bus concurrencv Furthermore, the present invention allows a CPU. DMA controller bus bridge, and graphics controller to be mtegrated mto a smgle, low cost small size, integrated circuit device This mtegrated circuit device requires onlv one memory mtertace without sacrificing overall svstem performance and is thus able to support modern operating svstcms such as Windows* or GEOS
• Tig 1 A is a block diagram ot a p ⁇ or art computer svstem
• Fig IB is a block diagram ot a p ⁇ or art computer svstem employing a unified memon architecture
• Fig 2 is a block diagram ot a computer svstem including data stee ⁇ ng logic and arbitration logic accordmg to one embodiment ot the present mvention.
• Fig 3 is a detailed block diagram ot the data paths ot the computer svstem ot Fig 2.
• Fig 4 is a detailed block diagram ot the arbitration logic ot the computer svstem of Fig 2, and
• Fig 5 is a block diagram illustrating one embodiment ot the present mvention allowing an alternative configuration to support a 32-bit external high-speed bus
• Computer svstem 200 is shown including a central processing unit (CPU) 202.
• DMA controller 206 and graphics controller 212 These three devices share access to unified svstem memon 222 through a 16 bit high-speed data bus 228
• System arbiter 210 and memon arbiter 218 work together to control access to the unified system memory 222 and prevent contention on the highspeed data bus 228
• the operation ot the arbiter svstem comprising svstem arbiter 210 and memon arbiter 218 is discussed in further detail below
• control logic 216 and data steermg logic 220 Data steermg logic 220 is coupled to the 32-bit CPU data bus and coupled to the 16 bit high-speed data bus 228 Also mcluded m computer svstem 200 is a slow-speed bus 224 which mav have one or more bus devices such as bus device 226 coupled to it I e 16 bit data bus ot the slow-speed bus 224 is coupled to data stee ⁇ ng logic 220 Also coupled to data stee ⁇ ng logic 220 is an 8 bit data bus which provides a data path to va ⁇ ous control units and registers represented bv PC Cores/Registers 208 in the illustration CPU 202 is illustrative ot an X86 microprocessor such as an 80486® microprocessor, or other compatible microprocessor It is understood, however, that a svstem according to the present invention mav employ other types ot microprocessors such as a RISC type microprocessor
• DMA controller 206 is illustrative ot. for example, a PC compatible DMA controller, such as two 8237A compatible controllers as typically incorporated m IBM compatible PCs However, it is understood that anv tvpe ot direct memon access controller may be utilized m the present invention DMA controller 206 tunctions to tacihtate data translers directly between devices connected to slow-speed bus 224 and the unified svstem memon 222 For example. DMA controller 206 obtains control of the high-speed data bus 228 and generates the necessan control signals to create memon transters between bus device 226 and unitied svstem memon 222 without mtenention bv CPU 202 Thus. DMA controller 206 provides tor higher overall system performance b ⁇ allowing devices located on slow-speed bus 224 to communicate directly with memon one operation as opposed to two operations that would be required it the CPU 202 intervened
• Graphics controller 212 tunctions to create and manipulate visual screen images on an external monitor (not shown) to provide the user interface tor computer svstem 200
• the screen image is stored as data m unified system memon 222
• the graphics controller 212 accesses the screen data m the unified system memon 222 in order to change and/or retresh the screen image
• Screen refreshes are performed when the graphics controller 21 reads the screen unage data trom the unified svstem memon 222 and converts the data into analog signals which are sent to the external monitor to create the visual screen image
• Graphics controller 212 mav be sunilar to graplucs controllers found in tvpical personal computers and mav function to control CRT tvpe external monitors or LCD type displays, among others
• Unified svstem memory 222 mav comprise DRAM tvpe memon operating in fast page mode or extended data out (EDO) mode It is understood that other types ot memorv.
• Unified svstem memon 222 is coupled to the graphics controller 212 and data stee ⁇ ng logic 220 bv high-speed data bus 228 Unified svstem memon 222 also receives address and control signals trom control logic 216 Data accessed bv CPU 202.
• graphics controller 212 and bus devices such as bus device 226. is all located in unitied system memon 222
• bus device 226 is all located in unitied system memon 222
• other memon mav be located on bus devices such as bus device 226. located on the slow-speed bus 224
• This tvpe of memon arclutecture where the CPU and graphics controller both share the same phvsical memon' is often referred to as a shared memon architecture
• Slow-speed bus 224 supports an expansion tvpe bus such as the Industn Standard Architecture (ISA) bus or the PCMCIA (PC Card) bus Also, m some embodiments ot the present invention, slow-speed bus 224 mav support two or more such busses, such as both an ISA bus and a PCMCIA bus One or more bus devices may be attached to slow-speed bus 224.
• ISA Industn Standard Architecture
• PCMCIA PC Card
• bus devices normally pertorm functions that do not lequire as much bandwidth to the svstem memon 222 as the CPU 202 and graphics controller 212 require Such bus devices mav include disk drive controllers, such as a SCSI controller, network controllers modems, and other I/O devices
• high-speed ' referring to high-speed data bus 228 and slow-speed referring to slow-speed bus 224 are used onlv as terms tor comparison
• high-speed bus 228 mav operate at 33 MHz.
• slow-speed bus 224 operates at 8 MHz
• the rate at which data could be transferred would be roughly lour times as great on high-speed data bus 228 as on slow-speed bus 224
• PC Cores Registers 208 includes va ⁇ ous control and functional units tvpicallv found in modern computer sv stems
• PC Cores Registers 208 mav include a programmable interrupt controller, a programmable intenal timer, a real tune clock a UART, a keyboard controller, a parallel port controller, and/or other registers and tunctions required tor the desired personal computer compatibility
• the functional units located ⁇ lthin PC ores/Registers 208 are connected to the computer system through an 8-bit data bus which allows access bv CPU 202
• controller tunctions which provide control signals tor the slow-speed bus 224 For example.
• PC cores/register 208 mav include an ISA controller and/or a PCMCIA controller Furthermore, tor portable and low-power computer applications.
• PC Cores/Registers 208 mav include a power management unit All of the functional units desc ⁇ bed above as included in PC Cores/Registers 208 may be functionally similar or equivalent to such functions tvpicallv found in PC tvpe computer svstems
• FIG 3 a block diagram showing a more detailed illustration ot the data paths in computer sv stem 200 is shown
• CPU 202 is coupled to the data stee ⁇ ng logic 220 bv tour 8-bit data bvte lanes 302 1 hese bvte lanes 302 torm the 32 bit CPU data bus PC Cores/Registers 208 is coupled to data stee ⁇ ng logic 220 bv an 8-bit data bus 304
• Data stee ⁇ ng logic 220 is also coupled to the high-speed data bus 228 which comprises tw o 8-bit bvte lanes to torm a 16-bit data path
• Data steering logic 220 mav also pertorm necessan byte gathermg and/or bvte lane stee ⁇ ng
• An unportant aspect ol the data steermg logic in the present mvention is the ability to allow tor CPU and DMA data transters to be performed concurrent with graphics controller data transters For mstance.
• the CPU 202 mav execute trom a ROM or FLASH device on the slow-speed bus 224 while the graphics controller accesses unified svstem memon 222
• Data steermg logic 220 mav couple the CPU data bus 302 to the slow-speed data bus 306 as illustrated bv path 312 Data steermg. as shown bv path 312 in data steermg logic 220.
• data steermg path 314 allows data transters between CPU 202 and the various PC Cores/Registers 208 to be performed concurrentlv with data transters between graphics controller 212 and unified svstem memon 222 Also.
• DMA ti ansters mav occur through path 316 between unified svstem memory 222 and devices located on slow-speed bus 224.
• data steermg logic 220 provides data connections that allow data translcr operations to continue between svstem components du ⁇ ng tunes when graphics controller 212 is accessing unified system memon 222 Therefore, the overall computer system performance is enhanced Reter ⁇ ng back to Fig 2.
• data stee ⁇ ng logic 220 is controlled bv control signals generated m control logic 216
• Control ot data stee ⁇ ng logic 220 is a function ot the result ot the arbitration svstem comprising svstem arbiter 210 and memon arbiter 218 This arbitration system is further descnbed below
• Sv stem arbiter 210 arbitrates between CPU 202 and DMA controller 206 for access to the svstem memon 222 For svstem arbiter 210.
• the CPU 202 is the default bus owner DMA controller 206 requests bus access bv asserting the HRQ signal to svstem arbiter 210 To obtam bus access tor DMA controller 206 the s ⁇ stem arbiter 210 asserts the HOLD signal to CPU 202 When the CPU 202 finishes its cu ⁇ ent transaction, it asserts the HLD ⁇ signal to the svstem arbiter 210 to indicate that it is relinquishing control ol the bus Sv stem arbiter 210 then asserts the bus request to the memon arbiter 218
• Memory arbiter 218 arbitrates between the winner (DMA controller 206 or CPU 202) trom svstem arbiter 210 and graphics controller 212 for access to the unified svstem memon 222 on high-speed data bus 228 I hus. a device cannot obtam access to unified svstem memon 222 until both levels of arbitration ha e been completed and the device receives a bus grant mdication
• Graphics controller 212 is given p ⁇ o ⁇ tv over requests trom the CPU 202 or DMA controller 206 in order to ensure that a glitch tree screen display is mamtained Graphics controller 212 asserts the VREQ to memon arbiter 218 in order to request access to svstem memon 222 It high-speed data bus 228 is currentlv idle, then memon arbiter 218 w ill assert the VGNT signal to graphics controller 222. and then assert the
• SEL GRAPHICS signal to the control logic 216. in order to mdicate that the graphics controller 212 should be granted access to high-speed data bus 228 If high-speed data bus 228 is not idle when graphics controller 212 asserts the VREQ signal then memory arbiter 218 waits until the current transaction is completed on high-speed data bus 228. then removes bus ownership trom the current bus owner and asserts the VGNT signal to award bus ownership to graphics controller 212
• CPU 202, graphics controller 212. and DMA controller 206 all compete for access to the unified system memory 222 through the high-speed data bus 228. Since only one of these devices may access the unified memory 222 through the high-speed data bus 228 at a time, performance is greatly enhanced by data steering logic 220. which allows the CPU and DMA controller to perform data transactions with devices on slow-speed bus 224 or PC Cores/Registers 208 concurrent with data transfers performed between graphics controller 212 and system memory 222.
• the CPU 202. DMA controller 206 and graphics controller 212 will all need to access unified system memory 222 frequently so that one or more of these devices will be waiting for access to the unified system memory 222.
• a preferred embodiment of the present invention includes a cache 204 within CPU 202.
• Cache 204 allows CPU 202 to continue operations during times that graphics controller 212 has ownership of high-speed data bus 228.
• Cache 204 has a small high-speed memory which stores copies of data stored in unified system memory 222.
• CPU 202 can read the data stored in cache 204 without needing to access unified system memory 222 as long as the desired data is present within cache 204. When the desired data is not present within cache 204. then CPU 202 must compete for access to the high-speed data bus 228 by way of the arbitration system described above.
• Cache 204 improves overall system performance by providing another source of transaction concurrency.
• CPU 202 may access data stored within cache 204 concurrently with graphics controller 212 or DMA controller 206 accessing data stored within unified system memory 222. since CPU accesses to the cache 204 do not involve the high-speed data bus 228.
• the range of data accessed by graphics controller 212 within unified system memory 222 may be configured as noncacheable or as write-through cacheable.
• the arbitration and control logic (system arbiter 210. memory arbiter 218 and control logic 216) must accommodate snoops of the cache 204 during the beginning of DMA cycles which are targeted to data stored within unified system memory 222. for embodiments employing a write-back cache for cache 204.
• the system arbiter 210 will back off DMA controller 206 and allow write-back cache 204 to update the memory location in unified system memory 222 with the correct data. Thereafter, system arbiter 210 will allow DMA controller 206 to proceed with the DMA transfer.
• FIFO 214 is a "first in, first out " memory device that acts as a buffer between graphics controller 212 and the unified system memory 222.
• graphics controller 212 may rapidly fill FIFO 214 with screen image data accessed from unified system memory 222.
• graphics controller 212 may then relinquish high-speed data bus 228 so that CPU 202 or DMA controller 206 may access the unified system memory 222.
• graphics controller 212 relinquishes control of highspeed data bus 228 it operates on data out of FIFO 214.
• FIFO 214 may be optimized to maximize performance.
• graphics controller 212 may perform data transfers to fill FIFO 214.
• FIFO 214 may be sized so that bus latency is minimized without interrupting screen refreshes.
• FIFO 214 within graphics controller 212 enhances overall system concurrency by allowing graphics controller 212 to access data from FIFO 214 while DMA controller 206 or CPU 202 concurrently accesses data in unified system memory 222.
• CMOS complementary metal-oxide-semiconductor
• CPU 202 DMA controller 206.
• PC Cores Registers 208 system arbiter 210.
• control logic 216 including memory arbiter 218, and data steering logic 220 may be integrated into a single integrated circuit device.
• An integrated circuit device as represented by dotted-line 240 is suitable for computer systems requiring low-power, low-cost and low-area implementations.
• the improved bus concurrency of the present invention provided by arbitration logic 210. 218 and data steering logic 220. combined with the use of unified system memory 222. allows the functional units shown in Fig. 2 within dotted-line 240 to be integrated into a single low-cost device without sacrificing performance.
• a low-cost integrated circuit device is obtained because only a single data interface to memory 222 is required, and thus only one memory control unit is required within control logic 216. Therefore, the overall external pin count and gate size of the integrated circuit device represented by dotted-line 240 is decreased compared to traditional computer architectures utilizing a separate graphics memory.
• the improved bus concurrency of the present invention allows overall system performance to be maintained nearer the levels of traditional computer architectures. Therefore, an integrated circuit device 240 according to the present invention may be suitable for high performance applications utilizing various modern operating systems.
• integrated circuit device 240 couples to 16-bit high-speed data bus 228 and 16-bit slow-speed bus 224.
• integrated circuit device 240 may be optionally configured to combine data bus 228 and the data portion of bus 224 into a 32 bit data bus to support access to 32-bit memory and/or access to 32 bit peripheral busses, such as the VL bus or Peripheral Component Interconnect (PCI) bus.
• VL bus Peripheral Component Interconnect
• Fig. 5 illustrates a configuration of integrated circuit device 240 where data bus 228 and a data portion of bus 224 are combined to provide a 32-bit interface.
• the graphics controller 212 within integrated circuit device 240 is disabled because the concurrent operations described above may no longer be performed since the full 32-bit data bus is required for all accesses to system memory 502.
• the two data buses 224 and 228 are combined to provide 32-bit access to 32-bit memory 502.
• the combined data buses 224 and 228 may support a 32-bit peripheral bus 508.
• Peripheral bus 508 may support bus devices according to standard bus specification such as the VL bus or the Peripheral Component Interconnect (PCI) bus.
• PCI Peripheral Component Interconnect
• a slower bus 506 may be supported in this configuration.
• the slower bus 506 may also support a standard bus specification such as the Industry Standard Architecture (ISA) bus or Personal Computer Memory Card International Association (PCMCIA) bus.
• Transceiver 504 may be required to buffer slower speed bus 506 from data bus 224 because of loading requirements.
• Transceiver 504 may also be required to isolate slower speed bus 506 during certain operations to prevent bus contention. It will be appreciated to those skilled in the art having the benefit of this disclosure that this invention is believed to be capable of achieving a low-cost, low-area computer system with improved bus concurrency.
• the form of the invention shown and described is to be taken as exemplary, presently prcl ' e ⁇ ed embodiments. Various modifications and changes may be made without departing from the spirit and scope of the invention as set forth in the claims. It is intended that the following claims be interpreted to embrace all such modifications and changes.

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• 1997
  • 1997-04-14 US US08/837,120 patent/US5941968A/en not_active Expired - Lifetime
• 1998
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