WO1998042009A1 - Procede pour produire un dispositif a circuit integre a semi-conducteur - Google Patents

Procede pour produire un dispositif a circuit integre a semi-conducteur Download PDF

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Publication number
WO1998042009A1
WO1998042009A1 PCT/JP1997/000810 JP9700810W WO9842009A1 WO 1998042009 A1 WO1998042009 A1 WO 1998042009A1 JP 9700810 W JP9700810 W JP 9700810W WO 9842009 A1 WO9842009 A1 WO 9842009A1
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WO
WIPO (PCT)
Prior art keywords
integrated circuit
circuit device
manufacturing
semiconductor integrated
film
Prior art date
Application number
PCT/JP1997/000810
Other languages
English (en)
Japanese (ja)
Inventor
Shinji Nishihara
Shuji Ikeda
Naotaka Hashimoto
Hiroshi Momiji
Hiromi Abe
Shinichi Fukada
Masayuki Suzuki
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to CNB971820252A priority Critical patent/CN1146959C/zh
Priority to KR10-2004-7007841A priority patent/KR20040053359A/ko
Priority to KR1019997008290A priority patent/KR100563503B1/ko
Priority to PCT/JP1997/000810 priority patent/WO1998042009A1/fr
Priority to US09/380,735 priority patent/US6693001B2/en
Priority to AU19405/97A priority patent/AU1940597A/en
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority claimed from CNB971820252A external-priority patent/CN1146959C/zh
Publication of WO1998042009A1 publication Critical patent/WO1998042009A1/fr
Priority to US11/006,702 priority patent/US7214577B2/en
Priority to US11/783,187 priority patent/US7314830B2/en
Priority to US11/950,152 priority patent/US7553766B2/en
Priority to US12/492,276 priority patent/US8034715B2/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a manufacturing technology of a semiconductor integrated circuit device, and particularly to a technology effective when applied to a salicide (Salicide; self-aligned silicide) process using a Co (cobalt) film formed by a sputtering method. It is about. Background art
  • refractory metal (silicide) films for electrodes and wiring are formed on a semiconductor wafer by sputtering a target made by sintering a refractory metal (silicide) powder in argon. You.
  • Japanese Unexamined Patent Publications Nos. 6-192,974, 6-192,799 and 7-34886 describe impurities, particularly Ni (nickel) and Fe ( It discloses a technique for producing high-purity Co with a purity of 99.999% (5N) or more by reducing the content of iron) by electrolytic refining. These high-purity Cos are applied to the production of Co targets for forming Co films used for electrodes and wiring (electrodes, gates, wiring, elements, protective films) of semiconductor devices. You.
  • Japanese Patent Application Laid-Open No. Hei 5-137700 discloses a method of manufacturing a high melting point metal silicide target for sputtering that can suppress generation of particles that cause disconnection or short circuit of electrodes and wiring.
  • the high melting point metal include W, Mo (molybdenum), Ta (tantalum), Ti, Co, and Cr (chromium).
  • the refractory metal silicide film can be formed by using the refractory metal silicide target as described above or by reacting the refractory metal film with silicon.
  • Japanese Patent Application Laid-Open No. 7-321069 uses a composite metal target composed of 20 atom% of a ferromagnetic material such as Co and 80 atom% of a paramagnetic material such as Ti.
  • a magnetron 'sputtering method formed a Co-Ti film on the entire surface of the semiconductor substrate on which the metal oxide semiconductor field effect transistor (MFETSFET) was formed.
  • MFETSFET metal oxide semiconductor field effect transistor
  • the present inventors have studied the introduction of a salicide process for forming a low-resistance high-melting-point metal silicide layer on a polycrystalline silicon gate and on a source and a drain as a measure for increasing the speed of a MOS FET.
  • the high melting point metal material Co was selected, which can provide a low resistance silicide of about 15 ⁇ cm.
  • the threshold voltage As a countermeasure, a dual gate in which the gate electrode of a p-channel MOSFET is made of p-type polycrystalline silicon to be a surface channel type, and the gate electrode of an n-channel MOSFET is made of n-type polycrystalline silicon and is a surface channel type The introduction of a CMOS structure was considered.
  • the above-mentioned salicide method for forming a silicide layer on a polycrystalline silicon gate is problematic in the connection method between the p-type polycrystalline silicon gate and the n-type polycrystalline silicon gate. This problem can be solved by combining this with a process.
  • the process for forming the Co silicide layer on the polycrystalline silicon gate and the source and drain of the MOS FET is as follows.
  • a Co film is deposited on a semiconductor substrate on which a MOS FET is formed by a sputtering method using a Co target. Then, heat treatment allows Co and Si to react with each other. A Co silicide layer is formed on the surface (first heat treatment).
  • the Co silicide obtained at this time is monosilicide (CoSi) having a relatively high resistance of 50 to 60 ⁇ cm.
  • the substrate is again heat-treated to cause the monosilicide to undergo a phase transition to low-resistance disilicide (CoSi 2 ) (second heat treatment).
  • the present inventor performed the first heat treatment on the Co film formed using a 99.9% pure Co target, and found that the obtained Co monosilicide (Co Si) layer
  • the film thickness was highly dependent on the temperature change of the heat treatment. Specifically, a phenomenon was observed in which the higher the heat treatment temperature, the thicker the film thickness, and the lower the heat treatment temperature, the thinner the film thickness, and it was difficult to control the film thickness stably. It is considered that such a variation in the film thickness is mainly caused by silicidation of some of the impurity transition metals such as Fe and Ni contained in the Co target.
  • the thickness of the monosilicide layer is reduced by setting the first heat treatment temperature lower to avoid an increase in junction leakage current, the resistance of the silicide layer increases. Further, when the heat treatment temperature is low, the progress of the silicidation reaction is slowed, so that the resistance of the side layer is further increased. Furthermore, as the thickness of the Co silicide layer becomes thinner, its heat resistance decreases. Therefore, a heat treatment step after OS FET formation (for example, P (phosphorus) for gettering a metal such as Na (sodium)). A process of depositing a doped silicon oxide film on top of the MOS FET and then crystallizing the silicon oxide film at a high temperature) causes the co-silicide crystal grains to aggregate (agglomeration), resulting in abnormal resistance. It may increase.
  • OS FET formation for example, P (phosphorus) for gettering a metal such as Na (sodium
  • a method for manufacturing a semiconductor integrated circuit device includes the following steps (a) to (d).
  • the method of manufacturing a semiconductor integrated circuit device when forming a CoSi 2 layer on the surface of silicon by the reaction of Co and Si, has at least a small first heat treatment temperature dependency and a film thickness.
  • the sheet resistance of the Co Si 2 layer should be 10 ⁇ / port or less. It is.
  • the high-purity Co target used in the present invention has a Co purity of at least 99.99% and a Fe or Ni content of 10 ppm or less, or a Fe and Ni content of 50 ppm or less. It is. More preferably, the purity of Co is 99.99% or more, and the content of Fe and Ni is 10 ppm or less. Use with a purity of 99.999%.
  • the term “wafer” refers to a single or multiple single-crystal regions (here, mainly silicon) after at least a certain step of manufacturing a semiconductor integrated circuit device mainly in a surface region thereof. )
  • the “semiconductor integrated circuit device” includes not only a device formed on a normal single crystal wafer but also a device formed on another substrate such as a TFT liquid crystal.
  • a method for manufacturing a semiconductor integrated circuit device includes the following steps:
  • the Co target has a Co purity of 99.99% or more and a Fe or Ni content of 10 ppm or less.
  • the Co purity power S of the Co target is 99.99% or more, and the contents of Fe and Ni are 50 ppm or less.
  • the Co target has a Co purity of 99.99% or more and Fe and Ni contents of 10 ppm or less.
  • the Co target has a Co purity of 99.999%.
  • the temperature of the first heat treatment is 475 : C to 525 ° C.
  • the temperature of the second heat treatment is 650 ° C. to 800 ° C. C.
  • the Co film has a thickness of 18 to 60 bodies.
  • a sheet resistance of the Co silicide layer after performing the second heat treatment is 10 ⁇ / port or less.
  • a junction depth of the source and the drain is 0.3 ⁇ m or less.
  • a method of manufacturing a semiconductor integrated circuit device of the present invention includes the following steps;
  • the operating power supply voltage of the MOSFET is 2 V or less.
  • the Co target has a Co purity of 99.99% or more and a Fe or Ni content of 10 ppm or less.
  • the Co target has a Co purity of 99.99% or more, and a content of Fe and Ni is 50 ppm or less.
  • the Co target has a Co purity of 99.99% or more, and a content of Fe and Ni is 10 ppra or less.
  • the Co target has a Co purity of 99.999%.
  • the method for manufacturing a semiconductor integrated circuit device of the present invention includes the following steps:
  • the silicon oxide film doped with the impurity is a PSG film.
  • the temperature of the third heat treatment is 700 ° C to 800 ° C.
  • An object of the present invention is to provide a salicide process capable of forming a Co silicide layer having low resistance and low junction leakage current.
  • FIG. 9 to FIG. 12 are cross-sectional views of a main part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.
  • 8 is a graph showing the relationship between the heat treatment at 750 eC for 30 minutes for activating the impurity and the leakage current of the source and drain formed by this impurity
  • Fig. 10 is the sputtering used for depositing the Co film.
  • Schematic diagram of the chamber of the device Fig. 11 is a perspective view of the Co target
  • Fig. 14 is an n-channel MOS FET and p-channel type with Co silicide layers formed on the gate electrode, source and drain surfaces.
  • Enlarged view of MOS FET Figure 15 shows sheet resistance of Co silicide layer and first heat treatment temperature 6 is a graph showing a relationship with the graph.
  • This embodiment is applied to a dual-gate CMOS process in which the design rule is 0.25 ⁇ m and the operating power supply voltage is 2 V, but the present invention is limited by this embodiment. Of course, it is not.
  • a CMO SFET with a dual-gate structure To form a CMO SFET with a dual-gate structure, first, as shown in Fig. 1, the surface of a semiconductor substrate 1 made of p-type single-crystal silicon having a specific resistance of about 10 ⁇ era is thermally oxidized to form a film. After the silicon oxide film 2 on the thigh is formed, a silicon nitride film 3 having a thickness of 100 nm is deposited on the silicon oxide film 2 by a CVD method. Next, the silicon nitride film 3 is patterned by dry etching using a photoresist as a mask to remove the silicon nitride film 3 in the element isolation region.
  • the surface thereof is flattened by the CMP method, and the silicon oxide film 5 is The element isolation groove 4 is formed by leaving the trench.
  • a heat treatment of 100 Ot: is performed to densify the silicon oxide film 5 inside the element isolation trench 4, and then the silicon nitride film 3 is removed by wet etching using hot phosphoric acid.
  • an n-type well 6 n and a p-type well 6 p are formed on the semiconductor substrate 1.
  • an impurity for forming an n-type well is ion-implanted into the semiconductor substrate 1 using a photoresist in which a region for forming a p-channel type MOSFET is opened as a mask.
  • an impurity for adjusting the value voltage is ion-implanted.
  • an impurity for forming an n-type well for example, P (phosphorus) is used, and ion implantation is performed at an energy of 360 keV and a dose of 1.5 ⁇ 10 13 / cm 2 .
  • the impurity for adjusting the threshold voltage for example, P is used, and ions are implanted at an energy of 40: keV and a dose of 2 ⁇ 10 I2 / cm 2 .
  • an impurity for forming a p-type well in the semiconductor substrate 1 is ion-implanted in the semiconductor substrate 1 using the photoresist in which an n-channel M ⁇ SFET formation region is opened as a mask.
  • an impurity for adjusting the threshold voltage of the n-channel MOSFET is ion-implanted.
  • impurity for adjusting the threshold voltage for example, boron fluoride (BF 2 ) is used, and ion implantation is performed at an energy of 40 keV and a dose of 2 ⁇ 10 / c ni 2 .
  • the semiconductor substrate 1 is heat-treated at 950 for 1 minute to activate the impurities, thereby forming the n-type well 6n and the p-type well 6p.
  • the semiconductor substrate 1 was thermally oxidized to form a 4 nm-thick gate oxide film 7 on the surface of each of the active regions of the n-type well 6 n and the p-type well 6 p. Thereafter, a 250-nm-thick polycrystalline silicon film 8 is deposited on the semiconductor substrate 1 by the CVD method, and a silicon oxide film 9 is deposited on the polycrystalline silicon film 8 by the CVD method. Neither n-type impurities nor p-type impurities are doped into this polycrystalline silicon film 8.
  • the gate electrode of the n-channel MOSFET is formed on the p-type well 6 p.
  • 8 n is formed, and a gate electrode 8 p of p-channel type MOSFET is formed on the n-type well.
  • the gate electrode 8 n and the gate electrode 8 p are formed with a gout length of 0.25 ⁇ m.
  • the photoresist and the gate electrode 8 n are used as masks, and the p-type well 6 p has an energy of 20 keV, a dose of 3.0 X 10 "/ cm 2 and an n-type impurity (arsenic (A
  • the semiconductor substrate 1 is heat-treated at 100 ° C.
  • n-type well 6 n on both sides of the gate electrode 8 p is p-doped.
  • -Type semiconductor region 10 is formed, on both sides of gate electrode 8 n
  • An n-type semiconductor region 11 is formed in the p-type well 6 p of the semiconductor device.
  • a side wall spacer 12 having a thickness in the gate length direction of 0.1 / m is formed on the side walls of the gate electrodes 8 n and 8 p.
  • the sidewall spacers 12 are formed by anisotropically etching a silicon oxide film deposited on the semiconductor substrate 1 by a CVD method by a reactive ion etching method. When this etching is performed, the silicon oxide film 9 above the gate electrodes 8n and 8p is also etched to expose the surfaces of the gate electrodes 8n and 8p.
  • p-type impurities (B) are ion-implanted into the n-type well 6 n and the gate electrode 7 at an energy of 20 keV and a dose of 1.0 ⁇ 10 ′′ / cm 2.
  • p-type impurity (B) energy 5 ke V, a dose -. 2.
  • the semiconductor substrate By activity the 1 000 ° C, 1 0 seconds heat treatment to the impurities, Gate electrode to form a p f-type semiconductor region 1 3 to n-type Ueru 6 n 8 Change the conductivity type of p to p-type. Also, an n + -type semiconductor region 14 is formed in the p-type well 6 p and the conductivity type of the gate electrode 8 n is made n-type.
  • the p ⁇ type semiconductor region 13 and the n + type semiconductor region 14 are formed at a junction depth of 2 to 0.1 ⁇ m, respectively.
  • the semiconductor substrate 1 Prior to the heat treatment (1000, 10 seconds), the semiconductor substrate 1 is heat-treated at 750 ° C. for 30 minutes to reduce the ( ⁇ ⁇ / ⁇ ) junction leakage of the n + type semiconductor region 14 as shown in FIG. It can be reduced. This is because the point defect introduced into the semiconductor substrate 1 at the time of ion implantation is recovered by this heat treatment.
  • first heat treatment for 750 30 minutes is performed immediately after ion implantation for forming the type semiconductor region 14, and then ion implantation for forming the ⁇ ′-type semiconductor region 13.
  • a 15 nm-thick Co film 16 is deposited on the semiconductor substrate 1 by sputtering using a Co target, and a 10- to 15-nm-thick oxidation prevention film is formed on the Co film 16.
  • Film 17 is deposited.
  • the antioxidant film 17 uses, for example, TiNs deposited by a sputtering method. Same.
  • the thickness of the film 16 is preferably in the range of 18 to 60 employment. When the film thickness is less than 18 nm, it is difficult to reduce the sheet resistance of the Co silicide layer to] .0 ⁇ / port or less, and when the film thickness is more than 60 plates, the source and drain junction leakage currents increase.
  • FIG. 10 is a schematic view of a chamber of a sputtering apparatus used for depositing the Co film 16.
  • the inside of the chamber 100 is evacuated to a vacuum. During film formation, Ar gas is introduced and the pressure is maintained at about several mTorr.
  • a Co target 1.03 held by a sputter electrode 102 is arranged to face the semiconductor substrate 1.
  • the sputter power supply 104 connected to the Co target 103 is activated to start a steady discharge, the negative high voltage applied to the Co target 103 causes the C Plasma 105 is formed in the gap between 3 and semiconductor substrate 1.
  • FIG. 11 is a perspective view of the C 0 target 103.
  • the Co target 103 used in the present embodiment has a Co purity of at least 99.9% or more and a Fe or Ni content of] .0 ppm or less, or Fe and Ni. Ni content is 50 ppm or less. More preferably, those having a Co purity of 99.9% or more and Fe and Ni contents of 10 ppm or less, more preferably those having a Co purity of 99.999%. use.
  • Such a high-purity Co target 103 is prepared by sintering the raw material Co powder, which has been refined by using an electrolysis method or the like until the above-mentioned Co purity is obtained, by hot pressing, for example, into a disk shape. Manufactured by mechanical processing.
  • a first heat treatment for reacting Co with Si is performed.
  • a CoSi layer 16a is formed on each surface of the p + type semiconductor region 13, the n + type semiconductor region 14, and the gate electrodes 8n, 8P.
  • the first heat treatment is performed for about 30 seconds in a nitrogen atmosphere at a substrate temperature of 525: C or lower using a rapid thermal annealing (RTA) apparatus.
  • RTA rapid thermal annealing
  • the substrate temperature is preferably set to at least 475 or more.
  • FIG. 13 by performing the second heat treatment, the CoSi layer 16 a undergoes a phase transition to the CoSi 2 layer 16 b.
  • the second heat treatment is performed in a nitrogen atmosphere at a substrate temperature of 650 to 800 C for about 0.1 minute using an RTA apparatus.
  • C o S i 2 layer 16 n channel-type was formed b MOSFET and enlarged view of a p-channel type MOSFET to the respective surfaces of the source and drain, 1 5
  • C o S i 2 layers 16 is a graph showing the relationship between the sheet resistance of 16b and the first heat treatment temperature.
  • a high-purity product (target B) having a Co purity of 99.998% and a low-purity product (target A) having a 99.9% purity were used as the Co target.
  • Table 1 shows the impurity species and their contents in Targets 8 and B. Table 1 (Unit: Weight pm
  • the CoSi; layer 16b obtained from the high-purity target B having a purity of 99.998% has a small first heat treatment temperature dependence of the CoSi layer 16a, Since the temperature becomes almost uniform in this temperature range, a low sheet resistance of about 4 ⁇ / port was obtained throughout this temperature range.
  • the heat treatment temperature when the heat treatment temperature was low, the sheet resistance of the CoSi 2 layer obtained from the target A having a purity of 99.9% was significantly increased because the thickness of the Co film was small. Further, in order to obtain the same sheet resistance as the CoSi 2 layer obtained from the high-purity target B, the first heat treatment temperature had to be increased to 60 O'C.
  • the purity of the Co is 99.9.
  • the content of Fe and Ni is 9% or more. Since a Co silicide layer 16b with low junction leakage current can be obtained with a resistor, high-speed, high-performance, and low-power consumption devices using a fine CMO SFET with a gate length of 0.25 ⁇ m can be obtained. Can be promoted.
  • a 100-nm-thick silicon oxide film 18 is deposited on the semiconductor substrate 1 by a normal pressure CVD method, and then a thickness of 300 to 50 nm is formed by a plasma CVD method.
  • a 0-nm silicon oxide film 19 is deposited, the silicon oxide film] .9 is polished by a chemical mechanical polishing (CMP) method to flatten the surface.
  • CMP chemical mechanical polishing
  • the water in the PSG film 20 is removed.
  • Heat treatment (sintering) is performed in the temperature range of 700 to 800 ° C.
  • the film thickness of the CoSi 2 layer 16b can be sufficiently ensured, the aggregation of the CoSi 2 layer 16b is suppressed even when high-temperature sintering is performed. Therefore, it is possible to prevent an increase in the sheet resistance of the Co Si 2 layer 16 b, and Process margin can be improved.
  • FIG. 1 As shown in 7, PSG film 2 0 by a photo registry to mask, oxidation silicon film 1 9, by etching the .1 8, p ⁇ type semiconductor region 1 3 and After forming a connection hole 21 on each of the type semiconductor regions 14, a first layer wiring 22 is formed on the PSG film 20.
  • a thin first TiN film is deposited on top of the PSG film 20 by CVD, a thick W film is deposited on top of it, and the W film is etched back. And leave it inside the connection hole 2 1.
  • the second TN film, the A1 film and the second film are formed using a photoresist as a mask.
  • a first interlayer insulating film 23 is formed on the first layer wiring 22 and the surface thereof is planarized by a chemical mechanical polishing method.
  • a connection hole 24 is formed in the film 23.
  • a second-layer wiring 25 is formed on the first interlayer insulating film 23, so that the second-layer wiring 25 and the first-layer wiring 22 are electrically connected.
  • the first interlayer insulating film 23 is made of a silicon oxide film deposited by a plasma CVD method, and the second layer wiring 25 is made of the same material as the first layer wiring 22.
  • a second inter-layer insulating film 26 is formed on the second layer wiring 25 in the same manner as described above, and the surface flatness and the connection holes 27 are formed. After that, a third-layer wiring 28 is formed on the second interlayer insulating film 26.
  • a third interlayer insulating film 29 is formed on the third layer wiring 25, and after the surface is flattened and the connection holes 30 are formed, the third interlayer insulating film 29 is formed.
  • a fourth-layer wiring 31 is formed on the film 29, and a fourth interlayer insulating film 32 is formed on the fourth-layer wiring 31. The surface is flattened and the connection hole 33 is formed.
  • the fifth layer wiring 34 is formed on the fourth interlayer insulating film 32, whereby the semiconductor integrated circuit device of the present embodiment is almost completed.
  • the manufacturing method of the present invention using a high-purity Co target is, for example, an M ⁇ SFET. It can be applied to the case where only the source and drain surfaces are to be silicified with Co. Industrial applicability
  • the controllability of the thickness of the Co silicide layer is improved, and a Co silicide layer having low resistance and low junction leakage current is obtained. Therefore, it is suitable to be applied to a salicide process using a Co target.

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

On dépose une couche de Co sur la surface principale d'une plaquette par une méthode de pulvérisation qui utilise une cible en Co très pur ayant une pureté en Co supérieure ou égale à 99,99 %, de préférence à 99,999 %, et une teneur en Fe et Ni inférieure ou égale à 10 ppm. La couche de Co déposée est transformée en couche de siliciure de Co qui est en contact ohmique avec l'électrode grille, la source et le drain d'un transistor MOS à faible résistance, et qui produit peu de courant de fuite.
PCT/JP1997/000810 1997-03-14 1997-03-14 Procede pour produire un dispositif a circuit integre a semi-conducteur WO1998042009A1 (fr)

Priority Applications (10)

Application Number Priority Date Filing Date Title
KR10-2004-7007841A KR20040053359A (ko) 1997-03-14 1997-03-14 반도체 집적 회로 장치의 제조 방법
KR1019997008290A KR100563503B1 (ko) 1997-03-14 1997-03-14 반도체 집적 회로 장치의 제조 방법
PCT/JP1997/000810 WO1998042009A1 (fr) 1997-03-14 1997-03-14 Procede pour produire un dispositif a circuit integre a semi-conducteur
US09/380,735 US6693001B2 (en) 1997-03-14 1997-03-14 Process for producing semiconductor integrated circuit device
AU19405/97A AU1940597A (en) 1997-03-14 1997-03-14 Process for producing semiconductor integrated circuit device
CNB971820252A CN1146959C (zh) 1997-03-14 1997-03-14 制造半导体集成电路器件的方法
US11/006,702 US7214577B2 (en) 1997-03-14 2004-12-08 Method of fabricating semiconductor integrated circuit device
US11/783,187 US7314830B2 (en) 1997-03-14 2007-04-06 Method of fabricating semiconductor integrated circuit device with 99.99 wt% cobalt
US11/950,152 US7553766B2 (en) 1997-03-14 2007-12-04 Method of fabricating semiconductor integrated circuit device
US12/492,276 US8034715B2 (en) 1997-03-14 2009-06-26 Method of fabricating semiconductor integrated circuit device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
PCT/JP1997/000810 WO1998042009A1 (fr) 1997-03-14 1997-03-14 Procede pour produire un dispositif a circuit integre a semi-conducteur
CNB971820252A CN1146959C (zh) 1997-03-14 1997-03-14 制造半导体集成电路器件的方法

Related Child Applications (3)

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US09380735 A-371-Of-International 1997-03-14
US09/380,735 A-371-Of-International US6693001B2 (en) 1997-03-14 1997-03-14 Process for producing semiconductor integrated circuit device
US10/721,902 Continuation US6858484B2 (en) 1997-03-14 2003-11-26 Method of fabricating semiconductor integrated circuit device

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002043564A (ja) * 2000-07-21 2002-02-08 Mitsubishi Electric Corp サリサイドトランジスタの製造方法、半導体記憶装置および半導体装置
US7078758B2 (en) 2003-02-21 2006-07-18 Renesas Technology Corp. Semiconductor device having memory and logic devices with reduced resistance and leakage current

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05102078A (ja) * 1990-06-08 1993-04-23 Intel Corp シリコン基板上に２つの層を形成させる方法及びシリコン基板上の接点領域の充填物を形成する方法
JPH05182982A (ja) * 1991-07-16 1993-07-23 Toshiba Corp 半導体装置およびその製造方法
JPH073486A (ja) * 1993-06-15 1995-01-06 Japan Energy Corp 高純度コバルト及びその製造方法
JPH0778788A (ja) * 1993-06-21 1995-03-20 Sony Corp 半導体装置における配線構造及び配線形成方法並びにｍｏｓ型トランジスタ

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05102078A (ja) * 1990-06-08 1993-04-23 Intel Corp シリコン基板上に２つの層を形成させる方法及びシリコン基板上の接点領域の充填物を形成する方法
JPH05182982A (ja) * 1991-07-16 1993-07-23 Toshiba Corp 半導体装置およびその製造方法
JPH073486A (ja) * 1993-06-15 1995-01-06 Japan Energy Corp 高純度コバルト及びその製造方法
JPH0778788A (ja) * 1993-06-21 1995-03-20 Sony Corp 半導体装置における配線構造及び配線形成方法並びにｍｏｓ型トランジスタ

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002043564A (ja) * 2000-07-21 2002-02-08 Mitsubishi Electric Corp サリサイドトランジスタの製造方法、半導体記憶装置および半導体装置
US7078758B2 (en) 2003-02-21 2006-07-18 Renesas Technology Corp. Semiconductor device having memory and logic devices with reduced resistance and leakage current
US7329575B2 (en) 2003-02-21 2008-02-12 Renesas Technology Corp. Semiconductor device and semiconductor device manufacturing method
US7919799B2 (en) 2003-02-21 2011-04-05 Renesas Electronics Corporation Semiconductor device and semiconductor device manufacturing method
US8058679B2 (en) 2003-02-21 2011-11-15 Renesas Electronics Corporation Semiconductor device and semiconductor device manufacturing method
US8492813B2 (en) 2003-02-21 2013-07-23 Renesas Electronics Corporation Semiconductor device and semiconductor device manufacturing method
US8647944B2 (en) 2003-02-21 2014-02-11 Renesas Electronics Corporation Semiconductor device and semiconductor device manufacturing method

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