WO1998029949A1 - Single-phase domino time borrowing logic with clocks at first and last stages and latch at last stage - Google Patents

Single-phase domino time borrowing logic with clocks at first and last stages and latch at last stage Download PDF

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Publication number
WO1998029949A1
WO1998029949A1 PCT/US1997/023372 US9723372W WO9829949A1 WO 1998029949 A1 WO1998029949 A1 WO 1998029949A1 US 9723372 W US9723372 W US 9723372W WO 9829949 A1 WO9829949 A1 WO 9829949A1
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WO
WIPO (PCT)
Prior art keywords
domino
stages
stage
circuit
coupled
Prior art date
Application number
PCT/US1997/023372
Other languages
English (en)
French (fr)
Inventor
Thomas D. Fletcher
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to JP53009898A priority Critical patent/JP2001507887A/ja
Priority to AU58006/98A priority patent/AU5800698A/en
Publication of WO1998029949A1 publication Critical patent/WO1998029949A1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
PCT/US1997/023372 1996-12-27 1997-12-17 Single-phase domino time borrowing logic with clocks at first and last stages and latch at last stage WO1998029949A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP53009898A JP2001507887A (ja) 1996-12-27 1997-12-17 最初と最後のステージにクロックを有し、最後のステージにラッチを有する単相ドミノ時間借用論理回路
AU58006/98A AU5800698A (en) 1996-12-27 1997-12-17 Single-phase domino time borrowing logic with clocks at first and last stages and latch at last stage

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US77368996A 1996-12-27 1996-12-27
US08/773,689 1996-12-27

Publications (1)

Publication Number Publication Date
WO1998029949A1 true WO1998029949A1 (en) 1998-07-09

Family

ID=25099007

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1997/023372 WO1998029949A1 (en) 1996-12-27 1997-12-17 Single-phase domino time borrowing logic with clocks at first and last stages and latch at last stage

Country Status (4)

Country Link
JP (1) JP2001507887A (ja)
KR (1) KR20000069742A (ja)
AU (1) AU5800698A (ja)
WO (1) WO1998029949A1 (ja)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6265899B1 (en) 1999-06-04 2001-07-24 S3 Incorporated Single rail domino logic for four-phase clocking scheme
EP1130780A2 (en) * 2000-02-29 2001-09-05 Kabushiki Kaisha Toshiba Semiconductor integrated circuit having logical operation function
US6496038B1 (en) 2000-06-30 2002-12-17 Intel Corporation Pulsed circuit topology including a pulsed, domino flip-flop
US6542006B1 (en) 2000-06-30 2003-04-01 Intel Corporation Reset first latching mechanism for pulsed circuit topologies
US6567337B1 (en) 2000-06-30 2003-05-20 Intel Corporation Pulsed circuit topology to perform a memory array write operation

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100684871B1 (ko) * 2004-07-02 2007-02-20 삼성전자주식회사 저전력 파이프라인 도미노 로직
KR20130106096A (ko) 2012-03-19 2013-09-27 삼성전자주식회사 슈도-스태틱 도미노 로직 회로와 이를 포함하는 장치들

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3518451A (en) * 1967-03-10 1970-06-30 North American Rockwell Gating system for reducing the effects of negative feedback noise in multiphase gating devices
US4040015A (en) * 1974-04-16 1977-08-02 Hitachi, Ltd. Complementary mos logic circuit
US5378942A (en) * 1993-06-03 1995-01-03 National Science Council CMOS dynamic logic structure
US5383155A (en) * 1993-11-08 1995-01-17 International Business Machines Corporation Data output latch control circuit and process for semiconductor memory system
US5402012A (en) * 1993-04-19 1995-03-28 Vlsi Technology, Inc. Sequentially clocked domino-logic cells
US5453708A (en) * 1995-01-04 1995-09-26 Intel Corporation Clocking scheme for latching of a domino output
US5550490A (en) * 1995-05-25 1996-08-27 International Business Machines Corporation Single-rail self-resetting logic circuitry
US5708374A (en) * 1995-08-21 1998-01-13 International Business Machines Corp. Self-timed control circuit for self-resetting logic circuitry

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3518451A (en) * 1967-03-10 1970-06-30 North American Rockwell Gating system for reducing the effects of negative feedback noise in multiphase gating devices
US4040015A (en) * 1974-04-16 1977-08-02 Hitachi, Ltd. Complementary mos logic circuit
US5402012A (en) * 1993-04-19 1995-03-28 Vlsi Technology, Inc. Sequentially clocked domino-logic cells
US5378942A (en) * 1993-06-03 1995-01-03 National Science Council CMOS dynamic logic structure
US5383155A (en) * 1993-11-08 1995-01-17 International Business Machines Corporation Data output latch control circuit and process for semiconductor memory system
US5453708A (en) * 1995-01-04 1995-09-26 Intel Corporation Clocking scheme for latching of a domino output
US5550490A (en) * 1995-05-25 1996-08-27 International Business Machines Corporation Single-rail self-resetting logic circuitry
US5708374A (en) * 1995-08-21 1998-01-13 International Business Machines Corp. Self-timed control circuit for self-resetting logic circuitry

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6265899B1 (en) 1999-06-04 2001-07-24 S3 Incorporated Single rail domino logic for four-phase clocking scheme
EP1130780A2 (en) * 2000-02-29 2001-09-05 Kabushiki Kaisha Toshiba Semiconductor integrated circuit having logical operation function
EP1130780A3 (en) * 2000-02-29 2003-08-13 Kabushiki Kaisha Toshiba Semiconductor integrated circuit having logical operation function
US6496038B1 (en) 2000-06-30 2002-12-17 Intel Corporation Pulsed circuit topology including a pulsed, domino flip-flop
US6542006B1 (en) 2000-06-30 2003-04-01 Intel Corporation Reset first latching mechanism for pulsed circuit topologies
US6567337B1 (en) 2000-06-30 2003-05-20 Intel Corporation Pulsed circuit topology to perform a memory array write operation

Also Published As

Publication number Publication date
AU5800698A (en) 1998-07-31
JP2001507887A (ja) 2001-06-12
KR20000069742A (ko) 2000-11-25

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Muralidharan et al. A literature survey and investigation of various high performance domino logic circuits

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