AU5800698A - Single-phase domino time borrowing logic with clocks at first and last stages and latch at last stage - Google Patents

Single-phase domino time borrowing logic with clocks at first and last stages and latch at last stage

Info

Publication number
AU5800698A
AU5800698A AU58006/98A AU5800698A AU5800698A AU 5800698 A AU5800698 A AU 5800698A AU 58006/98 A AU58006/98 A AU 58006/98A AU 5800698 A AU5800698 A AU 5800698A AU 5800698 A AU5800698 A AU 5800698A
Authority
AU
Australia
Prior art keywords
last
clocks
latch
time borrowing
phase domino
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU58006/98A
Inventor
Thomas D. Fletcher
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of AU5800698A publication Critical patent/AU5800698A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
AU58006/98A 1996-12-27 1997-12-17 Single-phase domino time borrowing logic with clocks at first and last stages and latch at last stage Abandoned AU5800698A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US77368996A 1996-12-27 1996-12-27
US08773689 1996-12-27
PCT/US1997/023372 WO1998029949A1 (en) 1996-12-27 1997-12-17 Single-phase domino time borrowing logic with clocks at first and last stages and latch at last stage

Publications (1)

Publication Number Publication Date
AU5800698A true AU5800698A (en) 1998-07-31

Family

ID=25099007

Family Applications (1)

Application Number Title Priority Date Filing Date
AU58006/98A Abandoned AU5800698A (en) 1996-12-27 1997-12-17 Single-phase domino time borrowing logic with clocks at first and last stages and latch at last stage

Country Status (4)

Country Link
JP (1) JP2001507887A (en)
KR (1) KR20000069742A (en)
AU (1) AU5800698A (en)
WO (1) WO1998029949A1 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6265899B1 (en) 1999-06-04 2001-07-24 S3 Incorporated Single rail domino logic for four-phase clocking scheme
JP3533357B2 (en) * 2000-02-29 2004-05-31 株式会社東芝 Semiconductor integrated circuit with logical operation function
US6542006B1 (en) 2000-06-30 2003-04-01 Intel Corporation Reset first latching mechanism for pulsed circuit topologies
US6567337B1 (en) 2000-06-30 2003-05-20 Intel Corporation Pulsed circuit topology to perform a memory array write operation
US6496038B1 (en) 2000-06-30 2002-12-17 Intel Corporation Pulsed circuit topology including a pulsed, domino flip-flop
KR100684871B1 (en) * 2004-07-02 2007-02-20 삼성전자주식회사 Low power pipelined domino logic
KR20130106096A (en) 2012-03-19 2013-09-27 삼성전자주식회사 Pseudo-static np domino logic circuit and apparatuses having the same

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3518451A (en) * 1967-03-10 1970-06-30 North American Rockwell Gating system for reducing the effects of negative feedback noise in multiphase gating devices
US4040015A (en) * 1974-04-16 1977-08-02 Hitachi, Ltd. Complementary mos logic circuit
US5402012A (en) * 1993-04-19 1995-03-28 Vlsi Technology, Inc. Sequentially clocked domino-logic cells
US5378942A (en) * 1993-06-03 1995-01-03 National Science Council CMOS dynamic logic structure
US5383155A (en) * 1993-11-08 1995-01-17 International Business Machines Corporation Data output latch control circuit and process for semiconductor memory system
US5453708A (en) * 1995-01-04 1995-09-26 Intel Corporation Clocking scheme for latching of a domino output
US5550490A (en) * 1995-05-25 1996-08-27 International Business Machines Corporation Single-rail self-resetting logic circuitry
US5565798A (en) * 1995-08-21 1996-10-15 International Business Machines Corporation Self-timed control circuit for self-resetting logic circuitry

Also Published As

Publication number Publication date
JP2001507887A (en) 2001-06-12
KR20000069742A (en) 2000-11-25
WO1998029949A1 (en) 1998-07-09

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