WO1998009804A1 - Flattening process for bonded semiconductor substrates - Google Patents

Flattening process for bonded semiconductor substrates Download PDF

Info

Publication number
WO1998009804A1
WO1998009804A1 PCT/US1997/013069 US9713069W WO9809804A1 WO 1998009804 A1 WO1998009804 A1 WO 1998009804A1 US 9713069 W US9713069 W US 9713069W WO 9809804 A1 WO9809804 A1 WO 9809804A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
thickness
wafer
layer
micrometers
Prior art date
Application number
PCT/US1997/013069
Other languages
English (en)
French (fr)
Inventor
Subramanian S. Iyer
William P. Downey
Original Assignee
Sibond L.L.C.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sibond L.L.C. filed Critical Sibond L.L.C.
Priority to EP97937023A priority Critical patent/EP0968081A4/en
Priority to JP10512644A priority patent/JP2001501368A/ja
Publication of WO1998009804A1 publication Critical patent/WO1998009804A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Element Separation (AREA)
PCT/US1997/013069 1996-09-04 1997-08-06 Flattening process for bonded semiconductor substrates WO1998009804A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP97937023A EP0968081A4 (en) 1996-09-04 1997-08-06 FLATTENING METHOD FOR LINKED SEMICONDUCTOR SUBSTRATES
JP10512644A JP2001501368A (ja) 1996-09-04 1997-08-06 接着した半導体基板の平坦化方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US71136096A 1996-09-04 1996-09-04
US08/711,360 1996-09-04

Publications (1)

Publication Number Publication Date
WO1998009804A1 true WO1998009804A1 (en) 1998-03-12

Family

ID=24857787

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1997/013069 WO1998009804A1 (en) 1996-09-04 1997-08-06 Flattening process for bonded semiconductor substrates

Country Status (5)

Country Link
EP (1) EP0968081A4 (ja)
JP (1) JP2001501368A (ja)
KR (1) KR20010029456A (ja)
TW (1) TW388078B (ja)
WO (1) WO1998009804A1 (ja)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0961314A1 (de) * 1998-05-28 1999-12-01 Wacker Siltronic Gesellschaft für Halbleitermaterialien Aktiengesellschaft Hochebene Halbleiterscheibe aus Silicium und Verfahren zur Herstellung von Halbleiterscheiben
WO2000072367A1 (en) * 1999-05-21 2000-11-30 Plasmasil, L.L.C. SEQUENCE OF OPERATIONS ON SILICON WAFERS
US6200908B1 (en) 1999-08-04 2001-03-13 Memc Electronic Materials, Inc. Process for reducing waviness in semiconductor wafers
WO2006031641A2 (en) * 2004-09-10 2006-03-23 Cree, Inc. Method of manufacturing carrier wafer and resulting carrier wafer structures
FR2888402A1 (fr) * 2005-07-06 2007-01-12 Commissariat Energie Atomique Procede d'assemblage de substrats par depot d'une couche mince de collage d'oxyde ou de nitrure et structure ainsi assemblee
EP1998367A3 (en) * 2007-05-30 2010-08-11 Shin-Etsu Chemical Company, Ltd. Method for manufacturing soi wafer
US7977211B2 (en) 2007-04-17 2011-07-12 Imec Method for reducing the thickness of substrates
EP3993074A1 (en) * 2020-11-03 2022-05-04 Corning Incorporated Substrate thining using temporary bonding processes
WO2022098607A1 (en) * 2020-11-03 2022-05-12 Corning Incorporated Substrate thining using temporary bonding processes
NL2027189B1 (en) * 2020-11-03 2022-06-27 Corning Inc Substrate thining using temporary bonding processes

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2857953B1 (fr) * 2003-07-21 2006-01-13 Commissariat Energie Atomique Structure empilee, et procede pour la fabriquer

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5218213A (en) * 1991-02-22 1993-06-08 Harris Corporation SOI wafer with sige
US5254830A (en) * 1991-05-07 1993-10-19 Hughes Aircraft Company System for removing material from semiconductor wafers using a contained plasma
US5494849A (en) * 1995-03-23 1996-02-27 Si Bond L.L.C. Single-etch stop process for the manufacture of silicon-on-insulator substrates

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05235312A (ja) * 1992-02-19 1993-09-10 Fujitsu Ltd 半導体基板及びその製造方法
JPH0750234A (ja) * 1993-08-04 1995-02-21 Komatsu Electron Metals Co Ltd 半導体ウェーハ製造装置および製造方法
JPH09252100A (ja) * 1996-03-18 1997-09-22 Shin Etsu Handotai Co Ltd 結合ウェーハの製造方法及びこの方法により製造される結合ウェーハ

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5218213A (en) * 1991-02-22 1993-06-08 Harris Corporation SOI wafer with sige
US5254830A (en) * 1991-05-07 1993-10-19 Hughes Aircraft Company System for removing material from semiconductor wafers using a contained plasma
US5494849A (en) * 1995-03-23 1996-02-27 Si Bond L.L.C. Single-etch stop process for the manufacture of silicon-on-insulator substrates

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP0968081A4 *

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0961314A1 (de) * 1998-05-28 1999-12-01 Wacker Siltronic Gesellschaft für Halbleitermaterialien Aktiengesellschaft Hochebene Halbleiterscheibe aus Silicium und Verfahren zur Herstellung von Halbleiterscheiben
WO2000072367A1 (en) * 1999-05-21 2000-11-30 Plasmasil, L.L.C. SEQUENCE OF OPERATIONS ON SILICON WAFERS
US6200908B1 (en) 1999-08-04 2001-03-13 Memc Electronic Materials, Inc. Process for reducing waviness in semiconductor wafers
WO2006031641A2 (en) * 2004-09-10 2006-03-23 Cree, Inc. Method of manufacturing carrier wafer and resulting carrier wafer structures
WO2006031641A3 (en) * 2004-09-10 2006-07-27 Cree Inc Method of manufacturing carrier wafer and resulting carrier wafer structures
US7393790B2 (en) 2004-09-10 2008-07-01 Cree, Inc. Method of manufacturing carrier wafer and resulting carrier wafer structures
WO2007006914A1 (fr) * 2005-07-06 2007-01-18 Commissariat A L'energie Atomique Procede d'assemblage de substrats par depot d'une couche mince de collage d'oxyde ou de nitrure
FR2888402A1 (fr) * 2005-07-06 2007-01-12 Commissariat Energie Atomique Procede d'assemblage de substrats par depot d'une couche mince de collage d'oxyde ou de nitrure et structure ainsi assemblee
US7977211B2 (en) 2007-04-17 2011-07-12 Imec Method for reducing the thickness of substrates
EP1998367A3 (en) * 2007-05-30 2010-08-11 Shin-Etsu Chemical Company, Ltd. Method for manufacturing soi wafer
US9064929B2 (en) 2007-05-30 2015-06-23 Shin-Etsu Chemical Co., Ltd. Method for reducing the thickness of an SOI layer
EP3993074A1 (en) * 2020-11-03 2022-05-04 Corning Incorporated Substrate thining using temporary bonding processes
WO2022098607A1 (en) * 2020-11-03 2022-05-12 Corning Incorporated Substrate thining using temporary bonding processes
NL2027189B1 (en) * 2020-11-03 2022-06-27 Corning Inc Substrate thining using temporary bonding processes

Also Published As

Publication number Publication date
EP0968081A4 (en) 2000-02-02
JP2001501368A (ja) 2001-01-30
KR20010029456A (ko) 2001-04-06
EP0968081A1 (en) 2000-01-05
TW388078B (en) 2000-04-21

Similar Documents

Publication Publication Date Title
US6004866A (en) Method for manufacturing bonded wafer and bonded wafer manufactured thereby
EP0514046B1 (en) System and method for controlling and executing the etching of a wafer
US5071785A (en) Method for preparing a substrate for forming semiconductor devices by bonding warped wafers
EP0207272B1 (en) A method of producing a thin semiconductor layer
EP0337556B1 (en) Method of manufacturing a semiconductor body
KR101284520B1 (ko) 반도체-온-인슐레이터 구조체의 연마 방법
EP1202339A2 (en) Semiconductor substrate, method of manufacturing the same, and bonded substrate stack surface shape measuring method
US6030887A (en) Flattening process for epitaxial semiconductor wafers
US6200908B1 (en) Process for reducing waviness in semiconductor wafers
CA2166409A1 (en) Soi substrate fabrication
US6716722B1 (en) Method of producing a bonded wafer and the bonded wafer
JP2692659B2 (ja) Ｓｏｉ基板および該ｓｏｉ基板の製造方法
EP0968081A1 (en) Flattening process for bonded semiconductor substrates
US7435662B2 (en) Method for manufacturing SOI wafer
JPH098124A (ja) 絶縁分離基板及びその製造方法
US5953620A (en) Method for fabricating a bonded SOI wafer
JP2000256094A (ja) シリコンエピタキシャル成長ウェーハ製造方法およびその装置
JPH0567598A (ja) 半導体基板の製造方法
US5998281A (en) SOI wafer and method for the preparation thereof
JPH07183477A (ja) 半導体基板の製造方法
EP0525781B1 (en) Method for making uniform the thickness of a Si single crystal thin film
WO1998044541A1 (en) Flattening process for semiconductor wafers
JPH09116125A (ja) Ｓｏｉウェーハ及びその製造方法
JPH03228326A (ja) 半導体装置の製造方法
JPH11214368A (ja) ウェーハの平坦化方法とその装置

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): HU JP KR PL SG

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 1019997001730

Country of ref document: KR

ENP Entry into the national phase

Ref country code: JP

Ref document number: 1998 512644

Kind code of ref document: A

Format of ref document f/p: F

WWE Wipo information: entry into national phase

Ref document number: 1997937023

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 1997937023

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 1019997001730

Country of ref document: KR

WWW Wipo information: withdrawn in national office

Ref document number: 1019997001730

Country of ref document: KR

WWW Wipo information: withdrawn in national office

Ref document number: 1997937023

Country of ref document: EP