WO1998004099A1 - Procede de reduction d'adresse dans des systemes de commutation en mode de transfert asynchrone (mta) - Google Patents

Procede de reduction d'adresse dans des systemes de commutation en mode de transfert asynchrone (mta) Download PDF

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Publication number
WO1998004099A1
WO1998004099A1 PCT/DE1997/001274 DE9701274W WO9804099A1 WO 1998004099 A1 WO1998004099 A1 WO 1998004099A1 DE 9701274 W DE9701274 W DE 9701274W WO 9804099 A1 WO9804099 A1 WO 9804099A1
Authority
WO
WIPO (PCT)
Prior art keywords
node
search
vpi
vci
memory
Prior art date
Application number
PCT/DE1997/001274
Other languages
German (de)
English (en)
Inventor
Manfred Hachinger
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Priority to JP50643998A priority Critical patent/JP3821854B2/ja
Priority to AU33351/97A priority patent/AU719083B2/en
Priority to EP97929128A priority patent/EP0914750A1/fr
Publication of WO1998004099A1 publication Critical patent/WO1998004099A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3081—ATM peripheral units, e.g. policing, insertion or extraction
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3009—Header conversion, routing tables or routing tags
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly

Definitions

  • the invention relates to a method according to the preamble of patent claim 1.
  • ATM connections Asynchronous Transfer Mode
  • information is transmitted from one transmitter to one or more receivers. This is done by packing and transmitting the information to be transmitted in ATM cells.
  • the useful information is stored in the information section of the relevant ATM cell and signaling information relating to the connection is stored in the cell header preceding the information section.
  • the signaling information is designed as virtual channel numbers or as virtual path numbers (VPI / VCI connection parameters).
  • VPI / VCI connection parameters are up to 28 bits long and indicate which connection the cell in question belongs to.
  • tables are kept in ATM switching systems in which connection data - that is to say all data characterizing a specific connection, such as data relating to cell rate monitoring or routing - are stored and can be changed dynamically if necessary.
  • connection data - that is to say all data characterizing a specific connection, such as data relating to cell rate monitoring or routing - are stored and can be changed dynamically if necessary.
  • N ⁇ 2 2 ⁇ .
  • the number N is in the order of 2 13 connections.
  • connection-related data In order to be able to take that connection-related data from the table, the associated memory cells must be addressed in a corresponding manner. In principle, this could be done using the VPI / VCI connection parameters. This is however not practical with 2 28 addresses. For this reason, a number of methods for address reduction have become established in the prior art.
  • the 28-bit VPI / VCI address is converted into a shorter one with about 13 bits. With this address, the connection data are now addressed and taken from the relevant table.
  • VPI / VCI connection parameters in shorter internal addresses ⁇ such as 13 bits
  • CAM content-addressable memories
  • the invention has for its object to show a way how the conversion of connection parameters of an ATM cell into internal addresses with simple means without large Effort can be carried out quickly and efficiently without impairing dynamic expandability.
  • a particular advantage of the invention is that this conversion is carried out using a sequential search method in a binary search tree.
  • This is done according to the invention in that the VPI / VCI connection parameters taken from the cell header of an ATM cell are fed as an input variable to a binary search tree having a plurality of nodes, starting with the uppermost node and then being compared in descending order with numerical values stored in the further nodes until equality is achieved in one of the comparison operations.
  • This has the advantage that no complex memory modules, such as the content-addressable memories used in the prior art, need be used.
  • a memory system which is split into a logic part and a memory part, the comparison operations being carried out in the logic part and the nodes being implemented as list entries in the memory part, and that several fields being defined in each of these list entries are updated each time a connection is established or disconnected.
  • This has the advantage that the memory portion is easily expandable in terms of hardware.
  • the algorithm implementing the search tree can also be easily changed in software. The easy expandability in hardware and software is given by the strict separation of logic part and memory part.
  • the termination criterion is the equality of the values linked in the comparison operation. This has the advantage that the different shortest address is completely determined and can be used for addressing the memory containing the connection-related data.
  • At least two search accesses to the memory portion are nested in a chronological order. This is associated with the advantage that the time gaps resulting from the accesses are optimally utilized, as a result of which a further dynamization of the method is achieved.
  • changes to the list - entries are carried out by using at least two databases, one of these databases having an active operating state and the remaining database having a passive operating state, and that at defined times, both databases are each assigned to them - Reported operating status from those in the remaining database.
  • FIG. 1 the method according to the invention using an abstract search strategy using a binary search tree
  • FIG. 2 the implementation of the method according to the invention
  • FIG. 3 nested search accesses for dynamization
  • FIG. 4 the changes in the search memory.
  • the method according to the invention is shown in FIG. 1 on the basis of an abstractly represented search strategy with the aid of a binary search tree.
  • This is a height-balanced, binary AVL tree.
  • Such trees are described in "Algorithms & Data Structures, N.Wirth".
  • the search tree itself is made up of a large number of nodes, each node being connected by connecting lines, which in the sense of the graph Theories are referred to as edges with a maximum of 2 successor nodes.
  • the distances between the top node and all end nodes, which are also referred to as depth, are kept small. In this way, the search time is also kept short.
  • each node is assigned a numerical value, which is formed from the higher bit positions of the VPI part and the lower bit positions of the VCI part of the connection parameters VPI / VCI, which will be described in more detail later.
  • the numerical values of all nodes in the left subtree of the search tree are smaller and in the right part
  • the tree of the search tree is larger than that of the respective node above it.
  • connection parameters VPI / VCI are taken from the cell header K and compared with the numerical value of the topmost node of the search tree. If the connection parameter value VPI / VCI taken from cell Z is greater than the numerical value entered here, a branch is made to the right to the next lower node. Otherwise it branches to the left to the next lower node. A further comparison is then made there. Depending on the result, there may be a further branching until equality is reached. It is important to note that equality can already be determined in the top node.
  • the reduced address is output. This address is usually made up of 13 bit positions, which means a significant reduction compared to the 28 bit positions described above. If no equality is reached in the comparison just mentioned, this means that a cell has arrived for a connection that does not exist and the search is terminated with an acknowledgment of a corresponding message.
  • search memory SP shows how the search tree is implemented in a memory system SP of the ATM switching system, hereinafter referred to as search memory SP.
  • the search memory SP is now split into a logic component ASIC and a memory component RAM.
  • the comparison operations are carried out in the logic part ASIC, while the connection parameter values VPI / VCI and further values to be specified are stored in the memory part RAM.
  • This division has the advantage that the search algorithm is easy to configure and the hardware portion of the RAM can be expanded easily in terms of hardware.
  • the entries in the RAM portion are organized in the form of a list and are made when the connection is established. When a connection is ended, these entries are deleted again. So there is an image in the RAM portion the current status of all connections existing in the ATM switching system in question.
  • N entries are shown in the memory portion RAM.
  • Each of these entries has a total of 8 fields.
  • the first field is formed by the connection parameter value VPI and has a size of 12 bit positions (possibly up to 16 bits).
  • the numerical value of the node (higher value part) is defined here.
  • the next field is the connection parameter value VCI, which has 16 bit positions and defines the least significant part of the numerical value of the node. This is followed by a field P, which is only 1 bit in size and functions as an indicator as to whether or not the connection parameter value VCI should be taken into account in the comparison.
  • connection parameters VPI / VCI are stored in the cell header K.
  • the search memory SP with logic component ASIC and memory component RAM is shown. In the latter, the search tree shown in FIG. 1 is implemented with nodes.
  • the memory S is disclosed, which contains the connection-related data in the table T. The internal processes of the method according to the invention are discussed in more detail below.
  • the connection parameters VPI / VCI are taken from the cell Z arriving in the ATM switching system and compared with a numerical value which is formed from the higher value part of the connection parameter value VPI and the lower value part of the connection parameter value VCI.
  • This numerical value is entered in the node of the search tree shown in FIG. 1.
  • a branch is made to the list entries in question.
  • the branching takes place according to the values entered in the fields LPTR or RPTR. 2 shows branches to the list entries 3 and N as examples.
  • connection parameter value VPI / VCI the numerical value entered here is compared with the connection parameter value VPI / VCI or only with the connection parameter value VPI, depending on the value of the bit contained in field P.
  • This uppermost node of the search tree does not necessarily have to be identical to the uppermost first entry - in the exemplary embodiment this would be the entry with the number 1 according to FIG. 2 - in the search memory SP. Rather, the search can also be carried out from any entry, but it is always started from the top node, regardless of where this node is implemented in the RAM. Depending on the result "greater”, “less” or “equal” of this comparison, the search is continued with the right or left successor node.
  • This branching is implemented in the RAM portion of the memory by means of the fields LPTR and RPTR. Pointer) to other entry fields (eg 2 ... N). If equality is found, the search is terminated by issuing a "Single match" acknowledgment. Furthermore, the list address AD of the node is sent as the return value. The table entries of table T are then addressed in memory S. If the search is continued because no equality has yet been determined, the selection of the successor node continues to be made using the pointing operators of the fields RPTR, LPTR, taking into account the bits stored in the fields RV and LV. If the search process is not ended after a predetermined number of steps, it is terminated with an error message ("mismatch", ie no suitable entry found).
  • FIG. 4 shows how the entries in the RAM memory portion are reorganized when the connection is established or cleared down. This is necessary because otherwise adding or removing entries in the search memory would take place at the same time.
  • two databases are used, which are designated Bank1, Bank2 in FIG. 4.
  • the reference symbol M the original content in the entry of the search memory SP
  • the reference symbol dM the difference in the memory content.
  • One of the databases e.g. B. the database Bankl, is only used for search access and should accordingly have an active operating state.
  • the remaining database, the Bank2 database should only be used for changes that can be entered in the new search list and are in a passive operating state.
  • the nested search accesses A, B according to FIG. 3 should begin in neighboring time slots if possible. The switchover must under no circumstances take place during a search access.
  • a height-balanced, binary AVL tree was used in particular.
  • the invention is not restricted to this type of search tree. Rather, the search can also be carried out using other search trees without restriction.

Abstract

Afin d'effectuer un adressage efficace de données liées à la connexion, mises en mémoire dans un tableau d'un système de commutation MTA, l'adresse nécessaire à l'adressage doit être courte. A cet effet, les paramètres de connexion VPI/VCI (identificateur de trajet virtuel/identificateur de canal virtuel) prélevés à la tête d'une cellule MTA sont acheminés en tant que données d'entrée vers un arbre de recherche binaire présentant une pluralité de noeuds, et sont comparés en commençant par le noeud supérieur, puis par ordre décroissant, à des valeurs numériques mémorisées dans les noeuds suivants, jusqu'à ce que l'une des comparaisons donne une relation d'égalité.
PCT/DE1997/001274 1996-07-23 1997-06-19 Procede de reduction d'adresse dans des systemes de commutation en mode de transfert asynchrone (mta) WO1998004099A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP50643998A JP3821854B2 (ja) 1996-07-23 1997-06-19 Ａｔｍ交換システムでのアドレス低減方法
AU33351/97A AU719083B2 (en) 1996-07-23 1997-06-19 Method for address reduction in ATM switching systems
EP97929128A EP0914750A1 (fr) 1996-07-23 1997-06-19 Procede de reduction d'adresse dans des systemes de commutation en mode de transfert asynchrone (mta)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19629765.6 1996-07-23
DE19629765A DE19629765A1 (de) 1996-07-23 1996-07-23 Verfahren zur Adreßreduktion in ATM-Vermittlungssystemen

Publications (1)

Publication Number Publication Date
WO1998004099A1 true WO1998004099A1 (fr) 1998-01-29

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EP (1) EP0914750A1 (fr)
JP (1) JP3821854B2 (fr)
AU (1) AU719083B2 (fr)
CA (1) CA2261169A1 (fr)
DE (1) DE19629765A1 (fr)
WO (1) WO1998004099A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19825541A1 (de) * 1998-06-08 1999-12-09 Bosch Gmbh Robert Vorrichtung und Verfahren zur Abbildung von Objektadressen
EP1189394A3 (fr) * 2000-09-19 2004-01-07 Siemens Aktiengesellschaft Procedé et dispositif pour la reduction des adresses pour un réseau ATM ou IP

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994001828A1 (fr) * 1992-07-02 1994-01-20 Wellfleet Communications Procede et appareil de traitement de paquets de donnees
EP0600683A2 (fr) * 1992-12-04 1994-06-08 AT&T Corp. Interface pour un réseau de paguets
US5323389A (en) * 1992-08-14 1994-06-21 Fore Systems, Inc. ATM cell interface and method for dispatching an ATM cell
WO1994021069A1 (fr) * 1993-03-10 1994-09-15 Telefonaktiebolaget Lm Ericsson Manipulation de labels dans des reseaux de paquets
WO1995018497A1 (fr) * 1993-12-24 1995-07-06 Newbridge Networks Corporation Machine de recherche pour reseau a base de paquets

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994001828A1 (fr) * 1992-07-02 1994-01-20 Wellfleet Communications Procede et appareil de traitement de paquets de donnees
US5323389A (en) * 1992-08-14 1994-06-21 Fore Systems, Inc. ATM cell interface and method for dispatching an ATM cell
EP0600683A2 (fr) * 1992-12-04 1994-06-08 AT&T Corp. Interface pour un réseau de paguets
WO1994021069A1 (fr) * 1993-03-10 1994-09-15 Telefonaktiebolaget Lm Ericsson Manipulation de labels dans des reseaux de paquets
WO1995018497A1 (fr) * 1993-12-24 1995-07-06 Newbridge Networks Corporation Machine de recherche pour reseau a base de paquets

Also Published As

Publication number Publication date
JP3821854B2 (ja) 2006-09-13
EP0914750A1 (fr) 1999-05-12
DE19629765A1 (de) 1998-01-29
AU3335197A (en) 1998-02-10
CA2261169A1 (fr) 1998-01-29
AU719083B2 (en) 2000-05-04
JP2000514972A (ja) 2000-11-07

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