WO1998004099A1

WO1998004099A1 - Address reducing process in atm communication systems

Info

Publication number: WO1998004099A1
Application number: PCT/DE1997/001274
Authority: WO
Inventors: Manfred Hachinger
Original assignee: Siemens Aktiengesellschaft
Priority date: 1996-07-23
Filing date: 1997-06-19
Publication date: 1998-01-29
Also published as: JP3821854B2; AU3335197A; CA2261169A1; DE19629765A1; EP0914750A1; AU719083B2; JP2000514972A

Abstract

For the connection-related data stored in a table of an ATM communication system to be efficiently addressed, the address required for addressing must be available in a short form. For that purpose, the VPI/VCI connection parameters taken from an ATM cell head are supplied as input values to a binary search tree having a plurality of nodes, beginning with the uppermost node, and are then compared in descending order to numeric values stored in the other nodes until one of the comparisons gives an equal result.

Description

description

Address reduction method in ATM switching systems.

The invention relates to a method according to the preamble of patent claim 1.

With ATM connections (Asynchronous Transfer Mode), information is transmitted from one transmitter to one or more receivers. This is done by packing and transmitting the information to be transmitted in ATM cells. The useful information is stored in the information section of the relevant ATM cell and signaling information relating to the connection is stored in the cell header preceding the information section. The signaling information is designed as virtual channel numbers or as virtual path numbers (VPI / VCI connection parameters).

The VPI / VCI connection parameters are up to 28 bits long and indicate which connection the cell in question belongs to. In general, tables are kept in ATM switching systems in which connection data - that is to say all data characterizing a specific connection, such as data relating to cell rate monitoring or routing - are stored and can be changed dynamically if necessary. At any given time, however, only a number of N connections can be established, where N << 2 ^2β . As a rule, the number N is in the order of 2 ¹³ connections.

In order to be able to take that connection-related data from the table, the associated memory cells must be addressed in a corresponding manner. In principle, this could be done using the VPI / VCI connection parameters. This is however not practical with 2 ²⁸ addresses. For this reason, a number of methods for address reduction have become established in the prior art. The 28-bit VPI / VCI address is converted into a shorter one with about 13 bits. With this address, the connection data are now addressed and taken from the relevant table.

As for the implementation of the VPI / VCI connection parameters in shorter internal addresses {such as 13 bits) is only available for a relatively short time - e.g. 2.8 μsec at a transmission rate of 155 Mbit / sec - content-addressable memories (CAM) have become established in the prior art. These are then offered 28-bit wide input data (i.e. the VPI / VCI connection parameter values). In accordance with an internal comparison of this data with all internal entries, data belonging to the entry found - i.e. in this case the internal address of 13 bits is output. There are basically three cases:

l. No matching entries (mismacht) are found in the memory.

2. Exactly one entry (single match) is found, or

3. More than one entry (multi-match) is found for the given input data.

A disadvantage of such a solution, however, is that the content-addressable memories are expensive and complex since, due to special requirements, they can only be implemented as ASIC components. Furthermore, an expansion of the hardware and software components brings with it difficulties, so that the practicable use is often questioned in practice.

The invention has for its object to show a way how the conversion of connection parameters of an ATM cell into internal addresses with simple means without large Effort can be carried out quickly and efficiently without impairing dynamic expandability.

A particular advantage of the invention is that this conversion is carried out using a sequential search method in a binary search tree. This is done according to the invention in that the VPI / VCI connection parameters taken from the cell header of an ATM cell are fed as an input variable to a binary search tree having a plurality of nodes, starting with the uppermost node and then being compared in descending order with numerical values stored in the further nodes until equality is achieved in one of the comparison operations. This has the advantage that no complex memory modules, such as the content-addressable memories used in the prior art, need be used.

Advantageous developments of the invention are provided in the subclaims.

According to claim 2 it is provided that a memory system is provided which is split into a logic part and a memory part, the comparison operations being carried out in the logic part and the nodes being implemented as list entries in the memory part, and that several fields being defined in each of these list entries are updated each time a connection is established or disconnected. This has the advantage that the memory portion is easily expandable in terms of hardware. In addition, the algorithm implementing the search tree can also be easily changed in software. The easy expandability in hardware and software is given by the strict separation of logic part and memory part.

According to claim 3 it is provided that the termination criterion is the equality of the values linked in the comparison operation. This has the advantage that the different shortest address is completely determined and can be used for addressing the memory containing the connection-related data.

According to claim 4, it is provided that in at least two fields of each list entry pointing operators are defined on the list entries to which the branch is to be made. This has the advantage that there is an efficient, fast search within the algorithm implementing the search tree.

According to claim 5 it is provided that at least two search accesses to the memory portion are nested in a chronological order. This is associated with the advantage that the time gaps resulting from the accesses are optimally utilized, as a result of which a further dynamization of the method is achieved.

According to claim 6 it is provided that changes to the list - entries are carried out by using at least two databases, one of these databases having an active operating state and the remaining database having a passive operating state, and that at defined times, both databases are each assigned to them - Reported operating status from those in the remaining database. This has the advantage that the changes only take effect at defined times, namely the changeover time. Since the addition and removal of entries is always accompanied by larger data movements, this further dynamic the process.

The invention is described in more detail below with the aid of an exemplary embodiment. Show it :

FIG. 1: the method according to the invention using an abstract search strategy using a binary search tree, FIG. 2 the implementation of the method according to the invention; FIG. 3 nested search accesses for dynamization; FIG. 4 the changes in the search memory.

The method according to the invention is shown in FIG. 1 on the basis of an abstractly represented search strategy with the aid of a binary search tree. This is a height-balanced, binary AVL tree. Such trees are described in "Algorithms & Data Structures, N.Wirth". The search tree itself is made up of a large number of nodes, each node being connected by connecting lines, which in the sense of the graph Theories are referred to as edges with a maximum of 2 successor nodes. The distances between the top node and all end nodes, which are also referred to as depth, are kept small. In this way, the search time is also kept short. This is necessary in order to perform the search - Can be maintained for less than 2.8 μsec Furthermore, each node is assigned a numerical value, which is formed from the higher bit positions of the VPI part and the lower bit positions of the VCI part of the connection parameters VPI / VCI, which will be described in more detail later The numerical values of all nodes in the left subtree of the search tree are smaller and in the right part The tree of the search tree is larger than that of the respective node above it.

An ATM cell Z penetrating into the ATM switching system is then checked to determine which connection it belongs to, if applicable, that in a table T of a memory S to be able to take and process stored connection-related data. For this purpose, the connection parameters VPI / VCI are taken from the cell header K and compared with the numerical value of the topmost node of the search tree. If the connection parameter value VPI / VCI taken from cell Z is greater than the numerical value entered here, a branch is made to the right to the next lower node. Otherwise it branches to the left to the next lower node. A further comparison is then made there. Depending on the result, there may be a further branching until equality is reached. It is important to note that equality can already be determined in the top node. If equality is determined, the reduced address is output. This address is usually made up of 13 bit positions, which means a significant reduction compared to the 28 bit positions described above. If no equality is reached in the comparison just mentioned, this means that a cell has arrived for a connection that does not exist and the search is terminated with an acknowledgment of a corresponding message.

2 shows how the search tree is implemented in a memory system SP of the ATM switching system, hereinafter referred to as search memory SP. The search memory SP is now split into a logic component ASIC and a memory component RAM. The comparison operations are carried out in the logic part ASIC, while the connection parameter values VPI / VCI and further values to be specified are stored in the memory part RAM. This division has the advantage that the search algorithm is easy to configure and the hardware portion of the RAM can be expanded easily in terms of hardware. The entries in the RAM portion are organized in the form of a list and are made when the connection is established. When a connection is ended, these entries are deleted again. So there is an image in the RAM portion the current status of all connections existing in the ATM switching system in question.

Furthermore, a part of the entries in the memory portion RAM must be reorganized as a result of a connection being established or a connection being closed. The number of changes is limited by the tree depth. 2, N entries are shown in the memory portion RAM. Each of these entries has a total of 8 fields. The first field is formed by the connection parameter value VPI and has a size of 12 bit positions (possibly up to 16 bits). The numerical value of the node (higher value part) is defined here. The next field is the connection parameter value VCI, which has 16 bit positions and defines the least significant part of the numerical value of the node. This is followed by a field P, which is only 1 bit in size and functions as an indicator as to whether or not the connection parameter value VCI should be taken into account in the comparison. This is essential insofar as it must be possible in ATM applications to only search for the VPI portion in addition to the combined VPI / VCI evaluation. Next follows a field LPTR with 13 bit positions, which defines a pointer to the left successor node. The field LV indicates with 1 bit whether this left successor node exists. The same applies to the fields PRTR (pointer to right successor node, 13 bit positions), RV (1 bit, indicator whether right successor node exists).

2, the ATM cell Z penetrating into the ATM switching node is furthermore shown, which has an information part I and a cell header K. The connection parameters VPI / VCI are stored in the cell header K. Furthermore, as already mentioned at the beginning, the search memory SP with logic component ASIC and memory component RAM is shown. In the latter, the search tree shown in FIG. 1 is implemented with nodes. Furthermore, the memory S is disclosed, which contains the connection-related data in the table T. The internal processes of the method according to the invention are discussed in more detail below. In this case, the connection parameters VPI / VCI are taken from the cell Z arriving in the ATM switching system and compared with a numerical value which is formed from the higher value part of the connection parameter value VPI and the lower value part of the connection parameter value VCI. This numerical value is entered in the node of the search tree shown in FIG. 1. Depending on the result of the comparison operation, a branch is made to the list entries in question. The branching takes place according to the values entered in the fields LPTR or RPTR. 2 shows branches to the list entries 3 and N as examples.

Starting from the top node of the search tree, the numerical value entered here is compared with the connection parameter value VPI / VCI or only with the connection parameter value VPI, depending on the value of the bit contained in field P. This uppermost node of the search tree does not necessarily have to be identical to the uppermost first entry - in the exemplary embodiment this would be the entry with the number 1 according to FIG. 2 - in the search memory SP. Rather, the search can also be carried out from any entry, but it is always started from the top node, regardless of where this node is implemented in the RAM. Depending on the result "greater", "less" or "equal" of this comparison, the search is continued with the right or left successor node. This branching is implemented in the RAM portion of the memory by means of the fields LPTR and RPTR. Pointer) to other entry fields (eg 2 ... N). If equality is found, the search is terminated by issuing a "Single match" acknowledgment. Furthermore, the list address AD of the node is sent as the return value. The table entries of table T are then addressed in memory S. If the search is continued because no equality has yet been determined, the selection of the successor node continues to be made using the pointing operators of the fields RPTR, LPTR, taking into account the bits stored in the fields RV and LV. If the search process is not ended after a predetermined number of steps, it is terminated with an error message ("mismatch", ie no suitable entry found). The same applies in the event that the checksum PR for the processed node is faulty. Multiple entries ( "Multimatch") are not checked during the search since, in contrast to the content-addressable memories addressed in the prior art, they cannot occur with this type of list structure. This is recognized here when the list is created, and thus incorrect contents of the RAM memory are not even permitted.

3 shows an advantageous development of the invention. During each search step of the sequential search, after reading in the respective node, a decision must be made as to which of the subsequent nodes must be addressed. Between the determination of the address of the subsequent node and the comparison operations, however, there are gaps in the access to the memory portion RAM, which means a loss of dynamics (loss of performance). This loss of dynamics can be reduced by nesting two search accesses (A and B). 3 describes the n # i step in the search access n. In the access scheme for the memory portion RAM, sufficient time for the refresh (DRAM) and access for changes in the memory must be kept free.

4, an advantageous development of the invention is shown. It shows how the entries in the RAM memory portion are reorganized when the connection is established or cleared down. This is necessary because otherwise adding or removing entries in the search memory would take place at the same time. Thereafter, two databases are used, which are designated Bank1, Bank2 in FIG. 4. Also means in Figure 4, the reference symbol M the original content in the entry of the search memory SP, and the reference symbol dM the difference in the memory content. One of the databases, e.g. B. the database Bankl, is only used for search access and should accordingly have an active operating state. The remaining database, the Bank2 database, should only be used for changes that can be entered in the new search list and are in a passive operating state. After the changes have been entered in the database having the passive operating state, the latter is transferred to the active operating state and the previously active database is provided with the same changes. So that the switching of the databases takes place without interference, the nested search accesses A, B according to FIG. 3 should begin in neighboring time slots if possible. The switchover must under no circumstances take place during a search access.

In the exemplary embodiment described above, a height-balanced, binary AVL tree was used in particular. However, the invention is not restricted to this type of search tree. Rather, the search can also be carried out using other search trees without restriction.

Claims

claims

l. Method for address reduction in ATM switching systems, with ATM cells (Z) which have an information part (I) and a cell header (K) preceding this, the latter storing logical connection parameters (VPI / VCI), and with a plurality of nodes having a search tree, which is organized in such a way that each node is connected to at least 2 successor nodes via connecting lines and a numerical value is assigned to each node, characterized in that the logical connection parameters (VPI / VCI) are taken from the cell header (K) and starting with the uppermost node in descending order with the numerical value stored in the node, and depending on the result of this comparison, a branching to further nodes is carried out, where a comparison of the numerical value stored there with the logical connection parameters (VPI / VCI ) is carried out until according to an abort criterion the comparison operations are canceled.

2. The method according to claim 1, characterized in that a memory system (SP) is provided, which is split into a logic part (ASIC) and a memory part (RAM), the comparison operations being carried out in the logic part (ASIC) and the nodes as List entries (1 ... N) in the memory portion (RAM) are implemented so that several fields are defined in each of these list entries, which are updated each time the connection is established or disconnected.

3. The method according to claim 1 or 2, characterized in that the termination criterion is the equality of the values linked in the comparison operation.

4. The method according to claim 1 to 3, characterized in that in at least two fields (LPTR, RPTR) of each list entry (1 ... N) pointing operators to the list entries (1 ... N) are defined, to which branches should.

5. The method according to claim 1 to 4, characterized in that at least two search accesses (A, B) to the memory portion (RAM) are nested in a chronological order.

6. The method according to any one of the preceding claims, characterized in that changes to the list entries are carried out by using at least two databases (Bankl, Bank2), one of these databases having an active operating state and the remaining database having a passive operating state, and that at fixed times, both databases are transferred from the operating state assigned to them to that of the remaining database.