Classifications

• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
  • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
  • G05F3/02—Regulating voltage or current
  • G05F3/08—Regulating voltage or current wherein the variable is DC
  • G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
  • G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
  • G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
  • G05F3/30—Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities

Definitions

• the invention relates to a bandgap reference voltage circuit for generating a temperature-compensated reference voltage with a first and second voltage divider connected between a first and a second voltage terminal, each having a transistor connected to the first voltage terminal as a diode, the transistor in the the first voltage divider via an ohmic resistor and the transistor in the second voltage divider is connected directly to a voltage divider point of the respective voltage divider and the two voltage divider points each via one
• Resistor device are connected to the second voltage terminal, which is connected on the output side to the first voltage terminal, with its inverting input to the voltage regulator point of the first voltage divider and with its non-inverting input to the voltage divider point of the second voltage divider.
• a bandgap reference voltage circuit is generally used, such as, for example, from the publication Grube / Dudek: "Prochip PROMETHEUS final report: Robust Analog Design” by the Institute for Microelectronics Stuttgart, pages 2 to 40 and in particular Page 30.
• These circuits all have a common characteristic: polysilicon resistors which are precisely matched to one another are always used, the size of which is inversely proportional to the current consumption of the circuit arrangement. As a size arrangement, for example, a total resistance of 870 k ⁇ with a current consumption of 14 ⁇ A can be considered.
• FIG. 1 shows the circuit arrangement of a known band gap reference voltage circuit.
• the circuit arrangement of FIG. 1 has a differential amplifier device, here a comparator K, the inverting and non-inverting input of which is in each case connected to a voltage divider point of a voltage divider.
• a first of these voltage dividers is connected between a first voltage terminal 1, which is connected to reference potential, and a second voltage terminal 2.
• the temperature-compensated reference voltage Vref to be generated can be tapped at the second voltage terminal 2.
• the first voltage divider has a series connection of a resistor R2 and a bipolar transistor Q2 connected as a diode. The collector and base connection of this bipolar transistor Q2 is the first
• the connection point of the resistor R2 and the bipolar transistor Q2 is connected to the non-inverting input of the comparator K.
• a second voltage divider is also connected between the first voltage terminal 1 and the second voltage terminal 2. This second voltage divider consists of the series connection of a resistor R1, a further resistor R3 and a bipolar transistor Q1, the collector and base connection of which are in turn connected to the first voltage terminal 1.
• the connection point of the resistors R1 and R3 is connected to the non-inverting input of the comparator K.
• the two bipolar transistors Q1 and Q2 mentioned are, for example, as shown in FIG.
• FIG. 1 also has a third voltage terminal 3, which is connected to a supply voltage Vdd connected.
• a p-channel MOSFET is connected between the second voltage terminal 2 and the third voltage terminal 3, the gate connection of which is acted upon by a control voltage V bias in order to implement a current source.
• the two bipolar transistors Q1 and Q2 are operated in this known circuit arrangement with different current densities II and 12. This should be done for different emitter base voltages Vbel and Vbe2 at the bipolar transistors Ql and Q2 according to the following relationship:
• the resulting voltage difference ⁇ Vbe between the two emitter connections of the bipolar transistors Q2 and Q1 is directly proportional to the operating temperature of the circuit arrangement and has a positive temperature coefficient, as the following relationship shows:
• M is the ratio of the emitter area of the bipolar transistor Q1 to the emitter area and the bipolar transistor Q2.
• This voltage difference .DELTA.Vbe is increasingly added to the emitter-base voltage of the bipolar transistor Q2, so that its negative temperature coefficient is compensated for.
• the resulting total voltage is the reference voltage Vref and is approximately of the order of 1.2 V.
• Voltage ⁇ Vbe are in the known circuit arrangement of FIG. 1 by the size of the resistors Rl, R2 and R3 used and the emitter areas of the bipolar transistors Ql and Q2 according to
• the comparator K with a subsequent output stage in the form of the MOSFET M30 ensures that the voltage divider points A and B are at the same potential.
• the invention is therefore based on the object of specifying a bandgap reference voltage circuit in which small polysilicon sheet resistances are sufficient and which are therefore suitable for use in a logic process.
• the circuit arrangement is intended to generate an accurate, temperature- and input voltage-independent reference voltage using relatively small resistances, the power consumption in comparison to the known band gap Reference voltage circuits should not be increased. Furthermore, the circuit arrangement should enable good matching of the components with one another and thus contribute to a high yield in production.
• the resistance devices are formed by resistance elements with decreasing conductance as the temperature rises and are connected to the second voltage terminal via a current mirror arrangement in that an ohmic resistor is connected to the voltage divider point of the second voltage divider is connected, which is connected with its free terminal, at which the temperature-compensated reference voltage can be tapped, to the second voltage terminal via the load path of a transistor, the control connection of this transistor being connected to the connection point of the current mirror arrangement and the resistance devices is connected that supply terminals of the differential amplifier arrangement are connected to the first and second voltage terminals, and that a controllable current source is connected between the second voltage terminal and a third voltage terminal st.
• the circuit arrangement according to the invention in contrast to the known bandgap reference voltage circuits, it is not the reference voltage itself that is regulated directly, but rather the control voltage applied to the second voltage terminal, which is at a higher potential. This ensures that disturbances in the supply voltage, which is connected to the third voltage terminal, are better damped and generate smaller disturbance amplitudes in the reference voltage. Furthermore, this decoupling ensures the stability of the bandgap control loop.
• the control voltage at the second voltage terminal is preferably set by a regulated voltage divider. This is done by the bandgap reference voltage circuit certain constant current impressed. A control deviation at the voltage divider points of the two voltage dividers and thus at the differential voltage input of the differential amplifier arrangement is amplified by the differential amplifier arrangement and corrected by a change in the gate-source voltage in an output stage transistor.
• the comparator preferably has a symmetrical input stage for reducing the comparator offset.
• an attenuator can be installed between the drain connection and the gate connection of the output stage transistor.
• the mentioned resistance elements with decreasing conductance with increasing temperature are realized by MOSFETs. This results in a higher temperature independence of the circuit arrangement.
• Fig. 3 an embodiment of a bandgap reference voltage circuit according to the invention in n-well technology
• FIG. 4 a more detailed circuit diagram for FIG. 3.
• the same reference symbols designate the same parts with the same meaning.
• the band gap reference voltage circuits presented in the following FIGS. 3 and 4 are each shown using n-well technology, it is readily possible to implement the circuits presented there using p-well technology.
• the circuit arrangement shown in FIG. 3 has a first voltage terminal 1, which in the present case is at reference potential, a second voltage terminal 2 and a third voltage terminal 3.
• a supply voltage Vdd is connected to the third voltage terminal 3.
• a control voltage Vreg can be tapped at the second voltage terminal 2.
• An output stage transistor M18 with its load path is connected between the first voltage terminal 1 and the second voltage terminal 2.
• this output stage transistor M18 is an n-channel MOSFET, the gate connection of which is connected to the output terminal of a comparator K.
• a supply voltage terminal of the comparator K is connected to the second voltage terminal 2 and another supply terminal of this comparator K is connected to the first voltage terminal 1.
• the inverting input is connected to a voltage divider point A and the non-inverting input of the comparator K is connected to a voltage divider point B of a voltage divider arrangement which forms the "bandgap core" and is described in detail below
• the voltage divider point A is connected via an ohmic resistor R1 to the emitter terminal of a bipolar transistor Q1.
• the base connection and collector connection of this bipolar transistor Q1 is connected to the first voltage terminal 1.
• Another bipolar transistor Q2 is also connected to the first voltage with its base connection and its collector connection. voltage terminal 1 connected, the emitter connection of which is directly connected to the voltage divider point B.
• the two bipolar transistors Q1 and Q2 are pnp bipolar transistors and are implemented, for example, as parasitic, vertical bipolar transistors (cf. FIG. 2).
• the voltage divider point A is connected to a switching point C via the load path of a p-channel MOSFET.
• This circuit point C is connected to the second voltage terminal 2 via a current mirror arrangement consisting of further p-channel MOSFETs M1, M2 and M3.
• the MOSFET located between the voltage divider point A and the circuit point C is identified by the reference symbol M19. Its gate connection is connected on the one hand to the first voltage terminal 1 and on the other hand to the gate connection of a further p-channel MOSFET M20.
• the load path of the MOSFET M20 is connected between the current mirror mentioned and the voltage divider point D.
• the current mirror arrangement has three p-channel MOSFETs M1, M2 and M3, which are connected as follows.
• the load path of the MOSFET Ml lies between the switching point C and the second voltage terminal 2.
• the gate connection of the MOSFET Ml is connected to the switching point C, as is the gate connection of the MOSFET M2.
• the load path of the MOSFET M2 is in series with the load path of the mentioned MOSFET M20.
• the two gate connections of the MOSFETs M1 and M2 are connected to the gate connection of the MOSFET M3.
• the load path of the MOSFET M3 is in series with a resistor R2 which is connected to the voltage divider point B.
• connection point of the resistor R2 and the load path of the MOSFET M3 also serves as an output connection for the temperature-compensated reference voltage Vref.
• the load path MOSFET M3 lies between this output connection and the second voltage terminal 2.
• Voltage V reg is regulated in such a way that the voltage divider points A and B are at the same potential, so the voltage ⁇ V j - ⁇ is mapped to the ohmic resistor Rl and thus determines the current II according to the following formula
• the value of the temperature gradient of the voltage V De 2 is approximately minus 2mV / l ° Celsius.
• the formula for determining the design parameters is as follows
• the circuit arrangement according to FIG. 3 does not directly regulate the reference voltage V re f, but rather the voltage V reg at the second voltage terminal, which is at a higher potential. In this way, disturbances in the supply voltage V ⁇ a at the third voltage terminal can be damped better and smaller interference amplitudes in the reference voltage V re f can be generated. This decoupling ensures the stability of the bad gap control loop.
• the control voltage V re ⁇ at the second voltage terminal 2 can be regulated by the adjustable current Source, as shown in Figure 3 and designated by reference numeral 4, can be set.
• FIG. 4 shows a detailed circuit diagram of a bandgap interference voltage circuit according to the invention, in which the comparator K explained in connection with FIG. 3, the current source 4 and the output stage M18 are implemented using specific circuit elements. In order to avoid repetitions, only the circuit-technical differences from FIG. 3 are described below in the explanation of the circuit arrangement in FIG.
• MOSFETs M4, M5, M6, M7 and M8 shown in FIG. 4 serve as the regulated current source.
• the MOSFETs M4, M7 and M8 are p-channel MOSFETs and M5 and M6 are n-channel MOSFETs.
• the MOSFET M4 is connected with one connection of its load path to the second voltage terminal 2 and with its other connection to the load path to a connection of the load path of the MOSFET M5.
• the other connection of the load path of this MOSFET M5 is connected to the first voltage terminal 1.
• the gate connection of the MOSFET M4 is connected to the circuit point C of the circuit arrangement, while the gate connection of the MOSFET M5 is connected on the one hand to the connection point between MOSFET M4 and M5 and on the other hand to the gate connection of the MOSFET M6.
• the load path of the MOSFET M6 is connected in series with the load path of the MOSFET M7, the MOSFET M6 being connected to a connection to the first voltage terminal 1 and thus to reference potential and a connection of the MOSFET M7 to the third voltage terminal 3.
• the connection point between MOSFET M6 and MOSFET M7 is short-circuited to the gate connection of MOSFET M7.
• the control voltage V reg at the second voltage terminal 2 is set by a regulated voltage divider consisting of the MOSFET M8 and the MOSFET M18.
• the connection point between MOSFET M8 and MOSFET M18, which is the output stage transistor, is also the second voltage terminal 2.
• the MOSFETs M9 to M16 which are also shown in FIG. 4 form the comparator K of the bandgap reference voltage circuit.
• the comparator K is known per se from the aforementioned publication Laker / Sansen (cf. page 577), so that reference is expressly made to this for the purposes of the disclosure.
• the comparator K has four p-channel MOSFETs M9, MIO, Mll, Ml6 and M17, and four n-channel MOSFETs M12, M13, M14 and M15. Like the two MOSFETs M15 and M17, the MOSFETs Ml4 and M16 are connected in series and lie between the first voltage terminal 1 and the second voltage terminal 2. The gate connections of the MOSFETs M16 and M17 are connected to one another and at the same time connected to the connection point of the two MOSFETs M14 and M16. The series circuit of the load paths of the MOSFET M9, the MOSFET MIO and the MOSFET M12 is also connected between the first voltage terminal 1 and the second voltage terminal 2.
• the series connection of the load paths of the MOSFETs Mll and Ml3 is connected at the connection point of the two load paths of the MOSFET M9 and the MOSFET MIO and the first voltage terminal 1.
• the gate connections of the MOSFETs Ml3 and M15 are connected to one another and at the same time connected to the connection point of the MOSFETs Mll and M13.
• the gate terminals of MOSFETs M12 and M14 are connected to the connection point between MOSFET MIO and MOSFET M12.
• the gate connection of the MOSFET M9 is connected to the node C of the circuit arrangement.
• the gate connection of the MOSFET Mll is the inverting input of the comparator K and is therefore connected to the voltage divider point A.
• the gate connection of the MOSFET MIO is the non-inverting input of the comparator K and consequently connected to the voltage divider point B.
• the output connection of the comparator K is also the connection point of the two MOSFETs M15 and M17.
• the output connection of the grain Parator K is connected to the gate connection of the MOSFET M18.
• a constant current determined by the bandgap reference voltage circuit is impressed into the MOSFET M8.
• a control deviation at the voltage divider points A and B is amplified by the comparator K and corrected by changing the gate-source voltage at the MOSFET Ml8 in the output stage.
• the comparator K has a symmetrical input stage to reduce the comparator offset.
• an attenuator here an RC element, is installed between the drain connection and the gate connection of the output stage transistor Ml8.
• the damping element is an RC element, the capacitor C1 of which is connected with a connection to the second voltage terminal 2 and with the second connection to the resistor R4.

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• 1996
  • 1996-05-20 DE DE1996120181 patent/DE19620181C1/de not_active Expired - Fee Related
• 1997
  • 1997-05-09 WO PCT/DE1997/000939 patent/WO1997044722A1/de active Application Filing
  • 1997-05-13 IN IN858CA1997 patent/IN191523B/en unknown

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