WO1997044722A1

WO1997044722A1 - Bandgap-reference voltage circuit for producing a temperature-compensated reference voltage

Info

Publication number: WO1997044722A1
Application number: PCT/DE1997/000939
Authority: WO
Inventors: Martin Bloch
Original assignee: Siemens Aktiengesellschaft
Priority date: 1996-05-20
Filing date: 1997-05-09
Publication date: 1997-11-27
Also published as: IN191523B; DE19620181C1

Abstract

A voltage Vreg is controlled which is led off from the distribution voltage by a controlled voltage divider. The voltage Vreg is at a higher potential than the reference voltage Vref. An essential portion of the circuit layout is formed by resistors the conductivity of which decreases with rising temperature. These resistors are each connected into one voltage divider, the voltage divider point (A, B) of which remains connected with the input of a differential amplifier (K).

Description

description

BANDGAP REFERENCE VOLTAGE CIRCUIT FOR GENERATING A TEMPERATURE COMPENSATED REFERENCE VOLTAGE

The invention relates to a bandgap reference voltage circuit for generating a temperature-compensated reference voltage with a first and second voltage divider connected between a first and a second voltage terminal, each having a transistor connected to the first voltage terminal as a diode, the transistor in the the first voltage divider via an ohmic resistor and the transistor in the second voltage divider is connected directly to a voltage divider point of the respective voltage divider and the two voltage divider points each via one

Resistor device are connected to the second voltage terminal, which is connected on the output side to the first voltage terminal, with its inverting input to the voltage regulator point of the first voltage divider and with its non-inverting input to the voltage divider point of the second voltage divider.

Most of the integrated circuits require a very precise reference voltage that is independent of temperature and input voltage. In order to generate such a signal, a bandgap reference voltage circuit is generally used, such as, for example, from the publication Grube / Dudek: "Prochip PROMETHEUS final report: Robust Analog Design" by the Institute for Microelectronics Stuttgart, pages 2 to 40 and in particular Page 30. These circuits all have a common characteristic: polysilicon resistors which are precisely matched to one another are always used, the size of which is inversely proportional to the current consumption of the circuit arrangement. As a size arrangement, for example, a total resistance of 870 kΩ with a current consumption of 14 μA can be considered. 1 shows the circuit arrangement of a known band gap reference voltage circuit. The circuit arrangement of FIG. 1 has a differential amplifier device, here a comparator K, the inverting and non-inverting input of which is in each case connected to a voltage divider point of a voltage divider. A first of these voltage dividers is connected between a first voltage terminal 1, which is connected to reference potential, and a second voltage terminal 2. The temperature-compensated reference voltage Vref to be generated can be tapped at the second voltage terminal 2. The first voltage divider has a series connection of a resistor R2 and a bipolar transistor Q2 connected as a diode. The collector and base connection of this bipolar transistor Q2 is the first

Voltage terminal 1 in connection, during whose emitter connection is connected to the second voltage terminal 2 via the resistor R2 mentioned. The connection point of the resistor R2 and the bipolar transistor Q2 is connected to the non-inverting input of the comparator K. A second voltage divider is also connected between the first voltage terminal 1 and the second voltage terminal 2. This second voltage divider consists of the series connection of a resistor R1, a further resistor R3 and a bipolar transistor Q1, the collector and base connection of which are in turn connected to the first voltage terminal 1. The connection point of the resistors R1 and R3 is connected to the non-inverting input of the comparator K. The two bipolar transistors Q1 and Q2 mentioned are, for example, as shown in FIG. 2, mostly parasitic, vertical bipolar transistors and, in the present example, p-channel bipolar transistors. An output terminal of the comparator K is connected to the gate terminal of an n-channel MOSFET, the load path of which is connected between the first voltage terminal 1 and the second voltage terminal 2. Finally, the known circuit arrangement of FIG. 1 also has a third voltage terminal 3, which is connected to a supply voltage Vdd connected. In the present exemplary embodiment, a p-channel MOSFET is connected between the second voltage terminal 2 and the third voltage terminal 3, the gate connection of which is acted upon by a control voltage V bias in order to implement a current source.

The two bipolar transistors Q1 and Q2 are operated in this known circuit arrangement with different current densities II and 12. This should be done for different emitter base voltages Vbel and Vbe2 at the bipolar transistors Ql and Q2 according to the following relationship:

where K = 1,380.10 ^{~ 23} JK ^-1 (Boltzmann constant) and e = 1,602.10 ^-19 C (elementary charge).

The resulting voltage difference ΔVbe between the two emitter connections of the bipolar transistors Q2 and Q1 is directly proportional to the operating temperature of the circuit arrangement and has a positive temperature coefficient, as the following relationship shows:

where M is the ratio of the emitter area of the bipolar transistor Q1 to the emitter area and the bipolar transistor Q2.

This voltage difference .DELTA.Vbe is increasingly added to the emitter-base voltage of the bipolar transistor Q2, so that its negative temperature coefficient is compensated for. The resulting total voltage is the reference voltage Vref and is approximately of the order of 1.2 V. The different current densities and the amplification of the

Voltage ΔVbe are in the known circuit arrangement of FIG. 1 by the size of the resistors Rl, R2 and R3 used and the emitter areas of the bipolar transistors Ql and Q2 according to

set. The comparator K with a subsequent output stage in the form of the MOSFET M30 ensures that the voltage divider points A and B are at the same potential.

The main problem with this known circuit arrangement lies in the implementation of the required resistors R1, R2 and R3. Due to the high demands on the accuracy of these resistors, only those made of polysilicon are used in integrated circuit technology. Such polysilicon resistors usually have only a very small surface resistance in logic processes, which is approximately in the order of 20 to 100 Ω / square. The circuit developer of this known bandgap reference voltage circuit thus has only relatively low-resistance polysilicon tracks available, insofar as the circuit arrangement is to be manufactured in a logic process. Under the current design requirement for minimal power consumption, this leads to an unacceptably large amount of space on the semiconductor body.

The invention is therefore based on the object of specifying a bandgap reference voltage circuit in which small polysilicon sheet resistances are sufficient and which are therefore suitable for use in a logic process. The circuit arrangement is intended to generate an accurate, temperature- and input voltage-independent reference voltage using relatively small resistances, the power consumption in comparison to the known band gap Reference voltage circuits should not be increased. Furthermore, the circuit arrangement should enable good matching of the components with one another and thus contribute to a high yield in production.

This object is achieved in the bandgap reference voltage circuit mentioned at the outset in that the resistance devices are formed by resistance elements with decreasing conductance as the temperature rises and are connected to the second voltage terminal via a current mirror arrangement in that an ohmic resistor is connected to the voltage divider point of the second voltage divider is connected, which is connected with its free terminal, at which the temperature-compensated reference voltage can be tapped, to the second voltage terminal via the load path of a transistor, the control connection of this transistor being connected to the connection point of the current mirror arrangement and the resistance devices is connected that supply terminals of the differential amplifier arrangement are connected to the first and second voltage terminals, and that a controllable current source is connected between the second voltage terminal and a third voltage terminal st.

In the circuit arrangement according to the invention, in contrast to the known bandgap reference voltage circuits, it is not the reference voltage itself that is regulated directly, but rather the control voltage applied to the second voltage terminal, which is at a higher potential. This ensures that disturbances in the supply voltage, which is connected to the third voltage terminal, are better damped and generate smaller disturbance amplitudes in the reference voltage. Furthermore, this decoupling ensures the stability of the bandgap control loop.

The control voltage at the second voltage terminal is preferably set by a regulated voltage divider. This is done by the bandgap reference voltage circuit certain constant current impressed. A control deviation at the voltage divider points of the two voltage dividers and thus at the differential voltage input of the differential amplifier arrangement is amplified by the differential amplifier arrangement and corrected by a change in the gate-source voltage in an output stage transistor. The comparator preferably has a symmetrical input stage for reducing the comparator offset. In order to ensure stable operation of the control circuit, an attenuator can be installed between the drain connection and the gate connection of the output stage transistor.

In a preferred development of the invention, the mentioned resistance elements with decreasing conductance with increasing temperature are realized by MOSFETs. This results in a higher temperature independence of the circuit arrangement.

The bandgap reference voltage circuit according to the invention is explained in more detail below in connection with further figures using an exemplary embodiment. Show it:

1: the band gap reference voltage circuit according to the prior art, already explained,

2: a schematic sectional view through a semiconductor body with a vertical bipolar transistor in p-channel technology,

Fig. 3: an embodiment of a bandgap reference voltage circuit according to the invention in n-well technology and

FIG. 4: a more detailed circuit diagram for FIG. 3. In the following figures, unless otherwise stated, the same reference symbols designate the same parts with the same meaning. Although the band gap reference voltage circuits presented in the following FIGS. 3 and 4 are each shown using n-well technology, it is readily possible to implement the circuits presented there using p-well technology.

The circuit arrangement shown in FIG. 3 has a first voltage terminal 1, which in the present case is at reference potential, a second voltage terminal 2 and a third voltage terminal 3. A supply voltage Vdd is connected to the third voltage terminal 3. There is a regulated current source between the third voltage terminal 3 and the second voltage terminal 2. A control voltage Vreg can be tapped at the second voltage terminal 2. An output stage transistor M18 with its load path is connected between the first voltage terminal 1 and the second voltage terminal 2. In the present example, this output stage transistor M18 is an n-channel MOSFET, the gate connection of which is connected to the output terminal of a comparator K. A supply voltage terminal of the comparator K is connected to the second voltage terminal 2 and another supply terminal of this comparator K is connected to the first voltage terminal 1. The inverting input is connected to a voltage divider point A and the non-inverting input of the comparator K is connected to a voltage divider point B of a voltage divider arrangement which forms the "bandgap core" and is described in detail below.

The voltage divider point A, similar to that explained in connection with FIG. 1, is connected via an ohmic resistor R1 to the emitter terminal of a bipolar transistor Q1. The base connection and collector connection of this bipolar transistor Q1 is connected to the first voltage terminal 1. Another bipolar transistor Q2 is also connected to the first voltage with its base connection and its collector connection. voltage terminal 1 connected, the emitter connection of which is directly connected to the voltage divider point B. The two bipolar transistors Q1 and Q2 are pnp bipolar transistors and are implemented, for example, as parasitic, vertical bipolar transistors (cf. FIG. 2).

The voltage divider point A is connected to a switching point C via the load path of a p-channel MOSFET. This circuit point C is connected to the second voltage terminal 2 via a current mirror arrangement consisting of further p-channel MOSFETs M1, M2 and M3. The MOSFET located between the voltage divider point A and the circuit point C is identified by the reference symbol M19. Its gate connection is connected on the one hand to the first voltage terminal 1 and on the other hand to the gate connection of a further p-channel MOSFET M20. The load path of the MOSFET M20 is connected between the current mirror mentioned and the voltage divider point D.

The current mirror arrangement has three p-channel MOSFETs M1, M2 and M3, which are connected as follows. The load path of the MOSFET Ml lies between the switching point C and the second voltage terminal 2. The gate connection of the MOSFET Ml is connected to the switching point C, as is the gate connection of the MOSFET M2. The load path of the MOSFET M2 is in series with the load path of the mentioned MOSFET M20. The two gate connections of the MOSFETs M1 and M2 are connected to the gate connection of the MOSFET M3. The load path of the MOSFET M3 is in series with a resistor R2 which is connected to the voltage divider point B. The connection point of the resistor R2 and the load path of the MOSFET M3 also serves as an output connection for the temperature-compensated reference voltage Vref. The load path MOSFET M3 lies between this output connection and the second voltage terminal 2. The operation of the bandgap reference voltage circuit shown in Fig. 3 is as follows.

If a current II flows through the bipolar transistor Q1, this current II is impressed by the current mirror M1, M2 and M3 in the following manner. The N times the current II flows through the MOSFET M3 and exactly the current II flows through the MOSFET M2. This results in a current 12 in the bipolar transistor Q2

generated.

Because of the differently large currents II and 12 through the bipolar transistors Q1 and Q2, a voltage difference ΔVbe in the order of magnitude of about 50 to 100mV according to the above-mentioned formula (2) arises between the emitter connections of these bipolar transistors Ql and Q2. This voltage difference has a positive temperature gradient and is directly proportional to the operating temperature. Now the

Voltage V _{reg is} regulated in such a way that the voltage divider points A and B are at the same potential, so the voltage ΔV _j - ^ is mapped to the ohmic resistor Rl and thus determines the current II according to the following formula

The current mirror with the MOSFETs Ml, M2 and M3 impresses the current N • II in the resistor R2. As a result, the voltage Δv drops across this resistor R2 in accordance with

from. If the formulas (2) and (4) are used in the formula (6), the result is a value which depends only on the component parameters R1, R2, N and M in accordance with the following relationship

The sum of the voltage ΔV and the voltage Vj _De 2 across the bipolar transistor Q2 gives the reference voltage V _re f according to the following formula

The component parameters R1, R2, N and M must now be selected such that the negative temperature coefficient of the voltage V _{] De} 2 is compensated for by the positive temperature gradient of the voltage ΔV, as the following relationship shows

The value of the temperature gradient of the voltage V _De 2 is approximately minus 2mV / l ° Celsius. The formula for determining the design parameters is as follows

One of the most important circuit components in the bandgap reference voltage circuit are the resistance elements implemented by transistors M19 and M20. The error deviation of the current through the MOSFET M3 from its theoretical value 12 = N • II is determined by the following relationship (11) with l_ ₃ length of M ₃ , V _EP constant transistor parameter

This relationship is e.g. B. from the publication Laker / Sansen: "Design Of Analog Integrated Circuits And Systems", McGraw-Hill, New York (1994), which is why reference is expressly made to this publication for the purpose of disclosure. In order to minimize this mirror error, the two MOSFETs M19 and M20 are inserted. They act as quasi-constant resistors with decreasing conductance as the temperature rises. They generate at their source contacts, so at nodes C and D, a potential in the order of magnitude of the reference voltage V _rej In comparison, has the voltage on the A and B Spannungsteilerpunk¬ th value of about between 400 and 800 mV. The voltage profiles at the voltage divider point A and at the switching point C are plotted against the temperature in FIG. It can clearly be seen that the change in voltage after the temperature at the switching point C is significantly less than at the voltage divider point A, so that the current level over the entire temperature range from approximately -40 ° C. to + 160 ° C. is still sufficiently accurate to the times the mirror current in the MOSFET M3.

In contrast to the known bandgap reference voltage circuits, the circuit arrangement according to FIG. 3 does not directly regulate the reference voltage V _re f, but rather the voltage V _reg at the second voltage terminal, which is at a higher potential. In this way, disturbances in the supply voltage V ^ a at the third voltage terminal can be damped better and smaller interference amplitudes in the reference voltage V _re f can be generated. This decoupling ensures the stability of the bad gap control loop. The control voltage V _reσ at the second voltage _terminal 2 can be regulated by the adjustable current Source, as shown in Figure 3 and designated by reference numeral 4, can be set.

FIG. 4 shows a detailed circuit diagram of a bandgap interference voltage circuit according to the invention, in which the comparator K explained in connection with FIG. 3, the current source 4 and the output stage M18 are implemented using specific circuit elements. In order to avoid repetitions, only the circuit-technical differences from FIG. 3 are described below in the explanation of the circuit arrangement in FIG.

The MOSFETs M4, M5, M6, M7 and M8 shown in FIG. 4 serve as the regulated current source. Here, the MOSFETs M4, M7 and M8 are p-channel MOSFETs and M5 and M6 are n-channel MOSFETs. The MOSFET M4 is connected with one connection of its load path to the second voltage terminal 2 and with its other connection to the load path to a connection of the load path of the MOSFET M5. The other connection of the load path of this MOSFET M5 is connected to the first voltage terminal 1. The

The gate connection of the MOSFET M4 is connected to the circuit point C of the circuit arrangement, while the gate connection of the MOSFET M5 is connected on the one hand to the connection point between MOSFET M4 and M5 and on the other hand to the gate connection of the MOSFET M6. The load path of the MOSFET M6 is connected in series with the load path of the MOSFET M7, the MOSFET M6 being connected to a connection to the first voltage terminal 1 and thus to reference potential and a connection of the MOSFET M7 to the third voltage terminal 3. The connection point between MOSFET M6 and MOSFET M7 is short-circuited to the gate connection of MOSFET M7.

The control voltage V _reg at the second voltage terminal 2 is set by a regulated voltage divider consisting of the MOSFET M8 and the MOSFET M18. The connection point between MOSFET M8 and MOSFET M18, which is the output stage transistor, is also the second voltage terminal 2. The MOSFETs M9 to M16 which are also shown in FIG. 4 form the comparator K of the bandgap reference voltage circuit. The comparator K is known per se from the aforementioned publication Laker / Sansen (cf. page 577), so that reference is expressly made to this for the purposes of the disclosure.

The comparator K has four p-channel MOSFETs M9, MIO, Mll, Ml6 and M17, and four n-channel MOSFETs M12, M13, M14 and M15. Like the two MOSFETs M15 and M17, the MOSFETs Ml4 and M16 are connected in series and lie between the first voltage terminal 1 and the second voltage terminal 2. The gate connections of the MOSFETs M16 and M17 are connected to one another and at the same time connected to the connection point of the two MOSFETs M14 and M16. The series circuit of the load paths of the MOSFET M9, the MOSFET MIO and the MOSFET M12 is also connected between the first voltage terminal 1 and the second voltage terminal 2. The series connection of the load paths of the MOSFETs Mll and Ml3 is connected at the connection point of the two load paths of the MOSFET M9 and the MOSFET MIO and the first voltage terminal 1. The gate connections of the MOSFETs Ml3 and M15 are connected to one another and at the same time connected to the connection point of the MOSFETs Mll and M13. Similarly, the gate terminals of MOSFETs M12 and M14 are connected to the connection point between MOSFET MIO and MOSFET M12. The gate connection of the MOSFET M9 is connected to the node C of the circuit arrangement.

The gate connection of the MOSFET Mll is the inverting input of the comparator K and is therefore connected to the voltage divider point A. The gate connection of the MOSFET MIO is the non-inverting input of the comparator K and consequently connected to the voltage divider point B. The output connection of the comparator K is also the connection point of the two MOSFETs M15 and M17. The output connection of the grain Parator K is connected to the gate connection of the MOSFET M18.

In this circuit arrangement shown in FIG. 4, too, a constant current determined by the bandgap reference voltage circuit is impressed into the MOSFET M8. A control deviation at the voltage divider points A and B is amplified by the comparator K and corrected by changing the gate-source voltage at the MOSFET Ml8 in the output stage. The comparator K has a symmetrical input stage to reduce the comparator offset. In order to ensure stable operation of the entire control circuit, an attenuator, here an RC element, is installed between the drain connection and the gate connection of the output stage transistor Ml8. In the present case, the damping element is an RC element, the capacitor C1 of which is connected with a connection to the second voltage terminal 2 and with the second connection to the resistor R4. The free connection of this resistor R4 is connected to the gate A connection of the output stage transistor Ml8. The circuit arrangement of FIGS. 3 and 4 enables the component parameters Rl = R2 and M = 1 to be selected extremely favorably with regard to the adaptation and dimensioning of the bipolar transistors Q1 and Q2 Rl and R2 are kept very small and at the same time only a very small current can be set.

Reference list

1 first voltage terminal

2 second voltage terminal 3 third voltage terminal

M1..M30 MOSFET transistors

Ql, Q2 transistors

Rl ... R4 resistors A, B voltage divider points

C, D circuit points

Cl capacitor

V _re f reference voltage ^v reg control voltage V _DD supply voltage

VΔ voltage

ΔV ^ _g voltage

K differential amplifier device

II current 12 current

Claims

claims

1. Bandgap reference voltage circuit for generating a temperature-compensated reference voltage (V _re f) with a first and second voltage divider connected between a first and second voltage terminal (1, 2), each having a tranistor connected to the first voltage terminal (1) as a diode (Ql, Q2), the first transistor (Ql) in the first voltage divider being connected via an ohmic resistor (R1) and the second transistor (Q2) in the second voltage divider being connected directly to a voltage divider point (A, B) of the respective voltage divider and the two voltage divider points (A, B) are each connected to the second voltage terminal (2) via a resistance device, and with a differential amplifier arrangement (K) which on the output side connects to the first voltage terminal (1) with its inverting input the voltage divider point (A) of the first voltage divider and with its non-inverting input to the voltage divider point (B) of the is connected to the second voltage divider, characterized in that the resistance devices are formed by resistance elements (M19, M20) with decreasing conductance as the temperature rises, and are connected to the second voltage terminal (2) via a current mirror arrangement (M1, M2, M3) voltage divider point (B) of the second voltage divider is a resistive Wi¬ resistor (R2) is connected, which me with his free Klem¬ at which the reference voltage (V _re f) is tapped off, via the load path of a transistor (M3) to the second voltage terminal (2) is connected, the control terminal of this transistor (M3) being connected to the connection point of the current mirror (M1, M2) and a resistance element (M19) such that supply voltage terminals of the differential amplifier arrangement (K) are connected to the first and second voltage terminals (1, 2), and that a controllable current source (4) is provided which is between the second voltage terminal e (2) and a third voltage terminal (3) is connected.

2. Bandgap reference voltage circuit according to claim 1, characterized in that the transistors connected as diodes (Q1, Q2) are each bipolar transistors, the base connections and collector connections of which are short-circuited to one another.

3. Bandgap reference voltage circuit according to claim 2, da¬ characterized in that the bipolar transistors are vertical bipolar transistors in n-well technology or p-well technology.

4. Bandgap reference voltage circuit according to one of claims 1 to 3, characterized in that the resistance elements (M19, M20) are implemented by transistors.

5. Bandgap reference voltage circuit according to claim 4, characterized in that the transistors are formed as MOSFETs and looped in with their load paths in series in the respective voltage dividers and connected to the respective gate connections of the first voltage terminal (1) are.

6. bandgap reference voltage circuit according to one of Ansprü¬ che 1 to 6, characterized in that the voltage (V _req ) at the second voltage terminal (2) is selected so that the same potential is present at the voltage divider points (A, B).

7. bandgap reference voltage circuit according to one of Ansprü¬ che 1 to 6, characterized in that the current mirror (Ml, M2) is dimensioned such that through the one transistor (M2) flows N times the current of the other transistor (Ml) .

8. bandgap reference voltage circuit according to claim 7, da¬ characterized in that the component parameters of the resistors (Rl, R2), the current amplification factor (N) and that

Emitter area ratio between the two bipolar transistors (Q1, Q2) is selected so that the negative temperature coefficient between the voltage (Vj- _{) e} 2) dropping at the base and emitter of the second bipolar transistor (Q2) is compensated by the positive temperature gradient of the voltage (VΔ) dropping at the resistor (R2).

9. bandgap reference voltage circuit according to claim 8, da¬ characterized in that the ohmic resistance values of the two resistors (Rl, R2) are chosen the same and the factor M is chosen equal to 1.

10. bandgap reference voltage circuit according to one of Ansprü¬ che 1 to 9, characterized in that the voltage (V _req ) at the second voltage terminal (2) by a regulated voltage divider (M8, M18) is adjustable.

11. Bandgap reference voltage circuit according to one of claims 1 to 10, characterized in that the differential amplification arrangement (K) is connected on the output side to an output stage transistor (M18), the output stage transistor (M18) with its load path between the first Voltage clamp (1) and the second voltage clamp (2).

12. Bandgap reference voltage circuit according to claim 11, characterized in that between the second voltage terminal (2) and the gate terminal of the output stage transistor (M18) an attenuator, in particular an RC element (Cl, R4) is switched is.