Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
  • H01R4/00—Electrically-conductive connections between two or more conductive members in direct contact, i.e. touching one another; Means for effecting or maintaining such contact; Electrically-conductive connections having two or more spaced connecting locations for conductors and using contact members penetrating insulation
  • H01R4/04—Electrically-conductive connections between two or more conductive members in direct contact, i.e. touching one another; Means for effecting or maintaining such contact; Electrically-conductive connections having two or more spaced connecting locations for conductors and using contact members penetrating insulation using electrically conductive adhesives
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
  • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
  • H05K3/321—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by conductive adhesives
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W74/00—Encapsulations, e.g. protective coatings
  • H10W74/01—Manufacture or treatment
  • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W74/00—Encapsulations, e.g. protective coatings
  • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
  • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
  • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
  • H05K2201/10621—Components characterised by their electrical contacts
  • H05K2201/10674—Flip chip
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
  • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
  • H05K2201/10954—Other details of electrical connections
  • H05K2201/10977—Encapsulated connections
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
  • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
  • H05K2201/10954—Other details of electrical connections
  • H05K2201/10984—Component carrying a connection agent, e.g. solder, adhesive
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
  • H05K2203/01—Tools for processing; Objects used during processing
  • H05K2203/0195—Tool for a process not provided for in H05K3/00, e.g. tool for handling objects using suction, for deforming objects, for applying local pressure
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
  • H05K2203/03—Metal processing
  • H05K2203/0338—Transferring metal or conductive material other than a circuit pattern, e.g. bump, solder, printed component
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
  • H05K2203/05—Patterning and lithography; Masks; Details of resist
  • H05K2203/0562—Details of resist
  • H05K2203/0568—Resist used for applying paste, ink or powder
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
  • H05K3/12—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
  • H05K3/1216—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by screen printing or stencil printing
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/072—Connecting or disconnecting of bump connectors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/072—Connecting or disconnecting of bump connectors
  • H10W72/07231—Techniques
  • H10W72/07236—Soldering or alloying
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/073—Connecting or disconnecting of die-attach connectors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/073—Connecting or disconnecting of die-attach connectors
  • H10W72/07331—Connecting techniques
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/241—Dispositions, e.g. layouts
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/30—Die-attach connectors
  • H10W72/321—Structures or relative sizes of die-attach connectors
  • H10W72/325—Die-attach connectors having a filler embedded in a matrix
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/30—Die-attach connectors
  • H10W72/351—Materials of die-attach connectors
  • H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/30—Die-attach connectors
  • H10W72/351—Materials of die-attach connectors
  • H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/30—Die-attach connectors
  • H10W72/351—Materials of die-attach connectors
  • H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
  • H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/851—Dispositions of multiple connectors or interconnections
  • H10W72/853—On the same surface
  • H10W72/856—Bump connectors and die-attach connectors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
  • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
  • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
  • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
  • Y10T156/10—Methods of surface bonding and/or assembly therefor
  • Y10T156/1089—Methods of surface bonding and/or assembly therefor of discrete laminae to single face of additional lamina
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
  • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
  • Y10T156/10—Methods of surface bonding and/or assembly therefor
  • Y10T156/1089—Methods of surface bonding and/or assembly therefor of discrete laminae to single face of additional lamina
  • Y10T156/109—Embedding of laminae within face of additional laminae
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
  • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
  • Y10T156/10—Methods of surface bonding and/or assembly therefor
  • Y10T156/1089—Methods of surface bonding and/or assembly therefor of discrete laminae to single face of additional lamina
  • Y10T156/1092—All laminae planar and face to face
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
  • Y10T29/00—Metal working
  • Y10T29/49—Method of mechanical manufacture
  • Y10T29/49002—Electrical device making
  • Y10T29/49117—Conductor or circuit manufacturing
  • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
  • Y10T29/49126—Assembling bases
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
  • Y10T29/00—Metal working
  • Y10T29/49—Method of mechanical manufacture
  • Y10T29/49002—Electrical device making
  • Y10T29/49117—Conductor or circuit manufacturing
  • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
  • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
  • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion

Definitions

• This invention relates to the field of electronic interconnections in general and more specifically to a method of forming electronic interconnections and devices formed thereby.
• Computer hardware systems use printed circuit boards upon which are mounted components.
• Components are, predominantly, integrated circuit chips (ICs) usually in some level of intermediate packaging.
• ICs integrated circuit chips
• PCB printed circuit board
• Intermediate packaging that is to say, packaging layers that sit between the bare chip and the printed circuit board, have been used. Intermediate layers solve some challenges but create others.
• One problem with intermediate layers is the difficulty in establishing reliable connection between the intermediate layers and the PCB; and with the chip or chip and carrier. (Generalized representation in Figure 1). Pin connections are used to connect interposer layers. However, for high frequency applications, pin connections between the intermediate packaging and the circuit board are unsuitable because of high inductance and capacitance coupling owing to longer pin length. Connections that do not require leads (pins) have been and continue to be eagerly sought after.
• Interposer connectors were developed in an attempt to overcome the problem associated with pins or leads and intermediate packaging layers.
• Interposer connectors generally comprise conductive particles embedded in elastomeric materials. The particles extend through the elastomeric layer and, when the elastomeric layer is sandwiched between the two outer layers consisting of substrate (circuit board) and intermediate packaging, the two outer layers are electrically connected.
• interposer methods of forming the interposer have been limited to preparing the substrate with known methods such as sputtering or plating gold or nickel-silver to provide a surface for ball-bonding (depositing solder balls on one substrate surface and then assembling the two substrates).
• thermal compression bonding, laser bonding or automatic wire bonding have all been practiced. But none is recognized as a truly superior connection device.
• Wire bond studs at a 10 mil pitch have been dipped into conductive adhesive and then pressed against substrate to form a "leadless" interconnect.
• the resulting interconnect has a small footprint and promotes effective and easy underfilling.
• a ball grid array formed by such a method results in an array that is both replaceable and testable, and which eliminates coplanarity problems, even in large BGAs.
• a carrier is still required.
• wire bonding to get the studs is a slow process and can be prohibitively slow for high volume applications. For example, a high I/O application may require 900 I/O, and at a rate of three bonds per second, wire bonding alone consumes five minutes per chip. In addition, repair is completely impossible short of chiseling the chip off the substrate.
• Gel connectors (see, for example, USP 5,074,799) provide a high number of contacts and dense planar array. Gel connectors are especially attractive because gel dissipates forces impinging on the contacts. Gel also ameliorates the challenge of CTE mismatch.
• a wafer of conductive gel may be compressed between a BGA or LGA and a printed circuit board.
• AMP approach provides several advantages over that ofthe Cinapse "fuzz-button", both are basically “socket” approaches and both fail to provide complete solutions to certain key design challenges such as the reduction of large external forces as components increase in surface area.
• a method that provides for elimination of sockets is desirable; a short and compliant structure is much needed. Further, what is still needed is the elimination of the interposer/socket requirement altogether, along with the elimination of external clamping forces.
• a method is needed for providing effective electronic interconnect over large CTE mismatch and large DNPs, along with tolerance to coplananty mismatches, where such an interconnect is thermal cycle resistant. Further, the interconnect must be amenable to easy test and repair, ideally both during assembly and in the field. Furthermore, the method ought to be lead-free and no-clean.
• the invention taught herein relates to use of conductive adhesive, typically silicone with greater than 30% conductive particles by volume or similar adhesives, dispensed onto the conductive sites (wettable pads) of a substrate including chip or die followed by alignment with the conductive sites of a second substrate and assembly (attachment to another substrate) so as to provide, upon assembly ofthe two substrates, effective electronic interconnection ofthe two substrates.
• the invention further provides effective electronic interconnection over large CTE mismatch and large DNP.
• the invention further provides electronic interconnects that are thermal cycle resistant.
• the invention provides an interconnect path that supports high frequency operation, and is easy to test and repair.
• the invention provides tolerance to coplanarity mismatch. Further, the invention provides an assembly process that is lead- free and no-clean.
• Dispensing ofthe adhesive may be through stencil technique, other masking, including photoimageable or photostrippable, or through pin-transfer and related techniques.
• the invention provides easy IC chip attach to virtually any substrate, including PCB, die, or carrier. Such attach may, according to the present invention, involve assembly with wet or partially to fully cured adhesive, easy repair and testing prior to final cure, along with a variety of post-assembly curing and underfill options. Field testing and repair in devices according to the present invention is both rapid and uncomplicated.
• Fig 1 is a schematic illustrating generalized prior art chip attached to PCB.
• Fig 2 is a schematic ofthe method according to the present invention.
• FIG 3, A through C inclusive schematically depict steps of one embodiment of the inventive method taught herein, most particularly that of underfilling interconnect assemblage.
• Fig 4 is a flow chart depicting steps of one embodiment ofthe present invention.
• the invention taught herein provides short, compliant interconnects providing capabilities of elastic contact (through the use of conductive adhesive) without the need for sockets or other interposers.
• the invention provides capabilities for direct dispensing ofthe interconnect directly onto a carrier or onto the LGA or printed circuit board. Assembly between any two substrates may be performed when the interconnect material is wet, partially cured, or fully cured. After assembly, curing and underfilling may be done.
• the invention as described includes grid array (circuit) components, and printed circuits adapted to accommodate large numbers of such components as well as interconnection providing circuit function between computers and related devices.
• the inventive method is scalable, useful not only for pitches at about 6 mil, but also scalable to much larger feature sizes.
• the invention provides for assembly with low to no external pressure during and after the assembly in order for the interconnect to function.
• the invention provides for a flexible, scalable adhesive dispensing and substrate assembly protocol adaptable to the functionality characteristics required ofthe conductive device.
• the conductive adhesive can be uncured, partially or wholly cured. If attached to second substrate while uncured or partially cured, testing and repair can be performed at all stages prior to final and complete curing.
• the invention provides that "wet" assembly may be followed by cure.
• the inventive method provides a two-sided, flexible adhesive contact. Assembly when wet necessitates control of pressure and/or mechanical limiters to control spread of wet elastomer (especially with respect to contact between wet adhesive and adjacent conductors). In that method option, height limiting or spacer spheres or devices could be inco ⁇ orated into the adhesive. This "wet" approach is for more mature products where repair is not particularly important.
• the method employs a conductive adhesive 30, and a first substrate 32.
• the adhesive is dispensed 34 on a surface ofthe first substrate 32, resulting in deposits of adhesive at predetermined regions on a surface ofthe first substrate - the first substrate bearing dispensed conductive adhesive 36.
• a second substrate 38 is attached 39 to the first substrate bearing dispensed conductive adhesive 36 thereby forming an interconnected device 40 consisting of two substrates and a compliant conductive interconnect.
• the attach 39 step may be performed when the adhesive is wet, partially cured, or fully cured, depending on the desired connect characteristics or the scheme for attaching multiple chips to a comparatively large substrate such as a PCB.
• Post assembly protocols 42 for testing and repair (prior to final curing) as well as a variety of underfilling protocols are provided by the present invention.
• Suitable adhesives include those which are soft enough to be compressed by the internal forces from “underfilled” or pure underfill (see the discussion relating to Fig 3 infra).
• a suitable adhesive includes any member ofthe family of silicone adhesives or soft epoxies and similar compounds into which has been mixed conductive particles, flakes or wires (gold, carbon, silver, etc). While the isotropic nature ofthe adhesive connection simplifies the contact, the volume of conductive particles in the adhesive should not except in exceptional circumstances fall below 30%. More typical is 45 to 75% by volume conductive particles. Practical factors such as the preservation of compliance will suggest to the practitioner the appropriate volume.
• the compliance ofthe adhesive is the key factor in eliminating any need for external clamping. Selection of both adhesive and underfill should be considered with this in mind.
• Dispensing 34 of adhesive 30 may be accomplished by a variety of methods. Stenciling through a preconfigured mask, or though strippable or peelable photoimageable mask material, as well as other known stenciling methods may be selected.
• CPD Hewlett-Packard Company
• micro stenciling of conductive adhesive onto a substrate's conductive sites provides for compliant electronic interconnects without the need for external force during operation ofthe device.
• micro-stencil dispensing ofthe conductive adhesive generally includes the steps 410 of selecting a first substrate, mask and adhesive; assembling 412 the substrate and mask; aligning 414 the substrate-mask, depositing 416 the conductive adhesive, removing 424 the mask; cleaning 430 the mask; and, possibly, reusing the mask in another repetition ofthe process.
• Other embodiments eliminate the step of mask removal 424; still others include intermediate inspection 418, 426 and touch-up 420, 428 steps to ensure the regular volume of conductive adhesive and proper placement.
• the dispensing may be accomplished by "doctor-blading" or by pin-point transfer In “pin transfer” pins, needles or the like are dipped in adhesive and then the pin point is placed in contact with the substrate surface upon which the adhesive is intended to be deposited. The contact causes a dollop or footprint of adhesive to be transferred to the substrate.
• a studded die at each site it is simple to use a single studded die as a pattern to transfer (pin transfer/doctor blade) adhesive to the substrate. Unbumped die can then be aligned and attached to the pre- patterned sites.
• Curing ofthe adhesive may be performed according to any ofthe protocols illustrated above (i.e. full/partial uncured).
• a further alternative embodiment provides for a mirror image ofthe die and pin transfer ofthe adhesive to unbumped die. Any ofthe three cure options is possible.
• underfill may be used to maintain contact pressure. While possibly only a fully cured adhesive would require pressure to maintain electrical contiguity, all direct chip attach methods will benefit from environmental seal supplied by the underfill.
• Underfill for a conductive adhesive can provide more favorable characteristics that those provided by normal epoxy underfill. Without filler (solid particles) a clear underfill will shrink more on curing than a comparable filled underfill. Since conductive adhesives are highly filled, shrinkage of surrounding underfill upon curing will place conductive adhesive bumps in compression.
• Un-filled underfill due to lower viscosity, quickly wicks under the chip and does not separate. Further, un-filled underfill has a lower modulus and is less likely to cause chip breakage or stress-induced piezo electric phenomenon with large die. Low modulus reduces the need for a void-free underfill, since a low modulus bubble interface is less ofa stress riser.
• Transparent underfill can be formulated with UV cure mechanisms, to edge tack the die in place.
• Optional thermal cures can be a secondary operation after testing is complete.
• suitable underfills are cyanoacrylates, UV cured epoxy
• acrylates such as “Lite-tak” (Loctite) and other similar polymers.
• the invention provides for direct chip attach to substrate (printed circuit board, land or pad grid array, zincate die, or other substrates) without a carrier and without leads.
• Uncured adhesive may be applied to the most reliable surface, either chip or board, and the two surfaces pressed together. After assembly, practitioner may proceed with a number of process options, including underfilling and curing, as desired to meet performance characteristics. FYpmplarv Protocol
• a 1089 pin Kyocera Ceramic LGA is the substrate upon which silver-silicone adhesive (from Grace Specialty Polymers; specific gravity 3.6) is stencil printed (30 mil pads; 50 mil pitch).
• the bumped LGA is cured for one hour at 150 degrees Centigrade, under pressure of about 5-10 pounds.
• the semi-cured bumped LGA is dipped into a thin layer ofthe silver-silicone paste (wet; doctor-bladed; about 5 mils thick) so that the tips ofthe bumps are wetted by the paste.
• the LGA and the bumps thereon are aligned with and placed in contact with the conductive sites of an FR-4 PCB
• the LGA-PCB assembly is cured for one hour at 150 degrees Centigrade
• Low-viscosity underfill such as Sealant 350 from Loktite, a UV-curable modified acrylic
• Sealant 350 from Loktite a UV-curable modified acrylic

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• Engineering & Computer Science (AREA)
• Manufacturing & Machinery (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Wire Bonding (AREA)
• Electric Connection Of Electric Components To Printed Circuits (AREA)
• Connections Effected By Soldering, Adhesion, Or Permanent Deformation (AREA)

Priority Applications (3)

Applications Claiming Priority (2)

Publications (2)

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Family Applications (1)

Country Status (5)

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• 1996
  • 1996-01-26 US US08/592,042 patent/US5842273A/en not_active Expired - Fee Related
• 1997
  • 1997-01-23 DE DE69700591T patent/DE69700591T2/de not_active Expired - Fee Related
  • 1997-01-23 EP EP97902073A patent/EP0876689B1/en not_active Expired - Lifetime
  • 1997-01-23 WO PCT/US1997/001026 patent/WO1997027646A2/en not_active Ceased
  • 1997-01-23 JP JP09526973A patent/JP2000517457A/ja not_active Ceased

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